Interlaced Column-Row Message-Passing Schedule for Decoding LDPC Codes

Transcription

1 Interlaced Column-Row Message-Passing Schedule for Decoding LDPC Codes Saleh Usman, Mohammad M. Mansour, Ali Chehab Department of Electrical and Computer Engineering American University of Beirut Beirut , Lebanon {sau00, mmansour, Abstract This paper investigates efficient decoding algorithms for LDPC codes. Alternating column-row message-passing (A- CRMP) and Interlaced column-row message-passing (I-CRMP) schedules for decoding of LDPC codes are proposed and investigated in this work. Existing serial scheduling schemes for LDPC decoding are based either on column message-passing (MP) or row MP, and roughly converge twice as fast as Gallager s flooding-based MP schedule at high signal-to-noise ratio (SNR). To further accelerate the convergence speed of serial decoders, hybrid column-row MP schedules that perform multiple message passes between check and variable nodes within or between iterations are proposed. Our proposed I-CRMP schedule converges in less than half the number of iterations compared to the best existing serial decoding schedules. Compared to column MP, the added complexity of this scheme is proportional only to checknode-degree times more additions at variable nodes. This increase in complexity is moderate compared to the convergence acceleration factor that the scheme achieves. Superior performance of the proposed I-CRMP scheme is confirmed by decoding randomly generated as well as IEEE n/ac LDPC codes. Index Terms LDPC Codes, turbo-decoding of LDPC codes, Gallager s algorithm, IEEE n/ac I. INTRODUCTION LDPC codes have become the coding scheme of choice for high performance error correcting codes in many applications owing to their near-optimal performance [1]. They have been incorporated in numerous present and upcoming IEEE standards like n/ac/ax (WiFi), ad (WiGig) [2], [3], among others. Compared to turbo codes [4], LDPC codes provide an attractive additional feature of inherent parallel structure at the decoder, and therefore are better suited for present and future high throughput applications. For LDPC decoding, mainly two types of schedules are employed. One is Gallager s standard message-passing (SMP) technique, known as the flooding schedule [5], and which consists of two distinct phases. In one phase, all variable nodes are updated, and then in the second, all the check nodes are updated. This technique was originally proposed by Gallager [5], and later used by Mackay [6] in his rediscovery of LDPC codes. The SMP algorithm has the advantage that computations in each phase are inherently parallel, a feature that can be fully exploited to design high-speed fully parallel LDPC decoder architectures. However, in practical implementations, routing congestion between various processing elements and large silicon footprint associated with such a fully parallel hardware solution limit the LDPC block lengths that can be supported. In the second type, known as serial decoding, message computations carried out in one phase (say variable nodes) are immediately propagated to the other phase (check nodes in this case). This immediate information exchange between the two phases improves the convergence speed of serial decoders by roughly a factor of two compared to SMP decoders at high signal-to-noise ratio (SNR). Serial decoders are further divided into two types, known as row message-passing (RMP) decoders [7] and column message-passing (CMP) decoders [8], based on whether the row or column order of the parity-check matrix is followed in the decoding process. In the RMP schedule, decoding starts from the first check node and computed messages are immediately passed back to connected variable nodes. This process is repeated one by one for all the check nodes. Immediate propagation of messages computed at check nodes back to variable nodes enables future check nodes to have access to the most updated message nodes, thus accelerating the convergence rate. A turbo-decoding scheduling scheme for LDPC decoder based on RMP was first introduced in [7], [9], and further analyzed in [10]. Other variations of this scheme later appeared in the literature (e.g., [11]). In all of these works, it was demonstrated analytically and through simulations, that RMP schedule take on average half the number of iterations at high SNR to converge compared to SMP. In CMP scheduling, decoding starts in reverse order compared to SMP, by computing messages first at variable nodes and then messages are immediately exchanged with connected check nodes. This scheme achieves almost the same bit errorrate (BER) performance as RMP. CMP was proposed in [8] and [12], and it was shown that this schedule also converges in half the number of iterations compared to SMP. These serial decoders provide faster convergence without introducing any significant complexity overhead, i.e., the number of computations remains almost constant in one iteration of serial decoders as in SMP. An added advantage of serial decoders is that they can be implemented in a memory efficient way, requiring significantly lower memory than SMP [7], [9]. To further improve the convergence rate from 2 over the SMP, hybrid scheduling schemes that combine both the CMP and RMP schemes are being proposed in this paper. Two /16/$ IEEE

2 alternatives, named as Alternating Column-Row Message- Passing (A-CRMP) and Interlaced Column-Row Message- Passing (I-CRMP) schemes are considered. A-CRMP scheme is based on decoding messages such that one iteration is done by CMP and the next iteration is done by RMP. This pattern of alternating CMP and RMP is repeated over all iterations. I-CRMP scheme, which is more complex, starts from the first variable node and propagates its values to connected check nodes, as in CMP. After updating these check nodes, I-CRMP moves one step forward than CMP and propagates these updated check nodes values to their connected variable nodes, as in RMP. This scheme converges in less than half the number of iterations compared to CMP and RMP, and also provides performance improvement in terms of BER. Radosavljevic et al have also introduced a row-column MP schedule in [13] by combining RMP and CMP in a way that the variable and check nodes are updated single element by single element through a random walk. This scheme is fundamentally different from schemes proposed in this work since variable and check nodes are updated in a deterministic way rather than a random way in our proposed schemes. Also the performance of Radosavljevic s [13] scheme shows no improvement to CMP or RMP. A joint row-column decoding algorithm is presented in [14] as well. However, in this decoding algorithm, the authors have named the RMP process of updating the variable nodes by check nodes as joint row-column decoding, but in essence, it is the same schedule as RMP. These schemes actually do not go beyond the basic theme of existing serial decoders, i.e., the process of exchanging extrinsic information between nodes in one step, and hence their performance is the same as that of CMP or RMP. While the I-CRMP scheme proposed in this work uses a two-step process of exchanging extrinsic information between processing nodes, which actually leads to a faster convergence speed and lower bit error-rate. The remainder of the paper is organized as follows. Background material related to SMP, RMP, and CMP is presented in Section II. The proposed CRMP schemes are introduced in Section III. Complexity analysis of the proposed I-CRMP scheme is carried out in Section IV. Convergence analysis of I-CRMP is presented in Section V. Simulation results are depicted in Section VI. Finally, Section VII concludes the paper. II. BACKGROUND LDPC codes are either defined by a sparse parity-check matrix (SPCM), or represented by a sparse bipartite Tanner graph consisting of variable nodes and check nodes. Variable nodes in the Tanner graph represent columns of the SPCM, and check nodes are associated with rows of the SPCM. Consider an LDPC code having N V variable nodes and N C check nodes in its associated Tanner graph G. Letd v denote the degree of variable node v, d c the degree of check node c in the graph. Let P vc represent the message computed at variable node v corresponding to the check node c, and L cv be the message computed at check node c associated with variable node v. Message computations based on the standard message-passing scheduling algorithm is described next. A. Standard Message-Passing (SMP) Algorithm The SMP scheduling based on a flooding scheme updates the variable nodes and check nodes in two phases as follows (e.g., see [7]). Two types of messages will be updated and exchanged: L cv refers to the message sent from check node c to variable node v, and P vc refers to the message sent from variable node v to check node c: Initialization: Initialize all variable node messages to the received channel LLRs P vc (0) = LLR[v], v G. (1) Phase 1: Update all check node messages at iteration k 1 according to L cv (k) =Ψ 1( ( )) P (k 1) Ψ, c G, (2) v R[c] v where Ψ(x) 0.5 log(tanh(x/2)) = Ψ 1 (x). Theset R[c] denotes the set of d c = R[c] variable nodes connected to check node c. Note that the notation R[c] v indicates that the summation does not include the previous message from variable node v that is set to receive the new updated message L cv from check node c. Phase 2: Update all variable nodes at iteration k 1 using the equation ( ) P vc (k) = LLR[v]+ L (k) c v, v G, (3) c C[v] c where C[v] is the set of d v = C[v] check nodes connected to the variable node v, and LLR[v] is the loglikelihood ratio (LLR) of the received channel value of variable node v. As in Phase 1, the summation does not include the previous message from neighboring check node c which the variable node is connected to. For decision making in the final iteration, all neighboring check node messages are included in the summation when evaluating (3), i.e., none of the check nodes are excluded: ( Λ[v] LLR[v]+ c C[v] v c L (K) c v ), v G. (4) Here, the Λ s denote updated channel LLR values at the end of the final decoding iteration. Hard decisions on the bits are then made based on the sign of the Λ LLR values. B. Column Message-Passing (CMP) Algorithm This scheduling starts from the first variable node and computes its message using equation (3). Then, instead of proceeding to the second variable node, all check nodes connected to this variable node are updated first using equation (2) without waiting for the next iteration. This process of evaluating each variable node and immediately updating connected check nodes is repeated for all variable nodes in one iteration. Decision making process in the final iteration is based on evaluating (4) as in SMP. Figure 1(a) illustrates the processing schedule of this scheme for the first variable node.

3 CMP or RMP. It is found through preliminary simulations (shown in Section VI) that the performance of such a scheme is almost the same as that of CMP or RMP. The result, together with other experimental simulations pertaining to the SMP algorithm, highlight the following two observations: A scheduling process that involves computing all messages pertaining to one class of nodes at once using only old messages from the other class of nodes, without accounting for newly generated interim messages from the second class, essentially attains a similar performance as that of the SMP schedule. Fig. 1. CMP and RMP schedules: (a) CMP for first variable node (b) RMP for first check node. C. Row Message-Passing (RMP) Algorithm In row message-passing, decoding proceeds row-wise instead of column-wise, i.e., check-node messages are computed using (2), and then all of its connected variable nodes are updated immediately using equation (3). This process is repeated for all check nodes, in one iteration. Compared to CMP, this scheme has the advantage that it only involves addition computations at variable nodes that are much less expensive than check-node computations (which involve the non-linear function ψ). Moreover, this scheme can also be implemented in a memory-efficient way [9]. The processing schedule of this scheme for the first check node is illustrated in Fig. 1(b). D. Row-Column Message-Passing (RCMP) Algorithm There are some scheduling schemes in the literature that are based on a hybrid combination of CMP and RMP, but in essence, they are the same schemes as CMP or RMP, and their performance is essentially the same. For instance in [13], a row-column message-passing scheme is presented which combines RMP with CMP. The process of updating the variable-node and check-node messages in this scheme is done single element by single element through a random walk in the graph, but the convergence speed of the scheme is almost the same as that of CMP or RMP. Similarly in [14], a joint row-column decoding scheme is presented. The authors have named the RMP process of updating variable nodes by check nodes as joint row-column decoding, but actually this is the same algorithm as in [7], which is RMP. III. PROPOSED COLUMN-ROW MP SCHEMES Two scheduling techniques for variable-node and checknode message computations have been proposed and investigated in this work, with the aim of further accelerating the convergence rate of LDPC decoding. A. Alternating CRMP The first proposed scheme, referred as Alternating-CRMP (A-CRMP), is based on the idea of performing computations in one iteration using CMP and in the second iteration using RMP, and keep alternating between CMP and RMP throughout the iterative process. The scheme could be started from either On the other hand, a scheduling process that serializes the message computations of one class of nodes to account for newly updated messages from the other class of nodes, but still updates the neighboring nodes in the other class in parallel, essentially attains a similar performance as that of the RMP or CMP schedules. Hence, no major improvements can be achieved by investigating other variants of the SMP or RMP (CMP) schedules. B. Interlaced CRMP Based on the above observations, scheduling schemes that interlace between variable node and check node computations within one iteration are proposed and investigated. This Interlaced-CRMP (I-CRMP) schedule extends the process of exchanging extrinsic between nodes, to two steps within an iteration, and will be referred to as an order-2 update scheme. It is motivated by the following observation: A scheduling process that serializes both the node message computations of one class of nodes as well as the message computations within each node benefits from using the most up to date messages to update future nodes, and hence is expected to achieve better convergence rate. To elaborate further, the I-CRMP schedule combines row and column scheduling in a way such that the process of exchanging information between nodes is done in two steps, i.e., from variable nodes to check nodes and then back to variable nodes, within one iteration. Referring to Fig. 2(a), this starts by doing processing at one variable node, say the first one v 1, using (2). Then, only the first check node c 1 from the set of neighbors of the first variable node v 1 is updated using (3). Processing so far up to this point is similar to CMP. Next comes the part which makes the proposed scheme different than CMP, and essentially amplifies the convergence speed of CMP by that of RMP. Before moving to do computations at the second neighboring check node c 3 of v 1, the newly computed message from the first check node c 1 is further propagated to its connected variable nodes, excluding the one which originally propagated its value to this check node. After this, the second check node from the set of neighbouring check nodes of first variable node is updated, as shown in Fig. 2(b) and its value is similarly propagated to its connected variable nodes. The processing schedule of this scheme for the first variable node is depicted in Fig. 2.

4 Fig. 2. I-CRMP schedule for 1st variable node: (a) 1st connected check node is updated which further updates its connected variable nodes. (b) 2nd connected check node is updated which further updates its connected variable nodes. This process of performing computations on check nodes and immediately propagating newly generated messages to connected variable nodes is repeated for the complete neighbouring set of check nodes of first variable node. Since these check nodes are being updated serially, later check nodes now have access to the variable nodes updated by earlier check nodes. This second part of our schedule, which is similar to RMP thus combines the convergence acceleration effect of both the CMP and RMP. This completes the sub-cycle of information exchange that started from the first variable node and concluded also at some set of variable nodes, depending on the structure of the SPCM. N V such sub-cycles are repeated, one for each variable node, in one iteration. So in summary: One sub iteration of I-CRMP involves a variable node update, followed by serial updates of all the connected check nodes of the variable node and further propagation of the check nodes values to their neighbouring sets of variable nodes. Sub-iterations equal to number of variable nodes, one for each variable node, make one iteration of I-CRMP. This will add degree-of-checknode times more additions in one iteration of I-CRMP, compared to one iteration of CMP. The analog of this schedule would be Interlaced-Row- Column MP (I-RCMP). This will start from the first check node, update its connected variable nodes which will further propagate the new values back to their connected check nodes. But the disadvantage of this schedule will be the extra nonlinear computations at check nodes which are much more expensive than variable node computations. Hence we focus in this work on the I-CRMP schedule, but nevertheless, the techniques presented here apply to both schemes and the performance of the two schedules will essentially be the same. The pseudocode of the complete I-CRMP algorithm is summarized in Algorithm 1. Experimental simulation results presented in Section VI demonstrate the superior performance of I-CRMP over existing schedules. IV. COMPLEXITY ANALYSIS For simplicity of exposition, complexity analysis of the CMP schedule is presented first and then it is extended to the Algorithm 1 Interlaced CRMP Schedule 1: for all c, v G do initialization loop 2: L (0) cv 0 3: end for 4: for k =1to K do iteration loop 5: for j =1to N V do variable nodes loop 6: P v (k) jc i Eq. (3) for all c i C[v j ] 7: for i =1to d vj such that c i C[v j ] do Eq. (2) for all v R[c i ] v j 9: for all v R[c i ] v j do 10: P v c Eq. (3) for all c C[v ] 11: end for 12: end for 13: end for 14: end for 15: for all v G do Decision making 16: Λ[v] Eq. (4) 17: end for 8: L (k) c iv proposed I-CRMP schedule. It is reiterated that I-CRMP is selected for complexity analysis, instead of I-RCMP to avoid the disadvantage of extra non-linear computations at check nodes which are much more expensive than variable node computations. The differences between CMP and I-CRMP are elaborated by performing direct comparisons between the two, throughout the analysis steps. Regular variable and check node degrees are assumed here. A. Computational Complexity of CMP In column message-passing, decoding process starts from the first variable node by computing values for all of its connected check nodes. If d V is the degree of the variable node, then this variable node performs d V computations. These values are then propagated to the associated check nodes, which are of course d V in number. Each of the associated check node then updates its values for all of its connected variable nodes excluding the one it received the message from. In doing so, each check node will do (d C 1) computations and there are d V check nodes connected to one variable node. For one variable node, d V variable node computations and d V (d C 1) check node computations are performed. This process is repeated for all the N V variable nodes. Let V CMP and C CMP denote the number of variable and check nodes computations of the CMP schedule, respectively. Then the total numbers of computations for one iteration is: V CMP + C CMP = N V d V + N V d V (d C 1). (5) Variable and check node computations are given separately because former are simply additions and are much less expensive than their check node counterparts. B. Computational Complexity of I-CRMP For the proposed I-CRMP scheme, the values computed in CMP at check nodes are further propagated to all of their connected variable nodes as explained in Section III.

5 Compared to CMP, this incurs additional computations at variable nodes. Each variable node connected to a check node will add one more addition in log domain and there will be d V (d C 1) variable nodes in total to be updated. This process will be repeated for all of the N V variable nodes. Therefore, the additional computational cost of using this scheme is N V d V (d C 1) more additions compared to CMP decoding. If V CRMP and C CRMP are the variable and check node computations of the I-CRMP algorithm, respectively, then the total number of computations for one I-CRMP iteration is: V CRMP +C CRMP = N V d V d C +N V d V (d C 1). (6) As it can be seen, the number of check-node computations for this scheme is the same as that for CMP decoding since check node values are only propagated and no additional computations are performed at check nodes. The increased cost of this scheme is simply the extra additions at variable nodes, which are much less expensive than check-node computations. V. CONVERGENCE ANALYSIS The convergence speed of an LDPC decoding schedule is directly related to the number of times the channel LLRs at variable nodes are updated by neighboring check nodes. Hence, the convergence speed of the proposed I-CRMP scheme is analyzed based on the number of times variable nodes are updated in one I-CRMP iteration, by new messages from check nodes, and compared directly with RMP decoding. Since the convergence behavior of RMP and CMP is almost the same, RMP is chosen here to compare directly against. The RMP schedule starts its message computations at the first check node and updates all its corresponding variable nodes. This process is repeated by doing computations at check nodes based on updated variable nodes and updating back their connected variable nodes. As one check node is connected to d C variable nodes, and there are N C check nodes in total, so there will be N C d C variable-node updates by check nodes, in one iteration. If U RMP is the total number of variable nodes updates by check nodes in one iteration of row decoding then it will be given by: U RMP = N C d C. (7) The I-CRMP schedule starts by computing messages at the first variable node and updating immediately its connected check nodes. These check nodes serially update their values based on the received message from the variable node, and propagate the new check messages to their connected variable nodes one by one. As the schedule proceeds by taking one variable node a time, and connected to each variable node are d V check nodes and each check node updates back (d C 1) variable nodes, so for one variable node, d V (d C 1) updates of variable nodes are performed by check nodes. Since there are N V variable nodes in total, so there will be N V d V (d C 1) variable node updates by check nodes, in one iteration. If U I-CRMP denotes the total number of variable nodes updates by check nodes in one I-CRMP iteration, then: U I-CRMP = N V d V (d C 1). (8) In [13], the logarithm of the ratio of N RMP to N SMP is taken as convergence acceleration factor of RMP to SMP, where N SMP and N RMP are number of check node messages, updated in the previous iteration and utilized in the computation of one variable node during the current iteration of SMP and RMP, respectively. Number of variable nodes updates performed by all the check nodes of current iteration are compared here instead of counting the number of utilized check nodes updated previously. So the convergence acceleration factor α of I- CRMP to RMP using our approach will be the log ratio of U I-CRMP and U RMP and using eqs. (7) and (8) is given by: ( ) ( UI-CRMP NV d V (d C 1) α log =log U RMP N C d C ). (9) For rate-half LDPC codes with d C =2 d V, this convergence factor simplifies to: α =log(d C 1). (10) Since this ratio factor is greater than one, our proposed I- CRMP scheme converges faster than RMP. Since, the convergence speeds of RMP, CMP, and A-CRMP are almost the same, our proposed I-CRMP scheme converges faster than these existing LDPC serial decoding schedules. VI. SIMULATION RESULTS To study the potential advantages of the proposed I-CRMP scheme in terms of convergence speed and BER performance, five message passing schedules, viz. SMP, RMP, CMP, A- CRMP, and I-CRMP were simulated. The bit-error rate (BER) curves and number of iterations taken by each algorithm are plotted for rate-1/2 randomly generated LDPC codes and for n/ac LDPC codes. The maximum number of iterations was fixed and annotated against each plot in the figures. As shown in the plots, fast convergence rate and lower bit error rate of I-CRMP is verified consistently by these simulation. Also, it is evident that the performance of A- CRMP is almost the same as other serial decoding schedules. To get further insight into the performance offered by the proposed I-CRMP scheme, computations taken by CMP and I-CRMP for IEEE n/ac, rate 1/2 LDPC codes are tabulated in Tables I and II, corresponding to Figures 5 and 6. It is confirmed from these calculations that at high SNR, I- CRMP requires less than half the number of variable and check nodes updates (V. Updates and C. Updates) compared to CMP, with degree of check node times more additions. The extra additions could be justified by lower BER, additionally offered by I-CRMP, evident from BER columns of Tables I and II. TABLE I CMP COMPUTATIONS FOR RATE 1/2, N/AC LDPC CODES Eb/No Avg. Itrs. V. Updates C. Updates BER

6 Fig. 3. BER comparison of proposed schedule with other schedules for (3,6)(500,1000) randomly generated LDPC codes with max iterations of 100. Fig. 4. Iterations comparison corresponding to Fig. 3. VII. CONCLUSIONS Alternating and Interlaced column-row MP (A-CRMP and I-CRMP) schedules for decoding of LDPC codes have been proposed and investigated. It has been shown that by performing multi-hop message-computations between variable and check nodes within the same iteration, the convergence speed of the iterative decoding process can be accelerated compared to existing serial decoding schedules. Alternatively viewed, for a given fixed number of iterations (and hence processing Fig. 5. BER comparison of proposed CRMP schemes with other MP schedules for rate 1/2, n/ac LDPC Codes with max iterations of 100. Fig. 6. Iterations comparison corresponding to Fig. 5. TABLE II I-CRMP COMPUTATIONS FOR RATE 1/2, N/AC LDPC CODES Eb/No Avg. Itrs. V. Updates C. Updates Additions BER throughput), the BER performance can be improved. It was shown also that these improvements cannot be achieved if these multi-hop message computations are done at the iteration level, as is the case for RMP, SMP and the A-CRMP schemes. These advantages have been demonstrated both analytically and through simulations. Finally, through complexity analysis, it has been shown that the added cost of this scheme is simply more addition operations at variable nodes, which is minimal. REFERENCES [1] D. J. MacKay and R. M. Neal, Near shannon limit performance of Low-Density Parity-Check codes, Electron. Lett., vol. 32, Aug [2] IEEE standard for local and metropolitan area networks part 11: Wireless LAN (MAC) and physical layer (PHY), no , [3] IEEE draft standard for information technology-wireless lans-part 21: mmwave PHY specification, no ad, May [4] C. Berrou, A. Glavieux, and P. Thitimajshima, Near shannon limit error correcting coding and decoding: Turbo codes, in IEEE Workshop on Signal Processing Systems (SiPS02), pp , Oct [5] R. G. Gallager, Low-Density Parity-Check Codes, [6] D. MacKay, Good Error-Correcting Codes based on Very Sparse Matrices, IEEE Trans. Inf. Theory, vol. 45, [7] M. Mansour and N. Shanbhag, High-throughput LDPC decoders, IEEE Trans. VLSI Syst., vol. 11, pp , [8] J. Zhang and M. Fossorier, Shuffled belief propagation decoding, in Proc. Asilomar Conf. Signals, Systems and Computers, Nov [9] M. M. Mansour and N. R. Shanbhag, Memory-efficient turbo decoder architectures for LDPC coding, in Proc. IEEE Int. Conf. Commun. (ICC), pp , [10] M. Mansour, A Turbo-decoding message-passing algorithm for Sparse Parity-Check Matrix codes, IEEE Trans. Signal Process., vol. 54, [11] E. Sharon, S. Litsyn, and J. Goldberger, An efficient message-passing schedule for LDPC decoding, in 23rd IEEE Convention of Electrical and Electronics Engineers, pp , Sep [12] H. Kfir and I. Kanter., Parallel versus sequential updating for belief propagation decoding, Physica A: Statistical Mechanics and its Applications, vol. 330, no. 1, pp , Dec [13] P. Radosavljevic, A. Baynast, and J. R. Cavallaro, Optimized message passing schedules for LDPC decoding, in Proc. Asilomar Conf. Signals, Systems and Computers, pp , [14] Z. He, S. Roy, and P. Fortier, FPGA implementation of LDPC decoders based on joint row-column decoding algorithm, in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 2007.