ISSN Vol.08,Issue.07, July-2016, Pages:

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1 ISSN Vol.08,Issue.07, July-2016, Pages: Low Power Asynchronous Domino Logic Pipeline Strategy Using Synchronization Logic Gates H. NASEEMA BEGUM PG Scholar, Dept of ECE, Santhiram Engineering College, Nandyal, AP, India. Abstract: This paper presents a novel design method of asynchronous domino logic pipeline, which focuses on improving the circuit efficiency and making asynchronous domino logic pipeline design more practical for a wide range of applications. The data paths are composed of a mixture of single-rail and dual-rail domino gates. Dual-rail domino gates are limited to construct a stable critical data path. Based on this critical data path, the handshake circuits are greatly simplified, which offers the pipeline high throughput as well as low power consumption. Moreover, the stable critical data path enables the adoption of single-rail domino gates in the noncritical data paths. This further saves a lot of power by reducing the overhead of logic circuits. Synchronization logic gates, which have no data dependency problem, are used in the design to construct the reliable data path. Three phase dual-rail precharge (TDPL) logic is used for evaluating the proposed pipeline method. A high-throughput and ultralowpower asynchronous domino logic pipeline design method, targeting to latch-free and extremely fine-grain or gate-level design. Keywords: Asynchronous Pipeline, Critical Data Path, Dual- Rail Domino Gate, Single-Rail Domino Gate. I. INTRODUCTION Nowadays, clock design becomes an obstacle to high performance VLSI systems. With technology scaling, the clock ditribution remains an important challenge with requirement of high speed and low-power in VLSI system design[1][8]. Asynchronous designs, which replaces the externally supplied global clock with a local handshake, has the potential to make high-performance design more feasible. Due to the local handshake, asynchronous systems avoid issues related to clock distribution such as large clock power and difficult management of clock skew. Moreover, the operating speed of asynchronous system is determined by actual local latencies rather than global worest-case latency, which supplies a higher operating speed and better elasticity. Asynchronous domino logic pipeline is an intresting pipeline style that can entirely avoid explicit storage elemnets between stages by exploiting the implicit latching functionality of domino logic gates. The latchless featurer provides the benefits of reduced critical delays, smaller silicon area, and low power consumption. However, asynchronous domino logic pipeline has a common problem that dual-rail domino 2016 IJATIR. All rights reserved. logic pipeline has to be used to compose the domino data path. Single-rail domino logic cannot be used because it would be break the domino path since only noninverting logic can be implemented[9]. As a result, the domino data path has a dual-rail encoding overhead that consumes a lot of silicon area and power consumption. This paper presents a novel design method of asynchronous domino logic pipeline, which focuses on improving the circuit efficiency and making asynchronous domino logic pipeline design more practical for a wide range of applications. To obtain high throughput, the design targets extremely fine-grain or gate level pipelining, where the depth of every pipeline stage is only one dualrail dynamic logic[11]. Moreover, the handshake control logic is greatly simplified with a reliable critical data path which is constructed by using synchronicing logic gates[2]. The reduced handshake overhead not only increases the throughput but also decreases the power consumption. A further feature of the proposed design is that explicit latches or registers are not used. The dynamic logic gates themselves provide an implicit latch function with a careful sequencing of handshake control. The removal of explicit latches or registers provides benefits of smaller forward latency, smaller silicon area, and low power consumption. Based on the features of the design we name the proposed asynchronous pipeline as Asynchronous Pipeline based on a constructed critical data path (abbreviated APCDP). TABLE I: Code Table of the Four-Phase Dual-Rail Encoding The paper is organized as follows. Section II introduces the previous work. A deatiled background on PS0, a classic dual-rail dynamic asynchronous pipeline implementation style is introduced, followed by a recent improved approch LP2/2. Section III focuses on the design of APCDP. SLGs

2 and the extended design, Synchronizing Logic Gates with a Latch functions (SLGL), are introduced to construct the reliable critical data path. A simple analysis of the robustness of the structure is also provided. Section IV focuses on comparison parameters of the pipeline structures. Section V presents the conclusion. Fig.1. Block diagram of PS0. II. PREVIOUS WORK PS0 is a well-known implementation style of asynchronous domio logic pipeline ased on dual-rail protocal[3]. It is an important foundation for later proposed styles. Since our proposed pipeline is also based on PS0, we will begin by reviewing PS0 pipeline style, and then simply introducing two other advanced styles: 1) a timing-robust style called precharge half-buffer [4] and 2) a high-throughput style called look-ahead pipeline[5]. A. Williams PS0 Pipeline Four-phase Dual-Rail Protocol: PS0 is designed based on the four-phase dual-rail protocal. Fig.3 shows an example of data transfer based on the four-phase dual-rail protocol, and tablei shows the code table of the four-phase dual-rail encoding.the four-phase dual-rail encoding encodes a request signal into the data signal using two wires,(w_t,w_f). The data value 0 is encoded as (0,1), and value 1 is encoded as (1,0); the spacer is encoded as (0,0); (1,1) is not used. When transfering the valid data, a spacer is inserted between them. A receiver can easily obtain the valid data by monitoring the two wires. This protocol is very roboust since a sender and a receiver can communicate reliably regardless of delay in the combinational logic block and wires between them. The dualrail encoded datapath is known as the delay-insensitive data path. H. NASEEMA BEGUM gate and the 2-bit completion detector. A two-input NOR gate serves as the 1-bit completion detector to generate a bit done signal by monitoring the outputs of dual-rail domino gate. To build a 2-bit completion detector, C- element is needed to combine the bit done signals. A full completion detector is formed by combing all bit done signals from the entire data paths with a tree of C-elements, as shown in fig. 1 Protocal of PS0: The protocol of PS0 is quite simple. F(N) is precharged when F(N+1) finishes its reset, or precharege. In fig. 1, if we observe a single data flow through an initially empty pipeline in wich every pipleine stage is in evaluation phase, the compete cycle of events is as follows. F1 evaluates and data flow to F2. F2 evaluates and data flow to F3. F2 s completion detector detects completion of evaluation and sends a precharge signal to F1. F1 precharges and F3 evaluates. F3 s completion detector detects completion of evaluation and sends a precharge signal to F2. F2 precharges. F2 s completion detector detects the completion of precharge and sends an evaluation signal (enable signal) to F1. The evaluation signal enales F1 to evaluate new data once again. Overhead Problems: There are mainly two overhead problems that prohibit the widespread use of PS0, the detection overhead in handshake control logic and dual-rail encoding overhead in function block logic. A ripple carry adder, shown in fig. 4, is used as an example to clarify these overhead problem. In a 4-bit ripple carry adder, 18 dual-rail domino buffer gates are added, which almost cancel out the benefit of removing explicit storage elements. Fig.2. (a) Dual-rail domino AND gate (b) Two-bit completion detector. Structure of PS0: Fig. 1 shows a block diagram of PS0. In PS0, each pipeline stage is composed of a function block and a completion detector. Each function block is implemented using dual-rail domino logic. Each completion detector generates a local handshake signal to control the flow of data through the pipeline. The handshake signal is transferred to the precharge/evaluation control port of the previous pipeline stage. Fig 2 shows an example of the dual-rail domino AND Fig.3. Example of data transfer based on four-phase dual-rail protocol.

3 Low Power Asynchronous Domino Logic Pipeline Strategy Using Synchronization Logic Gates handshake control logic, the overhead problem in function block logic remains unsolved since dual-rail domino logic still has to be used to compose the domino data path [6]. Fig.4. Pipelined 4-bit ripple carry adder. B. Other Advanced Pipelines Precharge Half-Buffer Pipeline: Fig. 5 shows a block diagram of PCHB. PCHB is a timing-robust pipeline style that uses quasi-delay-insensitive control circuits [4]. Two completion detectors in a PCHB stage: one on the input side (Di) and one on the output side (Do). The complete cycle of events for a PCHB stage is quite similar to that of PS0, except that PCHB verifies its input bits. This design makes PCHB more timing robust; it causes a two-time overhead in handshake control logic compared with PS0. Fig.6. Block diagrams of LP2/2. (a) LP2/2 based on dual-rail protocol, (b) LP2/2-SR. III. ASYNCHRONOUS PIPELINE BASED ON CONSRUCTED CRITICAL DATA PATH Fig7 shows the block diagram of the proposed asynchronous pipeline (APCDP). The pipeline is designed based on a stable critical data path that is constructed using special dual-rail logic. The critical data path transfers a data signal and an encoded handshake signal. Noncritical data paths, composed of single-rail logic, only transfer data signal. A static NOR gate detects the dual-rail critical data path and generates a total done signal for each pipeline stage. The outputs of NOR gates are connected to the precharge ports of their previous stages. As a result, APCDP has a small overhead in both handshake control logic and function block logic, which can greatly, increases the throughput and power consumption. Fig.5. Block diagram of PCHB. LP2/2: LP2/2 is a high throughput pipeline style [5], which has both dual-rail and bundled-data protocol design. LP2/2 improves the throughput of PS0 by optimizing the sequential of handshake events. However, they do not solve the overhead problems in handshake control logic and functional block logic. Although this pipeline structure reduces the handshake cycle time, the asymmetric completion detectors still consume a lot of power since they have to detect the entire data paths. Fig 6(b) shows the bock diagram of LP2/2 based on bundleddata protocol (LP2/2-SR). LP2/2-SR avoids the detection overhead problem by implementing a single extra bundling signal. The bundling signal serves as a completion signal, which matches the worst case delay in functional blocks. Although such design reduces the power consumption in Fig.7. Block diagram of APCDP. The solid arrow represents a constructed critical data path, the dotted arrow represents the noncritical data path,

4 H. NASEEMA BEGUM and the dashed arrow represents the output of single to dualrail encoding converter as shown in Fig.8. The structure of asynchronous pipeline can be divided into following modules, SLG (Synchronizing logic gate) SLGL (Synchronizing logic gate with latch function) S to D converter (single-rail to dual-rail converter) S logic(single-rail logic) Fig.10. Encoding converters and truth table of encoding converter. Fig.8. Synchronizing AND gate and the truth table of dualrail and logic. Synchronizing Logic Gates: The synchronizing logic gates (SLG) are dual-rail domino gates that have no gate-delay and data dependence problem by making sure that that SLG cannot be activated until all inputs are valid [11]. Fig.9. Synchronizing AND gate with a latch function and the table of the latch states. SLGL: Based on the characteristics of SLGs, SLGLs are extended. Fig.9 shows synchronizing AND gate with a latch function and the table of the latch states. The slowest gate in a pipeline stage might be early triggered by outputs from previous pipeline stage. Then, SLGL are extended to solve it. The principle is that SLGLs cannot start evaluation without the presence of the enable signal. S to D Converter: In order to avoid the data transfer error, the encoding converters are used with a timing assumption. The encoding converters are used to bridge the connection between single-rail and dual-rail domino gates as shown in Fig.10. Fig.11. Structure of APCDP. S Logic: The single-rail logic (S logic) is applied in the non-critical data path in APCDP pipeline and it cannot implement an odd number of inversions as shown in Fig.11. If using a NOT gate to implement the complementary logic, the initial high voltage signal in precharge phase would broke the domino path. Therefore, this single rail logic can be only applied in the non-critical data path and which is converted to dual-rail path using the encoding converters. IV. SIMULATION RESULTS Proposed pipeline and existing pipeline both pipeline process based on PS0 pipeline style. The PS0 simulation result shown in Fig 12 and it is based on a delay assumption that each pipeline stage s predecessor precharges no slower than the stage s successor evaluates. Fig.12. PS0 wave form.

5 Low Power Asynchronous Domino Logic Pipeline Strategy Using Synchronization Logic Gates PCHB is the timing robust pipeline design. It works in parallel processing. It will start the evaluation only if all the inputs are valid as shown in Fig.13. It doesn t require any delay assumption by the designer. PCHB based on PS0 pipeline method. Fig.16. SLG Layout. TABLE II: Comparison of Parameters Fig.13. PCHB wave form. The robustness comes at the expense of performance. Also the simulation results of LP2/2 and APCDP are given in Fig.14 and Fig.15. We have done the analysis of these pipeline structures with different parameters such as average power consumption, Area, Power Delay Product. Fig.14. LP2/2-SR wave forms. Fig.16 shows the synchronizing logic gates layout. These critical data path solve the gate delay and data dependence problems. The slowest gate in a pipeline stage might be early triggered by outputs from previous pipeline stage. Then, SLGL are extended to solve this problem. Fig.15. APCDP wave form. Table II shows the comparison of parameters between PCHB, LP2/2 and APCDP Structures. From this table we can conclude that the proposed pipeline method APCDP consumes less power when compared to the other methods. V. CONCLUSION This paper introduced a novel design method of asynchronous domino logic pipeline. This pipeline is realized based on a constructed critical data path (SLG/SLGL). The design method greatly reduces the overhead of hand shake control logic as well as functional block, which not only increases the pipeline throughput but also decreases the power consumption. The power delay product is also reduced in the proposed APCDP method. The evaluation results show that the proposed design has better performance than a bundled-data asynchronous domino logic pipeline (LP2/2-SR). VI. REFERENCES [1] B.H.Calhoun, Y. Cao, X. Li, K.Mai, L.T.Pileggi, and R.A. Rutenbar, Digital circuit design challenges and opportunities in the era of Nano scale CMOs, Proc. IEEE,Vol96, no.2, pp , Feb [2]. Z. Xia, S. Ishihara, M.Hariyama, and M. Kameyama, Synchronizing logic gates for wave pipelining design, Electron. Lett, Vol.46, no.16, pp , Aug [3] T. E. Williams, Self-timed rings and their application to division, Ph.D. dissertation, Dept. Computer. Sci., Stanford Univ., Stanford, CA, USA, Jun [4].A. M. Lines, Pipelined asynchronous circuits, Dept. Comput. Sci., California Inst. Technol., Pasadena, CA, USA, Tech. Rep., [5] M. Singh and S. M. Nowick, The design of high performance dynamic asynchronous pipelines: Look ahead style, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.15, no. 11, pp , Nov

6 H. NASEEMA BEGUM [6].M. Singh, J. A. Tierno, A. Rylyakov, S. Rylov, and S. M.Nowick, An adaptively pipelined mixed synchronous asynchronous digital FIR filter chip operating at 1.3 gigahertz, IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 18, no. 7, pp , Jul [7] Zheng fan Xia, Masanori Hariyama, and Michitaka Kameyama Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path IEEE Transactions on very Large Scale Integration (VLSI) Systems 2014, pp [8] J. Sparsø and S. Furber, Principles of Asynchronous Circuit Design: A Systems Perspective. Boston, MA, USA: Kluwer, [9] D. Harris, introduction to CMOS VLSI design Lecture 9: Circuit Families (Lecture Notes on the subject). Claremont, CA, USA: Harvey Mudd College, [10] Z. Xia, S.Ishihara, M.Hariyama, and M. Kameyama, Dual-rail/single-rail hybrid logic design for highperformance asynchronous circuit, in Proc. IEEE ISCAS, May 2012, pp [11] Z. Xia, S. Ishihara, M. Hariyama, and M.Kameyama, Design of High-PerformanceAsynchronous Pipeline using Synchronizing Logic Gates, IEICE Trans. Electron., vol. E95-C, no. 8, pp , Aug