Design of 8 bit Pipelined Adder using Xilinx ISE

Transcription

1 Design of 8 bit Pipelined Adder using Xilinx ISE 1 Jayesh Diwan, 2 Rutul Patel Assistant Professor EEE Department, Indus University, Ahmedabad, India Abstract An asynchronous circuit, or self-timed circuit, is a sequential digital logic circuit which is not having any global clock. The communication and data transfer between functional blocks is performed by indicating completion of operation and instruction, using handshaking protocol. While in synchronous design the complete working of different blocks are coordinated by clock signal. All blocks will respond only at the positive or negative edge of the clock. Most of the digital devices today are using synchronous logic design techniques. Because it is easy to design, availability of pool of tools for complete design flow, expertise in synchronous design techniques. But future Nano CMOS VLSI Technology will not be compatible with synchronous designs as physical parameters variation will be dominant. These increased timing variations will reduce robustness, reliability and performance. However asynchronous circuit designs have the potential to be faster, less power consumption, lowering electromagnetic interference, with modular designs in large systems (SoCs). Index Terms Asynchronous Design, GALS - Globally Asynchronous Locally Synchronous, Minimalist, pla2verilog, Handshake Protocol I. INTRODUCTION Today s digital design methodologies are dominated by the synchronous style, where execution of functions in a machine is kept in lock-step by a central timing generator. This has not always been the case. In the early days of digital design a variety of design styles flourished. One of the dominant research areas during this time was in a particular style called asynchronous design. Asynchronous circuits are sequential circuits that do not require any central timing to coordinate their internal operations. During the 1950's and 60's, many computers and systems were built using this type of circuit. However, during the 70's, the interest in asynchronous design started to decline and had all but disappeared in the early 80's [1]. The reason for this was the rapidly growing complexity of digital systems. Synchronous circuits offered simplicity in their discrete and deterministic behavior. Designers only had to make sure that the clock period was large enough for the system to reach a stable state before the next clock tick. Asynchronous circuits, on the other hand, required very detailed examination to ensure a proper behavior, a task that became too hard as system complexity increased. However, with the advance of modern technology [2], system complexity and the demand for higher performance has revealed several inherent problems with the synchronous design style. Some of the more notable problems are clock skew due to high frequency operation, power dissipation due to clock distribution and high speed interfacing with the environment[3]. Asynchronous circuits do not suffer from these problems and have therefore lately received renewed attention from researchers and designers. II. ASYNCHRONOUS ADDER DESIGN Figure 1. Design of pipelined Asynchronous adder As shown in the fig. 1 the design presented over here is free from clock. The adder will add two 8 bits inputs whenever request signal Rin will be high. Rin is the handshaking signal coming from previous block in a pipeline. Hence it indicates that data is IJSDR International Journal of Scientific Development and Research (IJSDR) 385

2 ready for processing. Same way whenever adder will complete its operation, Ain signal will be asserted which is an Acknowledgement signal indicates that Adder is ready to take new data in. same way for the next stage in a pipeline the data will be latched using Rl2 and Al2 as handshaking signals. Hence the complete communication between different blocks is performed with request and acknowledgement signals. The synchronization between blocks is controlled by Control unit. It asserts or deasserts the request signal depending on the acknowledgment received. x, y and z are level-sensitive latches which are transparent when R=1. + is a bundled-data adder with matched delay between Ra and Aa. Rin indicates the validity of inputs while after Ain+ the environment is allowed to change the inputs X and Y. III. IMPLEMENTATION OF DESIGN IN XILINX ISE The design is implemented and tested on Xilinx FPGA XC3S250E of SPARTAN 3E family. The different modules are written in VHDL language. While it is simulated in Isim simulator from Xilinx. Xilinx XST is used to synthesis the modular design to RTL level. Fig. 2 shows the RTL schematic of the design. The hardware requirement of the design is as follow: Design Statistics # IOs : 27 Cell Usage : # BELS : 21 # LUT2 : 2 # LUT3 : 18 # LUT4 : 1 # FlipFlops/Latches : 41 # LD : 41 # IO Buffers : 27 # IBUF : 17 # OBUF : 10 Figure 2. RTL Schematic of the design The combinational path delay is ns. Means the adder can perform the addition at the rate of MHz. Due to control unit, the design is having an area overhead compare to synchronous design. IV. DESIGN OF THE CONTROL UNIT The control unit is responsible for correct operation of the circuit as it controls the communication between blocks using handshaking signals. The control unit is designed using a tool Minimalist. Minimalist is a Linux based CAD tool developed by IJSDR International Journal of Scientific Development and Research (IJSDR) 386

3 Robert M. Fuhrer and Steven M. Nowick at the Columbia University. The Linux based binaries are open source for designing signal transition based asynchronous designs. It is available at The burst mode specifications are coded in terms of signal transitions as shown in fig. 3.The corresponding state diagram for the design is also shown in fig. 4. Figure 3. Signal Transition Graph of the Control Unit Figure 4. State Transition Graph of the Control Unit Depending on the optimization criteria the tool will generate the gate level design of the control unit. It is shown in fig. 4. Figure 5. Gate level design generated by the Minimalist tool Following is the Verilog file generated by the tool pla2verilog for the control unit. module CU2_L_cl (y0, Ain, Rl1, Ra, Rl2, Al2, Aa, Y0, Al1, Rin); output y0, Ain, Rl1, Ra, Rl2; IJSDR International Journal of Scientific Development and Research (IJSDR) 387

4 input Al2, Aa, Y0, Al1, Rin; wire Al2_n1, Y0_n1, Al1_n1, p1, p2, p3; wire p4, p5, p6, p7; nand (p1, Al2); nand (p2, Aa, Al2_n1, Y0_n1); not (Al2_n1, Al2); not (Y0_n1, Y0); nand (p3, Al1, Y0_n1); nand (p4, Aa); nand (p5, Rin, Y0_n1); nand (p6, Rin, Al1_n1, Y0); not (Al1_n1, Al1); nand (p7, Rin, Y0); nand (y0, p1, p7); nand (Ain, p6); nand (Rl1, p4, p5); nand (Ra, p1, p3); nand (Rl2, p2); endmodule module CU2_L (Ain, Rl1, Ra, Rl2, Al2, Aa, Al1, Rin); output Ain, Rl1, Ra, Rl2; input Al2, Aa, Al1, Rin; wire Y0, y0; CU2_L_cl c3 (y0, Ain, Rl1, Ra, Rl2, Al2, Aa, Y0, Al1, Rin); assign Y0 = y0; endmodule The output waveform of the design is shown in fig. 6. The design simulation is done with Isim simulator from Xilinx. Figure 6. Simulation results of the design V. CONCLUSION The asynchronous adder performs the addition much faster compare to synchronous design. Because it need not to wait for the clock. It will complete its operation whenever the data is ready with request signal[4]. As there is no global ckock, there will be no IJSDR International Journal of Scientific Development and Research (IJSDR) 388

5 unnecessary signal transitions. As well as clock buffers will not be needed. So the power consumption will be very less. It will be easy to route the signals due to absence of complex clock tree[5]. The design is also delay independent. So timing variation due to process will not affect the design output. REFERENCES [1] K. Y. Yun, P. A. Beerelt, and J. Arceo, High-Performance Asynchronous Pipeline Circuits, IEEE, pp , [2] P. A. Beerel, R. O. Ozdag, and M. Ferretti, A Designer s Guide to Asynchronous VLSI. Cambridge: CAMBRIDGE UNIVERSITY PRESS, [3] D. Jayanthi and M. Rajaram, The Design of High Performance Asynchronous Pipelines with Quasi Delay Insensitive, Int. J. Comput. Appl., vol. 52, no. 16, pp , [4] S. Hauck, Asynchronous design methodologies: An overview, Proc. IEEE, vol. 83, pp , [5] S. E. Schuster and P. W. Cook, Low-power synchronous-to-asynchronous-to-synchronous interlocked pipelined CMOS circuits operating at GHz, IEEE J. Solid-State Circuits, IJSDR International Journal of Scientific Development and Research (IJSDR) 389