CFP4 LR4 100GE Optical Transceiver for up to 10 km Reach, Single Protocol TRA5E20ENF-LF000

Transcription

1 CFP4 LR4 100GE Optical Transceiver for up to 10 km Reach, Single Protocol TRA5E20ENF-LF000 Data Sheet

2 Lumentum 100GE transceiver module TRA5E20ENF-LF000 enables a dense-port and highthroughput solution in favor of its compact size and low power consumption. The TRA5E20ENF- LF000 modules can be used in various network applications, such as dense wavelength division multiplexing (DWDM) systems, metropolitan area network (MAN) systems, Internet protocol (IP) switches and routers, and storage area network (SAN) applications. The maximum transmission length of TRA5E20ENF-LF000 is 10 km. The TRA5E20ENF-LF000 is a fully integrated 100 Gbps optical transceiver module with 25 Gbps electrical interface. Mechanical dimensions, connecters, and footprint of TRA5E20ENF-LF000 conform to CFP4 MSA. The module size is 22 mm x 92 mm x 9.5 mm and hot pluggable in Z-direction by 56-pin connector. The maximum power consumption is 6 W and power supply voltage is +3.3 V. Key Features 100 Gigabit Ethernet (100GE) 100GBASE-LR4 single protocol transceiver Gbps single rate capability Gbps x 4 channel electrical interface Transmission length up to 10 km Low power consumption: 6 W max Operating Case Temperature: 0 C to 70 C Compact size (22 x 92 x 9.5 mm) LC-Duplex Optical Receptacle Hot Z-Pluggable to 56-pin electrical connector Latching mechanism: lever latch MDIO management interface Compliance CFP4 MSA IEEE 802.3ba 100GBASE-LR4 CFP4 MSA Hardware Specification, Rev. 1.0 CFP MSA MDIO Specification, Version 2.4 r06b, June 8, 2015 This document may contain technologies regulated by law [ECCN: 5E001.c.1, 5E001.c.2.d, 5E991 as of April 2005]. In the case of the export of product(s) and/or technologies described in this document, please take the appropriate procedure in conforming to all regulations related to the export. 2

3 1 Functional Description 1.1 High Speed Data and Clock I/O (1) Transmitter Data Interface The Transmitter Data is defined in OIF CEI-28G-VSR. No. Symbol Function I/O Logic 1 TX [0:3]p/n Transmitter data input I CML (2) Receiver Data Interface The Receiver Data is defined in OIF CEI-28G-VSR. No. Symbol Function I/O Logic 1 RX [0:3]p/n Receiver data output O CML (3) Reference Clock Input No. Symbol Function I/O Logic 1 REFCLKp/n Reference clock input I CML Note: Reference clock is not required for this product but it is recommended host board is able to provide the reference clock to CFP4, because there is a possibility the reference clock is required for CFP4 in future. (4) Monitor Clock The CFP4 module supplies either a transmitter monitor clock or a receiver monitor clock. The transmitter monitor clock is intended to be used as a reference for measurements of the optical output. Those clocks shall operate at a rate relative to the optical lane rate of 1/8 or 1/32. The user can select the rate of the monitor clock using MDIO register bits in VR region. During the time Rx Reset is asserted, Tx monitor clock is disrupted. No. Symbol Function I/O Logic 1 MCLK_p/n Monitor clock output O CML 1.2 Hardware Control Pins Non-MDIO The Module supports alarm, control and monitor functions via hardware pins and via an MDIO bus. Upon module initialization, these functions are available. The CFP4 Module supports real-time control functions via hardware pins. There are three Hardware Control pins as listed in Table 1. Table 1 Control Pins Pin # Symbol Description I/O Logic H L Pull-up/down 11 TX_DIS (PRG_CNTL1) Transmitter disable (Optionally configurable as Programmable Control after Reset) I LVCMOS Up 14 MOD_LOPWR Module low power mode I Low power Enable Up 16 MOD_RSTn Module reset (invert) I Enable Reset Down Programmable Control (PRG_CNTL) These control pin allows for the system to program certain controls via a Hardware pin. TX Disable Pin (TX_DIS) is optionally configurable as Programmable Control 1 Pin after Reset. When Programmable Control 1 is configured, the default setting for Control 1 is control of the TX_DIS. (1) Programmable Control 1 Pin Programmable Control Pin 1 is an input pin from the Host, operating with programmable logic. It is pulled up in the CFP4 module. It can be re-programmed over MDIO registers to another MDIO control register while the module is in any steady stateexcept Reset. The CFP4 MSA specifies that the default function be TX Disable (TX_DIS) with active-high logic. If the other function besides TX_DIS is configured for this pin, there is no way to assert TX disable via a hardware pin. (2) Programmable Control 2 Pin and Programmable Control 3 Pin Not supported in CFP4 module. (3) Hardware Interlock Not supported in CFP4 module. 3

4 1.2.2 Other Controls (4) TX Disable Pin TX Disable Pin (TX_DIS) is an input pin from the Host, operating with active-high logic. This pin is pulled up in the CFP4. When TX_DIS is asserted, all of the optical outputs inside a CFP4 module shall be turned off. When this pin is de-asserted, transmitters in a CFP4 module shall be turned on according to a predefined TX turned-on process which is defined by the state diagram shown in the CFP MSA Management Interface Specification. A maximum time is defined for the transmitter turn-on process. This time is vendor and/or technology specific and the value is stored in a MDIO register. See the CFP MSA Management Interface Specification for more details. (5) Module Low Power Pin Module Low Power Pin (MOD_LOPWR) is an input pin from the host, operating with active-high logic. It is pulled up in the CFP4. When MOD_LOPWR is asserted the CFP4 module is in the Low Power State and will stay in the Low Power State as long as it is asserted. When de-asserted, the CFP4 initiates the Full-Power-up process. This pin on the CFP4 module is about 1 mm shorter than the Vcc power supply pins by design. This design helps to control the inrush and outrush current during module plug-in (insertion) and pull-out (extraction). In Low Power mode the module can communicate via the MDIO management interface. While the module is in low power mode it has a maximum power consumption of <1W. This protects hosts that are not capable of cooling higher power modules, should such modules be accidentally inserted. A maximum time is defined for the High-Power-up process, and a MDIO register is specified in the CFP MSA Management Interface Specification. (6) Module Reset Pin Module Reset Pin (MOD_RSTn) is an input pin from the Host, operating with active-low logic. This pin is pulled down in the CFP4 with a pull-down resistor value of 4.7 kohm to 10 kohm. When MOD_RSTn is asserted (driven low) the CFP4 module enters the Reset State. When de-asserted, the CFP4 module comes out of the Reset State and shall begin an initialization process as part of the overall module startup sequence. 1.3 Hardware Alarm Pins non-mdio The CFP4 Module supports alarm hardware pins, listed in Table 2: Hardware Alarm Pins. Table 2 Hardware Alarm Pins Pin # Symbol Description I/O Logic H L Pull-up/down 12 RX_LOS (PRG_ALRM1) Receiver Loss of Signal (Optionally configurable as Programmable Alarm after Reset) O LVCMOS 15 MOD_ABS Module absent O LVCMOS Note: 1 Pull-Down resistor (<100Ohm) is located within the CFP4 module. Pull-up should be located on the host. Loss of Signal OK Absent Present Pull-Down Programmable Alarm (PRG_ALRM) This alarm pin allows for the system to program module supported alarms to Hardware pins. The intention is to allow for maximum design and debug flexibility. (1) Programmable Alarm 1 Pin Programmable Alarm Pin 1 (PRG_ALRM1) is an output pin to the Host, operating with programmable logic. This pin can be reprogrammed over MDIO registers to another MDIO alarm register while the module is in any steady state except Reset. CFP-MSA specifies the default function to be Receiver Loss of Signal (RX_LOS) indicator with active-high logic. (2) Programmable Alarm 2 Pin and Programmable Alarm 3 Pin Not supported in CFP4 module. 4

5 1.3.2 Other Alarms (1) Module Absent Pin Module Absent Pin (MOD_ABS) is an output pin from CFP4 to Host. It is pulled up on the host board and is pulled down to ground in the CFP4 module. MOD_ABS asserts a Low condition when module is plugged in host slot. MOD_ABS is asserted High when the CFP4 module is physically absent from a host slot. (2) Receiver Loss of Signal Pin The Receiver Loss of Signal Pin (RX_LOS) is an output pin to the Host, operating with active-high logic. When asserted, it indicates received optical power in the CFP4 module is lower than the expected value. The RX_LOS is the logic OR of the LOS signals from all the receiving channels in a CFP4 module. This pin can be optionally configured as Programmable Alarm 1 Pin after Reset. 1.4 MDIO Interface Pins The CFP4 Module supports alarm, control and monitor functions via hardware pins and via an MDIO bus. Upon module initialization, these functions are available. CFP4 MDIO electrical interface consists of 6 pins including 2 pins of MDC and MDIO and 3 Physical Port Address pins and the Global Alarm pin. MDC is the MDIO Clock line driven by host and MDIO is the bidirectional data line driven by both host and module depending upon the data directions. The CFP4 MDIO pins are listed in Table 3. Table 3 MDIO Interface Pins Pin # Symbol Description I/O Logic H L Pull-up/down 13 GLB_ALRMn Global alarm O LVCMOS OK Alarm 17 MDC MDIO clock I 1.2V LVCMOS 18 MDIO Management data input output bi-directional data I/O 1.2V LVCMOS 19 PRTADR0 MDIO Physical Port address bit 0 I 1.2V LVCMOS per MDIO document 20 PRTADR1 MDIO Physical Port address bit 1 I 1.2V LVCMOS 21 PRTADR2 MDIO Physical Port address bit 2 I 1.2V LVCMOS (1) Global Alarm Pin Global Alarm Pin (GLB_ALRMn) is an output pin to the Host, operating with active-low logic. When GLB_ALRMn is asserted (driven low), it indicates that a Fault/Alarm/Warning/Status (FAWS) condition has occurred. It is driven by the logical OR of all fault/status/alarm/ warning conditions latched in the latched registers. Masking Registers are provided so that GLB_ALRMn may be programmed to assert only for specific fault/alarm/warning/status conditions. It is recommended that the Host board be designed to support a high priority event handling service to respond to the assertion of this pin. Upon the assertion (driven low) of this pin, the host event handler identifies the source of the fault by reading the latched registers over the MDIO interface. The reading action clears the latched registers which in turn cause the CFP4 to de-assert (driven high) the GLB_ALRMnpin. (2) MDC Pin Host specifies a maximum MDC rate of 4 MHz and CFP4 module hence support a maximum MDC rate up to 4 MHz. Other notable parameter is the minimal 10 ns setup and hold time that the CFP4 module support in its MDIO implementation. (3) MDIO Pin The MDIO specification is defined in clause 45 of the IEEE Standard. The CFP4 Module shall support 4.0 Mbit/s as maximum data rate. The CFP4 uses an MDIO with 1.2V LVCMOS logic levels. (4) MDIO Port Addresses These control pins are used for the system to address all of the CFP4 ports contained within a host system. PRTADR0 corresponds to the LSB in the physical port addressing scheme. The 3-wire Physical Port Address lines are driven by host to set the module Physical Port Address which should match the address specified in the MDIO Frame. It is recommended that the Physical Port Addresses not be changed while the CFP4 module is powered on. 5

6 PERFORMANCE SPECIFICATIONS 2 Operating Environment Electrical and optical characteristics below are defined under this operating environment, unless otherwise specified. Table 4 Operating Environment No. Parameter Symbol Minimum Typical Maximum Unit Remarks 1 Supply voltage V CC V 2 Power supply noise Vrip Case temperature TC C % % DC 1 MHz 1 10 MHz 3 Optical Characteristics Table 5 Optical Characteristics for 100GBASE-LR4 1 No. Parameter Symbol Minimum Maximum Unit Remarks 1 Channel data rate fdc Gbps IEEE 802.3ba 2 Aggregate data rate fd Gbps 3 Signal speed variation from nominal ΔfD ppm 4 Transmitter center wavelength Lane 0 λ CT nm Lane 1 λ CT Lane 2 λ CT Lane 3 λ CT Optical output power in OMA OMA dbm Note2 6 Average optical output power of off transmitter P off -30 dbm 7 Optical waveform IEEE 802.3ba 8 Extinction ratio ER 4 db 9 Receiver sensitivity in OMA P minoma dbm 10 Stressed receiver sensitivity in OMA P minsoma -6.8 dbm Note 3 11 Receive power, each lane in OMA +4.5 dbm Note: 1. Data Rate; NRZ, Mark Ratio 50%, PRBS=2 31-1, 1x10-12 BER unless otherwise specified. 2. OMA=10log 10 [2P{(A-1)/(A+1)}], A = 10 (ER/10), P = 10 (Pf/10) 3. Stressed Receiver Sensitivity measurement method is under study. 4 Electrical Characteristics Table 6 Power supply Characteristics No. Parameter Symbol Minimum Typical Maximum Unit Remarks 1 Supply current ICC 1.9 A Note 1 2 Supply power mode ICCL 0.3 A 3 Power consumption Pw 6 W 4 Power power mode Plow 1 W Note: 1. Maximum module current ramp rate is 100 ma /μs. 6

7 Table 7 LVCMOS level No. Parameter Symbol Minimum Typical Maximum Unit Remarks 1 Input high voltage VIH 2 VCC V 2 Input low voltage VIL V 3 Input leakage current IIN μa 4 Output high voltage VOH VCC 0.2 V I OH =-100 μa 5 Output low voltage VOL 0.2 V I OL =100 μa 6 Minimum pulse width of control pin signal t_cntl 100 μs Table 8 1.2VLVCMOS level No. Parameter Symbol Minimum Typical Maximum Unit Remarks 1 Input high voltage VIH V 2 Input low voltage VIL V 3 Input leakage current IIN μa 4 Output high voltage VOH V 5 Output low voltage VOL V 6 Output high current IOH -4 ma 7 Output low current IOL +4 ma 8 Input capacitance Ci 10 pf Note: The above drawings, with maximum host load capacitance of 200pF, also define the measurement set-up for module MDC timing verification. The capacitor in the drawing indicates the stray capacitance on the line. Don t put any physical capacitor on the line. Table 9 High Speed Electrical Input Characteristics No. Parameter Symbol Minimum Maximum Unit Conditions 1 Differential voltage overload pk-pk Module input 900 mv Calibrated at TP1a 2 Differential termination mismatch Module input 10 % at 1 MHz 3 Differential return loss Module input Note 1 db 4 Common mode to differential conversion loss Host output Note 2 db Note: 1. SDD11, SDD22 < -11dB for f<fb/7, SDD11, SDD22 < *log(2f/fb) db for fb/7<f<fb (fb=25.78 GHz) 2. SDC11 < *(f/fb) db for f<fb/2, SDC11 < -15 db for fb/2<f<fb (fb=25.78 GHz) Table 10 High Speed Electrical Output Characteristics No. Parameter Direction Minimum Maxical Units Conditions 1 Differential voltage, pk-pk Module output 900 mv 2 Common mode noise, rms Module output 17.5 mv 3 Differential termination mismatch Module output 10 % at 1 MHz 4 Differential return loss Module output Note 1 db 5 Transition time: 20/80% Module output 9.5 ps 6 Vertical eye closure (VEC) 6.5 db 7 Eye width at probability (EW15) Module output 0.57 UI 8 Eye height at probability (EH15) Module output 240 mv Note: 1. SDD11, SDD22 < -11dB for f<fb/7, SDD11, SDD22 < *log(2f/fb) db for fb/7<f<fb (fb=25.78 GHz) Table 11 Transmitter and receiver monitor clock characteristics No. Parameter Symbol Minimum Typical Maximum Unit Remarks 1 Clock differential input impedance Zd ohm 2 Differential output clock amplitude V DIFF mvpp AC coupled CML 3 Reference clock duty cycle % 7

8 TX3n TX3p TX2n TX2p TX1n TX1p TX0n TX0p (REFCLKn) (REFCLKp) RX3n RX3p RX2n RX2p RX1n RX1p RX0n RX0p Bottom (Nx25G) Top (4x25G) (TX_MCLKn) (TX_MCLKp) VND_IO_A VND_IO_B PRG_CNTL1 PRG_CNTL2 PRG_CNTL3 PRG_ALRM1 PRG_ALRM2 PRG_ALRM3 TX_DIS RX_LOS MOD_LOPWR MOD_ABS MOD_RSTn GLB_ALRMn MDC MDIO PRTADR0 PRTADR1 PRTADR2 VND_IO_C VND_IO_D VND_IO_E (RX_MCLKn) (RX_MCLKp) Figure 1 Pin configurations

9 A A C NOTE 1 MEASUREMENT AIRFLOW DIRECTION DETAIL B A15 A01 A07 -A- A16 A17 A A A03 A08 2-A06 A18 A11 A19 A12 2-A20 NOTE 5 r B NOTE 4 PIN 29 PIN 56 A10 A13 D C D 4-A09 MATING PLANE A54 -D- -B- -C- PIN 28 A M A C A23 PIN 1 4-A21 SEC: A-A 0.2 M A C DETAIL C (CUTOUT FOR DATUM -D- INSPECTION) NOTE 3 A55 A26 EMI-GASKET PROTECT (NOTE 10) DETAIL F (EMI-GASKET PROTECT) 2-A53 A25 A51 A50 A24 A30 A29 A28 A33 A57 A58 A34 A32 F MATING PLANE -B- A27 NOTES ARE SHOWN ON PAGE 2 EMI-GASKET PROTECT BOTTOM VIEW OF MODULE A43 A39 A42 A35 A M A B A52 (LABLE RECESS) A M A B A37 SEC. D-D (UNLOCKED POSITION) MODULE OUTSIDE WALL POINT A (NOTE 8) 2-A45 -B- -D- A36 A41 MATING PLANE A 44 DETAIL E (CUTOUT FOR DATUM -D- INSPECTION) LOCK WALL PLANE SEC. D-D (LOCKED POSITION) MODULE OUTSIDE WALL 2-A47 LOCK WALL PLANE 2-A46 A 44 2-A47 2-A48 2-A49 NOTE: 1. 7 C MAXIMUM TEMPERATURE DELTA WITH NO HEATSINK AND 200LFM SIDEWAYS AIR FLOW. (DELTA TEMPERATURE SPECIFICATION TO BE VERIFIED WITH FIRST ARTICLES 2. DRAFT ANGLE TO BE IN THE DECREASING MASS DIRECTION. 3. MODULE LATCH POSITION MUST INTEROPERATE WITH CFP4 CAGE SPECIFICATIONS. 4. SURFACE FLATNESS: F IS SPECIFIED IN CFP4 HARDWARE SPECIFICATION. 5. SURFACE ROUGHNESS: R IS SPECIFIED IN CFP4 HARDWARE SPECIFICATION. 6. DIMENSION APPLIES TO LATCH MECHANISM. 7. MAXIMUM OUTSIDE ENVELOP BETWEEN TWO OPPOSITE LATCHES. 8. POINT A IS AT THE VIRTUAL INTERSECTION OF LOCK WALL PLANE AND OUTER SURFACE OF LATCH. 9. POINT B IS AT THE VIRTUAL INTERSECTION OF LOCK WALL PLANE AND OUTER SURFACE OF LATCH. 10. GASKET TO MEET MINIMUM PEELS STRENGTH: 30 OZ/IN OR 335 GF/CM PER ASTM D3330 TEST METHOD. POINT B (NOTE 9) Figure 2 Mechanical dimensions (all units in mm) 9

10 Key Value Tolerance Description A Max. Width of Module faceplate, overall A Max. Optical connector receptacle, overall A Max. Optical connector receptacle from module faceplate top front surface A04 Not used A05 Not used A06 R2.00 ±0.10 Top module lead-in radius A ±0.10 Width, module body, overall A ±0.20 Length of module, overall A ±0.10 Latch position from datum -B- A ±0.20 Height, module body, overall A Min. Height, module to optical connector A Max. Height of optical connector, top side A Max. Height of optical connector, bottom side A14 Not used A15 R1.00 ±0.20 Top module lead-in radius A16 R0.20 ±0.10 Top of module corner A ±0.10 Start of side wall A18 C2.50 ±0.20 Side wall chamfer A19 R0.20 ±0.10 Side wall lead-in radius A20 C0.30/R0.30 ±0.10 Module outside chamfer or radius A21 C0.20/R0.20 ±0.10 Module outside chamfer or radius A ±0.04 Width, connector, overall A Min. Width, module sidewall, overall A ±0.20 Distance from datum -C- to bottom surface of module tail A ±0.15 Datum -C- to center line of connector A ±0.20 Distance from datum -B- to module end A REF. Length of connector end from datum -B- A ±0.10 EMI-GASKET project A ±0.10 EMI-GASKET project A Min. Width of latch A31 Not used A ±0.15/-0.3 Module outside wall slope A REF. Width of cutout A34 20deg ±10deg. Module outside wall slope A ±0.20 Length of connector signal pin from datum -D- A Max. Label recess from datum -B- A ±5.00 Label recess from datum -B- A Max. Label recess width A Max. Latch surface A40 Not used A REF. Latch position from datum -B- A ±0.2 Length of connector pin from datum -D- A ±0.15 Length of connector from datum -D- A Max. Latch surface A Max. Module outside wall to point A A ±0.20 Module outside wall to point B A47 R0.10 ±0.05/-0.10 Lock wall radius A48 R0.20 ±0.10 Cutout of inspection wall radius A REF. Minimum cutout for datum -D- inspection A Min. End of lock wall position, top A Max. End of lock wall position, bottom A ±0.15 Label recess depth (the label should not protrude from datum -C-) A ±0.30 Latch center line from datum -C- A ±0.10 Position of the wall of side from the module bottom A ±0.40 Thickness of the EMI-GASKET A Max. Width of the protected of EMI-GASKET A Min. Lock wall, bottom A Max. Lock wall, top 10

11 5 Optical Interface No. Parameter Specifications Remarks 1 Connector LC-Duplex optical receptacle 10. Electrical Connector for the Customer Board No. Parameter Specifications Remarks 1 Yamaichi electronics Host connector Or equivalent 11. Mechanical Parts for the Customer Board No. Parameter Specifications Remarks 1 Yamaichi electronics CFP4 cage Or equivalent 2 Yamaichi electronics Host connector cover Or equivalent 8 Laser Safety This product is complied with IEC as Class 1 and with FDA 21 CFR as Class I laser product. Ordering Information For more information on this or other products and their availability, please contact your local Lumentum account manager or Lumentum directly at customer.service@lumentum.com. Description CFP4 optical transceiver, single rate 100GBASE-LR4, 10 km reach, LR4, 1310 nm transceiver, commercial temperature range, four optical lanes, LC connector Part number TRA5E20ENF-LF000 USER INFORMATION 6 Handling Precautions CAUTION: Take proper electrostatic-discharge (ESD) precautions while handling these devices. These devices are sensitive to ESD. 7 EMI Compliance This product meets Electromagnetic Interference (EMI) specifications of following standards No. Standards Criteria Remarks 1 FCC Class B Target 2 EN55002 Class B Target North America Toll Free: LITE (5483) Outside North America Toll Free: LITE (5483) China Toll Free: LITE (5483) Lumentum Operations LLC 400 North McCarthy Boulevard Milpitas, CA USA Lumentum Operations LLC Product specifications and descriptions in this document are subject to change without notice. cfp4-lr4-100gsp-ds-oc-ae