128Mbit, 4MX32 5V Flash Memory Module

Transcription

1 128Mbit, 4MX32 5V Flash Memory Module Features 5V Programming, 5V±10% Supply Access Times: 90, 120 and 150ns Package Options: 66-Pin Ceramic PGA 1.173" SQ 66-Pin Ceramic PGA 1.385" SQ Individual Byte Selection x32 down to x8 Embedded Program Algorithms TTL Compatible Inputs and CMOS Outputs Low Power Consumption Industrial and Military Screening 1,000,000 Erase/Program Cycles Product Description The MEF4M32 is a 5V-flash EEprom MCM, organized as 4 MEG by 32 bits. The package is a High-Temp multilayer cofired ceramic package, and based on "29F032". Byte write and automated block erase flowcharts are identical to "29F032" Data Sheet and should be used as a reference. Block Diagram December, 2003 Rev. A 1 OF 35

2 Pin Names A0 A21 DQ0 DQ31 CE1# CE4# WE# OE# GND VCC NC RY/BY1# RESET# Pin Name MEF4M32XXXXXX5 Address Inputs Data Inputs/Outputs Chip Enables Master Write Enable Pin Function Master Output Enable Ground P. Supply No Connection Ready/Busy Output signal from first chip Module Master RESET Note: # Symbol means "Active Low" Signal Pin Configuration for 66-Pin PGA (Top View) A B C F G H 1 DQ8 RESET# DQ15 DQ24 VCC DQ31 2 DQ9 CE2# DQ14 DQ25 CE4# DQ30 3 DQ10 GND DQ13 DQ26 RY/BY1# DQ29 4 A14 DQ11 DQ12 A7 DQ27 DQ28 5 A16 A10 OE# A12 A4 A1 6 A11 A9 A17 A21 A5 A2 7 A0 A15 WE# A13 A6 A3 8 A18 VCC DQ7 A8 A20 DQ23 9 DQ0 CE1# DQ6 DQ16 CE3# DQ22 10 DQ1 A19 DQ5 DQ17 GND DQ21 11 DQ2 DQ3 DQ4 DQ18 DQ19 DQ20 December, 2003 Rev. A 2 OF 35

3 Absolute Maximum Ratings MEF4M32XXXXXX5 Item Supply Voltage Relative to GND (1) Voltage On Any Pin Except A9 (2) A9 (2) Storage Temperature Output Short Circuit Current (3) Rating -2 to +7.0V -2 to +7.0V -2 to +14.0V -65 C to +150 C 200mA Notes: (1) Minimum D.C Voltage on any input is -0.5V, may undershoot to GND-2.0V for periods <20ns Maximum D.C Voltage on any output is Vcc +0.5V, may overshoot to Vcc +2.0V for periods < 20ns (2) Minimum D.C Voltage on A9 is -0.5V, may undershoot to -2.0V for periods < 20ns Maximum D.C Voltage on A9 is +13.5V, may overshoot to +14.0V for periods < 20ns (3) No more than one output shorted at a time for periods < 1second Recommended Operating Conditions Parameter Symbol Min Max Unit Supply Voltage VCC V Input High Voltage VIH 2.2 VCC +0.5 V Input Low Voltage VIL V Operating (Military) TA C Temperature (Industrial) C December, 2003 Rev. A 3 OF 35

4 Erase and Programming Performance (8 bit Operation Mode) Parameter Min Typ Max Unit Comments Sector Erase Time 1.0 (1) 8 Sec Chip Erase Time 64 (1) Sec Byte Programming Time (2) µs Chip Programming Time 28.8 (1) 86.4 Sec Notes: (1) 25 C, 5V VCC, 1,000,000 cycles Excludes 00H Programming prior to Erasure Excludes 00H Programming prior to Erasure Excludes System-level Overhead Excludes System-level Overhead (2) When programming a "1" over a "0", the Embedded Algorithms allow for 48 ms byte Program time Capacitance (TA = +25 C, VIN = 0, f = 1.0 MHz) Description Symbol Limits Unit Output Enable Capacitance OE# COE 50 pf Write Enable Capacitance WE# CWE 20 pf Chip Enable Capacitance CE1# to CE4# CCE 20 pf DQ0 to DQ31 Capacitance CI/O 20 pf A0 to A21 Capacitance CAD 50 pf Note: These parameters are guaranteed by design but not tested. December, 2003 Rev. A 4 OF 35

5 DC Characteristics (TTL Compatible, 8 bit Operation Mode) Parameter Symbol Min Max Unit Test Condition Input Load Current ILI ±1.0 µa Vcc = Max, GND=Vss to Vcc A9 Input Load Current ILIT 50 µa Vcc = Max, A9 = 12.5V Output Leakage Current ILO ±1.0 µa Vcc = Max, VOUT=GND to Vcc Vcc Active Current (1) ICC ma CE# = VIL, OE#=VIH Vcc Active Current (2)(3) ICC ma CE# = VIL, OE#=VIH Vcc Stand by Current ICC ma Vcc = Max, CE# =OE# =VIH Input Low Level VIL V Input High Level VIH 2.0 Vcc +0.5 V Voltage for Autoselect and Sector Protect VID V Vcc = 5.0V Output Low Voltage VOL 0.45 V IOL = 12mA, Vcc = Min Output High Voltage VOH 2.4 V IOH = -2.5mA, Vcc = Min Low Vcc Lock-Out Voltage VLKO V Notes: (1) The Icc current listed includes both the DC operating current and the frequency Dependent component (at 6 MHz) The frequency component typically is less than 1mA/MHz, with OE# at VIH (2) Icc active while Embedded Algorithm (program or erase) is in progress (3) Not 100% tested December, 2003 Rev. A 5 OF 35

6 Bus Operation Table Legend: L =Logic Low =V IL,H =Logic High =V IH,V ID =12.0 ± 0.5 V,X =Don t Care, D IN =Data In, D OUT =Data Out, A IN =Address In Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information. Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register it-self does not occupy any addressable memory location. The register is composed of latches that store the Commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus Operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. December, 2003 Rev. A 6 OF 35

7 Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to V IL.CE# is the power control and s elects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures t hat no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled f or read access until the command register contents are altered. See Reading Array Data for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A sector address Consists of the address bits required to uniquely select a sector. See the Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters The Autoselect Mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7 DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timings specification tables and timing diagrams for write operations. December, 2003 Rev. A 7 OF 35

8 Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7 DQ0. Standard read cycle timings and ICC read specifications apply. Refer to The Erase Resume command is valid only during the Erase Suspend mode. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when CE# and RESET# pins are both held at VCC ±0.5 V.(Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at V IH. The device requires standard access time (tce ) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin. If the device is deselected during erasure or programming, the device draws active current until The operation is completed. In the DC Characteristics tables, ICC3 represents the standby current specification. RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. December, 2003 Rev. A 8 OF 35

9 RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write Attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V IL, the device enters the TTL standby mode; if RESET# is held at VSS ± 0.5 V, the device enters the CMOS standby mode. The RESET# pin may be tied t o the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is 1 ), the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data t RH after the RESET# pin returns to V IH. Output Disable Mode When the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. December, 2003 Rev. A 9 OF 35

10 Command Definitions Command Sequence Read/Reset Bus Write Cycles Req`d First Bus Write Cycle Read/Reset 1 XXXH FOH Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read/Reset H AAH 2AAAH 55H 5555H FOH RA RD Autoselect H AAH 2AAAH 55H 5555H 90H Byte Program H AAH 2AAAH 55H 5555H AOH PA Data Chip Erase H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector Erase H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H Sector Erase Suspend Sector Erase Resume Erase can be suspended during sector erase with Addr (don't care), Data (BOH) Erase can be resumed after suspend with Addr (don`t care), Data (30H) Legend: X = don t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD =Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA =Address of the sector to be verified (in autoselect mode) or erased. Address bits A21 A16 select a unique sector. SGA =Address of the sector group to be verified. Address bits A21 A18 select a unique sector group. December, 2003 Rev. A 10 OF 35

11 Notes: 1. See Table for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Address bits A21 A11 are don t cares for unlock and command cycles, unless SA or PA required. 5. No unlock or command cycles required when reading array data. 6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. The data is 00h for an unprotected sector group and 01h for a protected sector group. See Autoselect Command Sequence for more information. 9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 10. The Erase Resume command is valid only during the Erase Suspend mode. December, 2003 Rev. A 11 OF 35

12 Sector Address Table MEF4M32XXXXXX5 December, 2003 Rev. A 12 OF 35

13 Sector Address Table (Continued) MEF4M32XXXXXX5 Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on DQ7 DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed insystem through the command register. When using programming equipment, the autoselect mode requires V ID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table. In addition, when verifying sector group protection, the sector group address must appear on the appropriate highest order address bits. Table also shows the remaining address bits that are don t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table.This method does not require V ID on an address line. Refer to the Autoselect Command Sequence section for more information. December, 2003 Rev. A 13 OF 35

14 Autoselect Codes Table MEF4M32XXXXXX5 Note: Identifier codes for manufacturer and device IDs exhibit odd parity with DQ7 defined as the parity bit. Sector Group Protection/Unprotection The hardware sector group protection feature disables both program and erase operations in any sector group. Each sector group consists of four adjacent sectors. Table shows how the sectors are grouped, and the address range that each sector group contains. The hardware sector group unprotection feature re-enables both program and erase operations in previously Protected sector groups. Sector group protection/unprotection must be implemented using Programming equipment. The procedure requires a high voltage (V ID ) on address pin A9 And the control pins. December, 2003 Rev. A 14 OF 35

15 Sector Group Addresses Table MEF4M32XXXXXX5 December, 2003 Rev. A 15 OF 35

16 Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper Sequence resets the de vice to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data.the de vice is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data wit h the same exception. See Erase Suspend/Erase Resume Commands for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the Reset Command section, next. December, 2003 Rev. A 16 OF 35

17 Reset Command Writing the reset command to the device resets the device to reading array data. Addresses bits are don t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (Also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to re turn to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Byte Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. December, 2003 Rev. A 17 OF 35

18 Chip Erase Command Sequence Chip erase is a six-bus-cycle operation. The chips erase command sequence is initiated by writing two unlock cycles, followed by a setup command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase Algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has Returned to reading array data, to ensure data integrity. Erase Operation December, 2003 Rev. A 18 OF 35

19 Data Polling Algorithm MEF4M32XXXXXX5 Notes: 1. VA =Valid address for programming. During a sector erase operation; a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any nonprotected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5. December, 2003 Rev. A 19 OF 35

20 Toggle Bit Algorithm Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text. December, 2003 Rev. A 20 OF 35

21 Write Operation Status MEF4M32XXXXXX5 Notes: 1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has Exceeded the maximum timing limits. December, 2003 Rev. A 21 OF 35

22 AC Characteristics Read Only Operations Parameter Symbol 90ns 120ns 150ns Limits Unit (1) (1) (1) Read Cycle Time (3) TRC Min ns Address to Output Delay (4) TACC Max ns Chip Enable to Output Delay (5) TCE Max ns Output Enable to Output Delay TOE Max ns Chip Enable to Output High Z (2)(3) TDF Max ns Output Enable to Output High Z (2)(3) TDF Max ns Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First TOH Min ns Notes: (1) Test Conditions: Output Load TTL gate and 100 pf Input rise and fall times ns Input pulse levels V to 2.4V Timing measurement reference level: Input and 2.0V Output and 2.0V (2) Output driver disable time (3) Not 100% tested (4) Test Setup: CE# = OE#=VIL (5) Test Setup: OE#=VIL December, 2003 Rev. A 22 OF 35

23 AC Characteristics (Con`t) Write/Erase/Program Operations MEF4M32XXXXXX5 Parameter Symbol 90ns 120ns 150ns Limits Unit Write Cycle Time TWC Min ns Address Setup Time TAS Min ns Address Hold Time TAH Min ns Data Setup Time TDS Min ns Data Hold Time TDH Min ns Output Enable Setup Time TOES Min ns Output Enable Read TOEH Min ns Hold Time Toggle and Data Polling Min ns Read Recover Time Before Write TGHWL Min ns CE# Setup Time TCS Min ns CE# Hold Time TCH Min ns Write Pulse Width TWP Min ns Write Pulse Width TWPH Min ns Byte Programming Operation TWHWH Min µs Erase Operation TWHWH Min Max VCC Set Up Time TVCS Min µs Voltage Transition Time* TVLHT Max µs Write Pulse Width* TWPP Min µs OE# Setup Time to WE# Active* TOESP Min µs CE# Setup Time to WE# Active* TCSP Min µs (*) - See protect/unprotected waveforms sec sec December, 2003 Rev. A 23 OF 35

24 AC Characteristics MEF4M32XXXXXX5 Write/Erase/Program Operations (Alternate CE# Controlled Writes) Parameter Symbol 90ns 120ns 150ns Limits Unit Write Cycle Time TWC Min ns Address Setup Time TAS Min ns Address Hold Time TAH Min ns Data Setup Time TDS Min ns Data Hold Time TDH Min ns Output Enable Setup Time TOES Min ns Output Enable Read TOEH Min ns Hold Time Toggle and Data Polling Min ns Read Recover Time Before Write TGHEL Min ns WE# Setup Time TWS Min ns WE# Hold Time TWH Min ns CE# Pulse Width TCP Min ns CE# Pulse Width High TCPH Min ns Byte Programming Operation TWHWH Min µs Erase Operation TWHWH Min Max Vcc Setup Time TVCS Min µs sec sec December, 2003 Rev. A 24 OF 35

25 Test Specifications KEY TO SWITCHING WAVEFORMS December, 2003 Rev. A 25 OF 35

26 Timing Waveforms General Definitions and Notes 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the data written to the device. 4. Dout is the output of the data written to the device. 5. Timing indicates last two bus cycles of four-bus cycle sequence. Timing Waveforms for Read Operation December, 2003 Rev. A 26 OF 35

27 Timing Waveforms for Program Operation Timing Waveforms for Chip/Sector Erase Operations December, 2003 Rev. A 27 OF 35

28 Timing Waveforms for Data Polling during Embedded Algorithm Operations Timing Waveforms for Toggle Bit During Embedded Algorithm Operations December, 2003 Rev. A 28 OF 35

29 Timing Waveforms for Program Operation (Alternate CE# Controlled) Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the data written to the device. 4. Dout is the output of the data written to the device. 5. Timing indicates last two bus cycles of four bus cycle sequence. December, 2003 Rev. A 29 OF 35

30 RESET# Timings December, 2003 Rev. A 30 OF 35

31 Temporary Sector Group Unprotect Timings December, 2003 Rev. A 31 OF 35

32 Alternate CE# Controlled Write Operation Timings Notes: 1. PA =Program Address, PD =Program Data, SA =Sector Address, DQ7#=Complement of Data Input, D OUT =Array Data. 2. Figure indicates the last two bus cycles of the command sequence. December, 2003 Rev. A 32 OF 35

33 Outline Drawing for 66-Pin Ceramic PGA (G3) December, 2003 Rev. A 33 OF 35

34 Outline Drawing for 66-Pin Ceramic PGA (G2) December, 2003 Rev. A 34 OF 35

35 Ordering Information (Standard Military Screened Products*) Model Number Speed Package MEF4M32G3090M5 90ns CPGA MEF4M32G3120M5 120ns CPGA MEF4M32G3150M5 150ns CPGA MEF4M32G2090M5 90ns Thin CPGA MEF4M32G2120M5 120ns Thin CPGA MEF4M32G2150M5 150ns Thin CPGA (*) - Contact Elisra for additional designs Part Number Breakdown December, 2003 Rev. A 35 OF 35