THIS SPEC IS OBSOLETE

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1 THIS SPEC IS OBSOETE Spec No: Spec Title: S29A8D, 8-MBIT (M 8-BIT/52K 6- BIT), 3 V BOOT SECTOR FASH Replaced by: NONE

2 S29A8D 8-Mbit (M x 8-Bit/52K x 6-Bit), 3 V Boot Sector Flash This product has been retired and is not recommended for designs. For new and current designs, S29A8J supercedes S29A8D. This is the factory-recommended migration path. Please refer to the S29A8J data sheet for specifications and ordering information. Distinctive Characteristics Architectural Advantage Performance Characteristics Single Power Supply Operation 2.7 to 3.6 volt read and write operations for battery-powered applications High Performance Access times as fast as ns Extended temperature range (-4 C to +25 C) Manufactured on 2 nm Process Technology Compatible with.32 µm and 23 nm Am29V8 devices Ultra-low Power Consumption (typical values at 5 MHz) 2 na Automatic Sleep mode current 2 na standby mode current 7 ma read current 5 ma program/erase current Flexible Sector Architecture One 6-Kbyte, two 8-Kbyte, one 32-Kbyte, and fifteen 64-Kbyte sectors (byte mode) One 8 Kword, two 4 Kword, one 6-Kword, and fifteen 32-Kword sectors (word mode) Supports full chip erase Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors Unlock Bypass Program Command Reduces overall programming time when issuing multiple program command sequences Top or Bottom Boot Block Configurations Available Embedded Algorithms Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors Embedded Program algorithm automatically writes and verifies data at specified addresses Compatibility with JEDEC Standards Pinout and software compatible with single-power supply Flash Superior inadvertent write protection Cycling Endurance:,, cycles per sector typical Data Retention: 2 years typical Reliable operation for the life of the system Package Option 48-ball FBGA 48-pin TSOP 44-pin SO Software Features Data# Polling and Toggle Bits Provides a software method of detecting program or erase operation completion Erase Suspend/Erase Resume Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Hardware Features Ready/Busy# Pin (RY/BY#) Provides a hardware method of detecting program or erase cycle completion Hardware Reset Pin (RESET#) Hardware method to reset the device to reading array data Cypress Semiconductor Corporation Document Number: Rev. *B 98 Champion Court San Jose, CA Revised January 24, 27

3 S29A8D General Description The S29A8D is an 8 Mbit, 3. volt-only Flash memory organized as,48,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more information, refer to publication number The word-wide data (x6) appears on DQ5 DQ; the byte-wide (x8) data appears on DQ7 DQ. This device requires only a single, 3. volt VCC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device. This device is manufactured using Spansion s 2 nm process technology, and offers all the features and benefits of the Am29V8B, which was manufactured using.32 µm process technology. The standard device offers access times of, 6, 7, and 9 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device contains separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3. volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle is completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Spansion s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Document Number: Rev. *B Page 2 of 49

4 S29A8D Contents. Product Selector Guide Block Diagram Connection Diagrams... 5 Special Handling Instructions for FBGA Package Pin Configuration ogic Symbol Ordering Information... 7 Standard Products Device Bus Operations... 8 Word/Byte Configuration... 9 Requirements for Reading Array Data... 9 Writing Commands/Command Sequences... 9 Program and Erase Operation Status... 9 Standby Mode... 9 Automatic Sleep Mode... RESET#: Hardware Reset Pin... Output Disable Mode... Autoselect Mode... 2 Sector Protection/Unprotection... 2 Temporary Sector Unprotect... 3 Hardware Data Protection Command Definitions... Reading Array Data... Reset Command... Autoselect Command Sequence... Word/Byte Program Command Sequence... Unlock Bypass Command Sequence... Chip Erase Command Sequence... Sector Erase Command Sequence... Erase Suspend/Erase Resume Commands Write Operation Status... DQ7: Data# Polling... RY/BY#: Ready/Busy#... DQ6: Toggle Bit I... DQ2: Toggle Bit II... Reading Toggle Bits DQ6/DQ2... DQ5: Exceeded Timing imits... DQ3: Sector Erase Timer Absolute Maximum Ratings Operating Ranges TS Pin Standard TSOP VBK Ball Fine-Pitch Ball Grid Array (FBGA) 8.5 x 6.5 mm SO Pin Small Outline Package Revision History Revision A (September 8, 24) Revision A (February 8, 25) Revision A2 (June, 25) Revision A3 (June 6, 25) Revision A4 (February 6, 26) Revision A5 (May 22, 26) Revision A6 (September 6, 26) Revision A7 (October 3, 26) Revision A8 (August 29, 27) Revision A9 (September 9, 27) Revision A (November 27, 27) Revision A (February 27, 29) DC Characteristics Zero Power Flash Test Conditions Key to Switching Waveforms AC Characteristics Erase/Program Operations Erase and Programming Performance Physical Dimensions... 4 Document Number: Rev. *B Page 3 of 49

5 S29A8D. Product Selector Guide Family Part Number Speed Options S29A8D Full Voltage Range: VCC = V Regulated Voltage Range: VCC = V Max access time, ns (tacc) Max CE# access time, ns (tce) Max OE# access time, ns (toe) Note See AC Characteristics on page 3 for full specifications. 2. Block Diagram DQ DQ5 (A-) RY/BY# VCC Sector Switches VSS Erase Voltage Generator RESET# WE# BYTE# Input/Output Buffers State Control Command Register PGM Voltage Generator Chip Enable Output Enable ogic CE# OE# Address atch Timer Data atch Y-Decoder Y-Gating -Decoder Cell Matrix STB VCC Detector STB A A8 Document Number: Rev. *B Page 4 of 49

6 S29A8D 3. Connection Diagrams Figure 3. Standard TSOP A5 A4 A3 A2 A A A9 A8 NC NC WE# RESET# NC NC RY/BY# A8 A7 A7 A6 A5 A4 A3 A2 A A6 BYTE# VSS DQ5/A- DQ7 DQ4 DQ6 DQ3 DQ5 DQ2 DQ4 VCC DQ DQ3 DQ DQ2 DQ9 DQ DQ8 DQ OE# VSS CE# A Figure 3.2 SO Pinout RY/BY# A8 A7 A7 A6 A5 A4 A3 A2 A A CE# VSS OE# DQ DQ8 DQ DQ9 DQ2 DQ DQ3 DQ Document Number: Rev. *B RESET# WE# A8 A9 A A A2 A3 A4 A5 A6 BYTE# VSS DQ5/A- DQ7 DQ4 DQ6 DQ3 DQ5 DQ2 DQ4 VCC Page 5 of 49

7 S29A8D Figure 3.3 Fine-pitch BGA Pinout (Top View, Balls Facing Down) 3. A6 B6 C6 D6 E6 F6 G6 H6 A3 A2 A4 A5 A6 BYTE# DQ5/A- VSS A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A A DQ7 DQ4 DQ3 DQ6 A4 B4 C4 D4 E4 F4 G4 H4 WE# RESET# NC NC DQ5 DQ2 VCC DQ4 A3 B3 C3 D3 E3 F3 G3 H3 RY/BY# NC A8 NC DQ2 DQ DQ DQ3 A2 B2 C2 D2 E2 F2 G2 H2 A7 A7 A6 A5 DQ DQ8 DQ9 DQ A B C D E F G H A3 A4 A2 A A CE# OE# VSS Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 5 C for prolonged periods of time. 4. Pin Configuration I/O Name Description A A8 9 addresses DQ DQ4 DQ5/A- BYTE# 5 data inputs/outputs DQ5 (data input/output, word mode), A- (SB address input, byte mode) Selects 8-bit or 6-bit mode CE# Chip enable OE# Output enable WE# Write enable RESET# Hardware reset pin, active low RY/BY# Ready/Busy# output VCC 3. volt-only single power supply (see Product Selector Guide on page 4 for speed options and voltage supply tolerances) VSS Device ground NC Pin not connected internally Document Number: Rev. *B Page 6 of 49

8 S29A8D 5. ogic Symbol 9 A A8 6 or 8 DQ DQ5 (A-) CE# OE# WE# RESET# BYTE# 6. RY/BY# Ordering Information This product has been retired and is not recommended for designs. For new and current designs, S29A8J supercedes S29A8D. This is the factory-recommended migration path. Please refer to the S29A8J data sheet for specifications and ordering information. 6. Standard Products Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. S29A8D T A I RI Packing Type = Tray = Tube 2 = 7 Tape and Reel 3 = 3 Tape and Reel Model Number = x8/x6, VCC = V, top boot sector device R = x8/x6, VCC = V. top boot sector device 2 = x8/x6, VCC = V, bottom boot sector device R2 = x8/x6, VCC = V. bottom boot sector device Temperature Range I = Industrial (-4 C to +85 C) N = Extended (-4 C to +25 C) Package Material Set A = Standard F = Pb-Free Package Type T = Thin Small Outline Package (TSOP) Standard Pinout B = Fine-pitch Ball-Grid Array Package M = Small Outline Package (SOP) Standard Pinout Speed Option = ns Access Speed 6 = 6 ns Access Speed 7 = 7 ns Access Speed 9 = 9 ns Access Speed Device Number/Description S29A8D 8 Megabit Flash Memory manufactured using 2 nm process technology 3. Volt-only Read, Program, and Erase Document Number: Rev. *B Page 7 of 49

9 S29A8D Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29A8D Valid Combinations Package Type, Material, and Temperature Range Model Number TAI, TFI R, R2 6, 7, 9 TAI, TFI, TAN, TFN, 2 BAI, BFI R, R2 6, 7, 9 BAI, BFI, BAN, BFN, 2 MAI, MFI R, R2 6, 7, 9 MAI, MFI, MAN, MFN, 2 Speed Option Device Number Packing Type S29A8D Package Description, 3 (Note ) TS48 (Note 3) TSOP, 2, 3 (Note ) VBK48 (Note 4) Fine-Pitch BGA,, 3 (Note 2) SO44 (Note 3) SOP Notes. Type is standard. Specify other options as required. 2. Type is standard. Specify other options as required. 3. TSOP and SOP package markings omit packing type designator from ordering part number. 4. BGA package marking omits leading S29 and packing type designator from ordering part number. 7. Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. S29A8D Device Bus Operations DQ8 DQ5 Operation CE# OE# WE# RESET# Addresses (Note ) DQ DQ7 BYTE# = VIH BYTE# = VI DQ8 DQ4 = High-Z, DQ5 = A- Read H H AIN DOUT DOUT Write H H AIN DIN DIN VCC.3 V VCC.3 V High-Z High-Z High-Z Output Disable H H H High-Z High-Z High-Z Reset High-Z High-Z High-Z Sector Protect (Note 2) H VID Sector Address, A6 =, A = H, A = DIN Sector Unprotect (Note 2) H VID Sector Address, A6 = H, A = H, A = DIN Temporary Sector Unprotect VID AIN DIN DIN High-Z Standby egend = ogic ow = VI H = ogic High = VIH VID = 2..5 V = Don t Care AIN = Address In DIN = Data In DOUT = Data Out Notes. Addresses are A8:A in word mode (BYTE# = VIH), A8:A- in byte mode (BYTE# = VI). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection/Unprotection on page 2. Document Number: Rev. *B Page 8 of 49

10 S29A8D 7. Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins DQ5 DQ operate in the byte or word configuration. If the BYTE# pin is set at logic, the device is in word configuration, DQ5 DQ are active and controlled by CE# and OE#. If the BYTE# pin is set at logic, the device is in byte configuration, and only data I/O pins DQ DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8 DQ4 are tri-stated, and the DQ5 pin is used as an input for the SB (A-) address function. 7.2 Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VI. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data on page 5 for more information. Refer to Table, Read Operations on page 3 for timing specifications and to Figure 5. on page 3 for the timing diagram. ICC in DC Characteristics on page 27 represents the active current specification for reading array data. 7.3 Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VI, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte Configuration on page 9 for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The Word/Byte Program Command Sequence on page 6 contains details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table on page and Table on page indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. The Command Definitions on page 5 contains details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7 DQ. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode on page 2 and Autoselect Command Sequence on page 6 for more information. ICC2 in DC Characteristics on page 27 represents the active current specification for the write mode. The AC Characteristics on page 3 contains timing specification tables and timing diagrams for write operations. 7.4 Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7 DQ. Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 2 for more information, and to AC Characteristics on page 3 for timing diagrams. 7.5 Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC.3 V, the device is in the standby mode, Document Number: Rev. *B Page 9 of 49

11 S29A8D but the standby current is greater. The device requires standard access time (tce) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In DC Characteristics on page 27, ICC3 and ICC4 represents the standby current specification. 7.6 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tacc + 3 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5 in DC Characteristics on page 27 represents the automatic sleep mode current specification. 7.7 RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of trp, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VI but not within VSS±.3 V, the standby current is greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a (busy) until the internal reset operation is complete, which requires a time of tready (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is ), the reset operation is completed within a time of tready (not during Embedded Algorithms). The system can read data trh after the RESET# pin returns to VIH. Refer to AC Characteristics on page 3 for RESET# parameters and to Figure 5.2 on page 3 for the timing diagram. 7.8 Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. S29A8D Top Boot Block Sector Addresses Address Range (in hexadecimal) Sector A8 A7 A6 A5 A4 A3 A2 Sector Size (Kbytes/ Kwords) SA h FFFFh h 7FFFh SA h FFFFh 8h FFFFh SA2 2h 2FFFFh h 7FFFh SA3 3h 3FFFFh 8h FFFFh SA4 4h 4FFFFh 2h 27FFFh SA5 5h 5FFFFh 28h 2FFFFh SA6 6h 6FFFFh 3h 37FFFh SA7 7h 7FFFFh 38h 3FFFFh SA8 8h 8FFFFh 4h 47FFFh SA9 9h 9FFFFh 48h 4FFFFh (x8) Address Range (x6) Address Range SA Ah AFFFFh 5h 57FFFh SA Bh BFFFFh 58h 5FFFFh SA2 Ch CFFFFh 6h 67FFFh Document Number: Rev. *B Page of 49

12 S29A8D S29A8D Top Boot Block Sector Addresses Address Range (in hexadecimal) Sector A8 A7 A6 A5 A4 A3 A2 Sector Size (Kbytes/ Kwords) SA3 Dh DFFFFh SA4 Eh EFFFFh 7h 77FFFh SA5 32/6 Fh F7FFFh 78h 7BFFFh SA6 8/4 F8h F9FFFh 7Ch 7CFFFh SA7 8/4 FAh FBFFFh 7Dh 7DFFFh SA8 6/8 FCh FFFFFh 7Eh 7FFFFh (x8) Address Range (x6) Address Range 68h 6FFFFh Note Address range is A8:A- in byte mode and A8:A in word mode. See Word/Byte Configuration on page 9. S29A8D Bottom Boot Block Sector Addresses Sector A8 A7 A6 A5 A4 A3 A2 Sector Size (Kbytes/ Kwords) SA SA SA2 SA3 SA4 SA5 SA6 SA7 SA8 Address Range (in hexadecimal) (x8) Address Range (x6) Address Range 6/8 h 3FFFh h FFFh 8/4 4h 5FFFh 2h 2FFFh 8/4 6h 7FFFh 3h 3FFFh 32/6 8h FFFFh 4h 7FFFh h FFFFh 8h FFFFh 2h 2FFFFh h 7FFFh 3h 3FFFFh 8h FFFFh 4h 4FFFFh 2h 27FFFh 5h 5FFFFh 28h 2FFFFh SA9 6h 6FFFFh 3h 37FFFh SA 7h 7FFFFh 38h 3FFFFh SA 8h 8FFFFh 4h 47FFFh SA2 9h 9FFFFh 48h 4FFFFh SA3 Ah AFFFFh 5h 57FFFh SA4 Bh BFFFFh 58h 5FFFFh SA5 Ch CFFFFh 6h 67FFFh SA6 Dh DFFFFh 68h 6FFFFh SA7 Eh EFFFFh 7h 77FFFh SA8 Fh FFFFFh 78h 7FFFFh Note Address range is A8:A- in byte mode and A8:A in word mode. See Word/Byte Configuration on page 9. Document Number: Rev. *B Page of 49

13 S29A8D 7.9 Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7 DQ. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (.5 V to 2.5 V) on address pin A9. Address pins A6, A, and A must be as shown in Table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table on page and Table on page ). Table shows the remaining address bits that are don t care. When all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on DQ7 DQ. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table on page 2. This method does not require VID. See Command Definitions on page 5 for details on using the autoselect mode. S29A8D Autoselect Codes (High Voltage Method) Description Mode Manufacturer ID: Spansion CE# OE# WE# A8 to A2 H Device ID: S29A8D (Top Boot Block) Word H Byte H Device ID: S29A8D (Bottom Boot Block) Word H Byte Sector Protection Verification H H SA A to A A9 A8 to A7 VID VID VID VID A6 A5 to A4 A3 to A2 A A H DQ8 to DQ5 DQ7 to DQ h 22h DAh H DAh 22h 5Bh 5Bh h (protected) h (unprotected) H egend = ogic ow = VI H = ogic High = VIH SA = Sector Address = Don t care. 7. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory prior to shipping the device through Spansion s ExpressFlash Service. Contact an Spansion representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 2 for details. Sector Protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 7.2 on page 4 shows the algorithms and Figure 5.2 on page 37 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3. volt-only Spansion flash devices. Publication number 2536 contains further details; contact an Spansion representative to request a copy. Document Number: Rev. *B Page 2 of 49

14 S29A8D 7. Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 7. shows the algorithm, and Figure 5. on page 37 shows the timing diagrams, for this feature. Figure 7. Temporary Sector Unprotect Operation START RESET# = VID (Note ) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Document Number: Rev. *B Page 3 of 49

15 S29A8D Figure 7.2 In-System Sector Protect/Sector Unprotect Algorithms START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PSCNT = RESET# = VID Wait ms Temporary Sector Unprotect Mode No PSCNT = RESET# = VID Wait ms First Write Cycle = 6h? First Write Cycle = 6h? Temporary Sector Unprotect Mode Yes Yes Set up sector address No All sectors protected? Sector Protect: Write 6h to sector address with A6 =, A =, A = Yes Set up first sector address Sector Unprotect: Write 6h to sector address with A6 =, A =, A = Wait 5 µs Increment PSCNT No Verify Sector Protect: Write 4h to sector address with A6 =, A =, A = Reset PSCNT = Read from sector address with A6 =, A =, A = Wait 5 ms Verify Sector Unprotect: Write 4h to sector address with A6 =, A =, A = Increment PSCNT No No PSCNT = 25? Yes Yes No Yes Device failed Protect another sector? No PSCNT =? Yes Remove VID from RESET# Device failed Write reset command Sector Protect Algorithm Read from sector address with A6 =, A =, A = Data = h? Sector Protect complete Set up next sector address No Data = h? Yes ast sector verified? No Yes Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Document Number: Rev. *B Page 4 of 49

16 S29A8D 7.2 Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table on page 2 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise ow VCC Write Inhibit When VCC is less than VKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VKO Write Pulse Glitch Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle ogical Inhibit Write cycles are inhibited by holding any one of OE# = VI, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one Power-Up Write Inhibit If WE# = CE# = VI and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. 8. Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table on page 2 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics on page Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands on page 9 for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See Reset Command on page 6. See also Requirements for Reading Array Data on page 9 for more information. Table, Read Operations on page 3 provides the read parameters, and Figure 5. on page 3 shows the timing diagram. Document Number: Rev. *B Page 5 of 49

17 S29A8D 8.2 Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). 8.3 Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table on page 2 shows the address and data requirements. This method is an alternative to that shown in Table on page 2, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address h retrieves the manufacturer code. A read cycle at address h in word mode (or 2h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 2h in word mode (or 4h in byte mode) returns h if that sector is protected, or h if it is unprotected. Refer to Table on page and Table on page for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. 8.4 Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table on page 2 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status on page 2 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The program command sequence should be reinitiated once the device resets to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a back to a. Attempting to do so may halt the operation and set DQ5 to, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read shows that the data is still. Only erase operations can convert a to a. 8.5 Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 2h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the Document Number: Rev. *B Page 6 of 49

18 S29A8D unlock bypass program command, Ah; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 9h; the second cycle the data h. Addresses are don t care for both cycles. The device then returns to reading array data. Table 8. illustrates the algorithm for the program operation. See Erase/Program Operations on page 33 for parameters, and Figure 5.5 on page 33 for timing diagrams. Figure 8. Program Operation START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes Increment Address No ast Address? Yes Programming Completed Note See Table on page 2 for program command sequence. Document Number: Rev. *B Page 7 of 49

19 S29A8D 8.6 Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table on page 2 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status on page 2 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 8.2 on page 9 illustrates the algorithm for the erase operation. See Erase/Program Operations on page 33 for parameters, and Figure 5.6 on page 34 for timing diagrams. 8.7 Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table on page 2 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 5 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. oading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 5 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 5 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase Timer on page 24.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status on page 2 for information on these status bits. Figure 8.2 on page 9 illustrates the algorithm for the erase operation. Refer to Erase/Program Operations on page 33 for parameters, and to Figure 5.6 on page 34 for timing diagrams. Document Number: Rev. *B Page 8 of 49

20 S29A8D 8.8 Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 5 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are don t-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 2 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation is suspended, the system can read array data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7 DQ. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 2 for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status on page 2 for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence on page 6 for more information. The system must write the Erase Resume command (address bits are don t care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device resumes erasing. Figure 8.2 Erase Operation START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes. See Table on page 2 for erase command sequence. 2. See DQ3: Sector Erase Timer on page 24 for more information. Document Number: Rev. *B Page 9 of 49

21 S29A8D Cycles S29A8D Command Definitions Command Sequence (Note ) Bus Cycles (Notes 2-5) First Second Addr Data Read (Note 6) RA RD Reset (Note 7) F Word Manufacturer ID 4 Autoselect (Note 8) Byte Addr Data 2AA AA AAA Addr Fourth Fifth Data Addr Data 9 22DA Word Byte AAA 2AA AAA 2 DA Device ID, Bottom Boot Block Word 2AA 225B AA 4 AA AAA 2 5B 2AA (SA) 2 Word (SA) 4 PA PD Byte AAA Word Program AA 2 A PA PD Unlock Bypass Reset (Note ) 2 9 (F) Word 6 Byte Word Sector Erase 2AA AA AAA 6 Byte B Erase Resume (Note 3) 3 8 AAA 2AA AA AAA Erase Suspend (Note 2) 8 AAA 2AA AA AAA 2 AAA Unlock Bypass Program (Note ) Chip Erase A AAA 2AA AA AAA 3 Byte 9 AAA 2AA AA AAA Word Unlock Bypass 4 Byte Data 9 AAA 4 Addr 9 Byte Sector Protect Verify (Note 9) Sixth Data AAA Device ID, Top Boot Block 4 Addr Third AAA 2AA AA AAA SA 3 egend = Don t care RA = Address of the memory location to be read RD = Data read from location RA during read operation, and PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A8 A2 uniquely select any sector. Notes. See Table on page 8 for a description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Data bits DQ5 DQ8 are don t cares for unlock and command cycles. 5. Address bits A8 A are don t cares for unlock and command cycles, unless PA or SA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. The data is h for an unprotected sector and h for a protected sector. See Autoselect Command Sequence on page 6 for more information.. The Unlock Bypass command is required prior to the Unlock Bypass Program command.. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 2. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 3. The Erase Resume command is valid only during the Erase Suspend mode. Document Number: Rev. *B Page 2 of 49

22 S29A8D 9. Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table on page 25 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. 9. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately µs, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to ; prior to this, the device outputs the complement, or. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 changes from the complement to true data, it can read valid data at DQ7 DQ on the following read cycles. This is because DQ7 may change asynchronously with DQ DQ6 while Output Enable (OE#) is asserted low. Figure 5.8, Data# Polling Timings (During Embedded Algorithms) on page 35, illustrates this. Table on page 25 shows the outputs for Data# Polling on DQ7. Figure 9. on page 22 shows the Data# Polling algorithm. Document Number: Rev. *B Page 2 of 49

23 S29A8D Figure 9. Data# Polling Algorithm START Read DQ7 DQ Addr = VA DQ7 = Data? Yes No No DQ5 =? Yes Read DQ7 DQ Addr = VA DQ7 = Data? Yes No FAI PASS Notes. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = because DQ7 may change simultaneously with DQ RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table on page 25 shows the outputs for RY/BY#. Figure 5. on page 3, Figure 5.2 on page 3, Figure 5.5 on page 33 and Figure 5.6 on page 34 shows RY/BY# for read, reset, program, and erase operations, respectively. 9.3 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. Document Number: Rev. *B Page 22 of 49

24 S29A8D After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 2). If a program address falls within a protected sector, DQ6 toggles for approximately µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table on page 25 shows the outputs for Toggle Bit I on DQ6. Figure 9.2 on page 24 shows the toggle bit algorithm. Figure 5.9 on page 36 shows the toggle bit timing diagrams. Figure 5. on page 36 shows the differences between DQ2 and DQ6 in graphical form. See also DQ2: Toggle Bit II on page DQ2: Toggle Bit II The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table on page 25 to compare outputs for DQ2 and DQ6. Figure 9.2 on page 24 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 23 explains the algorithm. See also DQ6: Toggle Bit I on page 22. Figure 5.9 on page 36 shows the toggle bit timing diagram. Figure 5. on page 36 shows the differences between DQ2 and DQ6 in graphical form. 9.5 Reading Toggle Bits DQ6/DQ2 Refer to Figure 9.2 on page 24 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7 DQ at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device completed the program or erase operation. The system can read array data on DQ7 DQ on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see DQ5: Exceeded Timing imits on page 23). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 9.2 on page 24). 9.6 DQ5: Exceeded Timing imits DQ5 indicates whether the program or erase time exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a. This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a to a location that is previously programmed to. Only an erase operation can change a back to a. Under this condition, the device halts the operation, and when the operation exceeds the timing limits, DQ5 produces a. Document Number: Rev. *B Page 23 of 49

25 S29A8D Under both these conditions, the system must issue the reset command to return the device to reading array data. 9.7 DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation started. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from to. The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands is always less than 5 µs. See also Sector Erase Command Sequence on page 8. Figure 9.2 Toggle Bit Algorithm START Read DQ7 DQ (Note ) Read DQ7 DQ Toggle Bit = Toggle? No Yes No DQ5 =? Yes Read DQ7 DQ Twice (Notes, 2) Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to. See text. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device accepted the command sequence, and then read DQ3. If DQ3 is, the internally controlled erase cycle started; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is, the device accepts additional sector erase commands. To ensure the command is accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not be accepted. Table shows the outputs for DQ3. Document Number: Rev. *B Page 24 of 49

26 S29A8D Write Operation Status DQ7 (Note 2) DQ6 DQ5 (Note ) DQ3 DQ2 (Note 2) DQ7# Toggle N/A No toggle Embedded Erase Algorithm Toggle Toggle Reading within Erase Suspended Sector No toggle N/A Toggle Reading within Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle N/A N/A Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm RY/BY# Notes. DQ5 switches to when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See DQ5: Exceeded Timing imits on page 23 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.. Absolute Maximum Ratings Parameter Rating Storage Temperature Plastic Packages 65 C to +5 C Ambient Temperature with Power Applied 65 C to +25 C Voltage with Respect to Ground VCC (Note ).5 V to +4. V A9, OE#, and RESET# (Note 2).5 V to +2.5 V All other pins (Note ) Output Short Circuit Current (Note 3).5 V to VCC+.5 V 2 ma Notes. Minimum DC voltage on input or I/O pins is.5 V. During voltage transitions, input or I/O pins may undershoot VSS to 2. V for periods of up to 2 ns. See Figure. on page 26. Maximum DC voltage on input or I/O pins is VCC +.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2. V for periods up to 2 ns. See Figure.2 on page Minimum DC input voltage on pins A9, OE#, and RESET# is.5 V. During voltage transitions, A9, OE#, and RESET# may undershoot VSS to 2. V for periods of up to 2 ns. See Figure. on page 26. Maximum DC input voltage on pin A9 is +2.5 V which may overshoot to 4. V for periods up to 2 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: Rev. *B Page 25 of 49

27 S29A8D. Operating Ranges Industrial (I) Devices Ambient Temperature (TA) -4 C to +85 C Extended (N) Devices Ambient Temperature (TA) -4 C to +25 C VCC Supply Voltages VCC for regulated voltage range+3. V to +3.6 V VCC for full voltage range +2.7 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed Figure. Maximum Negative Overshoot Waveform 2 ns 2 ns +.8 V.5 V 2. V 2 ns Figure.2 Maximum Positive Overshoot Waveform 2 ns VCC +2. V VCC +.5 V 2. V 2 ns Document Number: Rev. *B 2 ns Page 26 of 49

28 S29A8D 2. DC Characteristics Parameter Description Test Conditions Min II Input oad Current VIN = VSS to VCC, VCC = VCC max IIT A9 Input oad Current VCC = VCC max; A9 = 2.5 V IO Output eakage Current VOUT = VSS to VCC, VCC = VCC max. µa 35 µa. µa MHz 2 4 MHz MHz 9 6 MHz 2 4 CE# = VI, OE# = VIH 2 35 ma ma CE# = VI, OE# = VIH, Word Mode ICC2 Unit 5 MHz VCC Active Read Current (Notes, 2) VCC Active Write Current (Notes 2, 3, 6) Max MHz CE# = VI, OE# = VIH, Byte Mode ICC Typ ICC3 VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC.3 V.2 5 µa ICC4 VCC Reset Current (Notes 2, 4) RESET# = VSS.3 V.2 5 µa ICC5 Automatic Sleep Mode (Notes 2, 4, 5) VIH = VCC.3 V; VI = VSS.3 V.2 5 µa VI Input ow Voltage.5.8 V VIH Input High Voltage.7 x VCC VCC +.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.3 V V VO Output ow Voltage IO = 4. ma, VCC = VCC min.45 V VOH Output High Voltage VOH2 VKO IOH = 2. ma, VCC = VCC min 2.4 IOH = µa, VCC = VCC min VCC.4 ow VCC ock-out Voltage 2.3 V 2.5 V Notes. The ICC current listed is typically less than 2 ma/mhz, with OE# at VIH. Typical VCC is 3. V. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. At extended temperature range (>+85 C), typical current is 5µA and maximum current is µa. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tacc + 3 ns. 6. Not % tested. Document Number: Rev. *B Page 27 of 49

29 S29A8D 2. Zero Power Flash Figure 2. ICC Current vs. Time (Showing Active and Automatic Sleep Currents) Supply Current in ma Time in ns Note Addresses are switching at MHz Figure 2.2 Typical ICC vs. Frequency Supply Current in ma V V Frequency in MHz Note T = 25 C Document Number: Rev. *B Page 28 of 49

30 S29A8D 3. Test Conditions Figure 3. Test Setup 3.3 V 2.7 k Device Under Test C 6.2 k Note Nodes are IN364 or equivalent. Test Specifications Test Condition 6 Output oad 7 9 Unit pf TT gate Output oad Capacitance, C (including jig capacitance) 3 Input Rise and Fall Times Input Pulse evels ns. or VCC Input timing measurement reference levels.5 VCC Output timing measurement reference levels.5 VCC V 4. Key to Switching Waveforms Waveform Inputs Outputs Steady Changing from H to Changing from to H Document Number: Rev. *B Don t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center ine is High Impedance State (High Z) Page 29 of 49

31 S29A8D Figure 4. Input Waveforms and Measurement evels VCC.5 VCC Input.5 VCC Measurement evel Output. V 5. AC Characteristics Read Operations Parameter Speed Options JEDEC Std Description tavav trc Read Cycle Time (Note ) tavqv tacc Address to Output Delay Test Setup Min CE# = VI OE# = VI Max OE# = VI teqv tce Chip Enable to Output Delay Max tgqv toe Output Enable to Output Delay Max tehqz tdf Chip Enable to Output High Z (Note ) Max 6 tghqz tdf Output Enable to Output High Z (Note ) Max 6 atency Between Read and Write Operations tsr/w taq Min 2 Read Min Toggle and Data# Polling Min Min toeh Output Enable Hold Time (Note ) toh Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note ) Unit ns Notes. Not % tested. 2. See Figure 3. on page 29 and DC Characteristics on page 27 for test specifications. Figure 5. Read Operations Timings trc Addresses Stable Addresses tacc CE# tdf OE# toe tsr/w toeh WE# tce toh HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# V Document Number: Rev. *B Page 3 of 49

32 S29A8D Hardware Reset (RESET#) Parameter JEDEC Std Description tready RESET# Pin ow (During Embedded Algorithms) to Read or Write (See Note) Test Setup All Speed Options Unit 2 µs Max RESET# Pin ow (NOT During Embedded Algorithms) to Read or Write (See Note) 5 trp RESET# Pulse Width 5 trh RESET# High Time Before Read (See Note) trpd RESET# ow to Standby Mode 2 µs trb RY/BY# Recovery Time ns tready ns 5 Min Note Not % tested. Figure 5.2 RESET# Timings RY/BY# CE#, OE# trh RESET# trp tready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tready RY/BY# trb CE#, OE# RESET# trp Document Number: Rev. *B Page 3 of 49

33 S29A8D Word/Byte Configuration (BYTE#) Parameter JEDEC Speed Options Std Description tef/tefh CE# to BYTE# Switching ow or High Max tfqz BYTE# Switching ow to Output HIGH Z Max tfhqv BYTE# Switching High to Output Active Min Unit 5 ns 6 6 Figure 5.3 BYTE# Timings for Read Operations CE# OE# BYTE# tef BYTE# Switching from word to byte mode Data Output (DQ DQ4) DQ DQ4 Data Output (DQ DQ7) Address Input DQ5 Output DQ5/A- tfqz tefh BYTE# BYTE# Switching from byte to word mode DQ DQ4 DQ5/A- Data Output (DQ DQ7) Address Input Data Output (DQ DQ4) DQ5 Output tfhqv Document Number: Rev. *B Page 32 of 49

34 S29A8D Figure 5.4 BYTE# Timings for Write Operations CE# The falling edge of the last WE# signal WE# BYTE# tset (tas) thod (tah) Note Refer to Erase/Program Operations on page 33 for tas and tah specifications. 5. Erase/Program Operations Parameter Speed Options JEDEC Std Description tavav twc Write Cycle Time (Note ) tavw tas Address Setup Time twa tah Address Hold Time tdvwh tds Data Setup Time twhd tdh Data Hold Time toes Output Enable Setup Time tghw tghw tew tcs CE# Setup Time twheh tch CE# Hold Time twwh twp Write Pulse Width 35 twhw twph Write Pulse Width High 3 tsr/w atency Between Read and Write Operations 2 Byte twhwh Programming Operation (Note 2) twhwh2 twhwh2 Sector Erase Operation (Note 2) ns Min Read Recovery Time Before Write (OE# High to WE# ow) twhwh Unit ns 7 µs Word Typ 7.7 sec tvcs VCC Setup Time (Note ) Min 5 µs trb Recovery Time from RY/BY# Min Program/Erase Valid to RY/BY# Delay Max 9 tbusy ns Notes. Not % tested. 2. See Erase and Programming Performance on page 39 for more information. Figure 5.5 Program Operation Timings Notes. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode Document Number: Rev. *B Page 33 of 49

35 S29A8D Program Command Sequence (last two cycles) tas twc Addresses Read Status Data (last two cycles) h PA PA PA tah CE# tch OE# twhwh twp WE# twph tcs tds td PD Ah Data Status tbusy DOUT trb RY/BY# VCC tvcs Figure 5.6 Chip/Sector Erase Operation Timings Erase Command Sequence (last two cycles) tas twc Addresses Read Status Data 2AAh SA VA h for chip erase VA tah CE# tch OE# twp WE# twph tcs twhwh2 tds tdh Data h In Progress 3h Complete for Chip Erase tbusy trb RY/BY# tvcs VCC Notes. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 2). 2. Illustration shows device in word mode. Document Number: Rev. *B Page 34 of 49

36 S29A8D Figure 5.7 Back to Back Read/Write Cycle Timing twc Addresses trc PA RA PA tacc tah tcph tce CE# PA tcp toe tsr/w OE# tghw twp WE# twdh tdf tds Data toh tdh Valid In Valid Out Valid In Valid Out Figure 5.8 Data# Polling Timings (During Embedded Algorithms) trc Addresses VA VA VA tacc tce CE# tch toe OE# toeh tdf WE# toh DQ7 Complement Complement DQ DQ6 Status Data Status Data True True Valid Data Valid Data High Z High Z tbus RY/BY# Note VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle Document Number: Rev. *B Page 35 of 49

37 S29A8D Figure 5.9 Toggle Bit Timings (During Embedded Algorithms) trc Addresses VA VA VA VA tacc tce CE# tch toe OE# toeh tdf WE# toh High Z DQ6/DQ2 tbus Valid Status Valid Status (first read) (second read) Valid Status Valid Data (stops toggling) RY/BY# Note VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 5. DQ2 vs. DQ6 Enter Embedded Erasing Erase Suspend Erase Suspend Read Erase WE# Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Temporary Sector Unprotect Parameter JEDEC Std Description All Speed Options Unit tvidr VID Rise and Fall Time (See Note) Min 5 ns trsp RESET# Setup Time for Temporary Sector Unprotect Min 4 µs Note Not % tested. Document Number: Rev. *B Page 36 of 49

38 S29A8D Figure 5. Temporary Sector Unprotect Timing Diagram 2 V RESET# or 3 V or 3 V tvidr tvidr Program or Erase Command Sequence CE# WE# trsp RY/BY# Figure 5.2 Sector Protect/Unprotect Timing Diagram VID VIH RESET# SA, A6, Valid* Valid* Valid* A, A Sector Protect/Unprotect Data 6h µs Verify 6h 4h Status Sector Protect: 5 µs Sector Unprotect: 5 ms CE# WE# OE# Note For sector protect, A6 =, A =, A =. For sector unprotect, A6 =, A =, A =. Document Number: Rev. *B Page 37 of 49

39 S29A8D Alternate CE# Controlled Erase/Program Operations Parameter Speed Options JEDEC Std tavav twc Write Cycle Time (Note ) tave tas Address Setup Time tea tah Address Hold Time 45 tdveh tds Data Setup Time tehd tdh Data Hold Time toes Output Enable Setup Time tghe Read Recovery Time Before Write (OE# High to WE# ow) tghe Description Min twe tws WE# Setup Time tehwh twh WE# Hold Time teeh tcp CE# Pulse Width 35 tehe tcph CE# Pulse Width High 3 tsr/w atency Between Read and Write Operations twhwh twhwh Programming Operation (Note 2) twhwh2 twhwh2 Sector Erase Operation (Note 2) Unit 2 Byte ns ns 7 µs Word Typ 7.7 sec Notes. Not % tested. 2. See Erase and Programming Performance on page 39 for more information. Document Number: Rev. *B Page 38 of 49

40 S29A8D Figure 5.3 Alternate CE# Controlled Write Operation Timings for program PA for program SA for sector erase 2AA for erase for chip erase Data# Polling Addresses PA twc tas tah twh WE# tghe OE# twhwh or 2 tcp CE# tws tcph tbusy tds tdh DQ7# Data trh A for program for erase DOUT PD for program 3 for sector erase for chip erase RESET# RY/BY# Notes. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of command sequence. 3. Word mode address used as an example. 5.2 Erase and Programming Performance Typ (Note ) Max (Note 2) Unit Sector Erase Time Parameter.7 s Chip Erase Time 4 s Byte Programming Time 7 2 µs Word Programming Time 7 2 µs Chip Programming Time Byte Mode s (Note 3) Word Mode s Comments Excludes h programming prior to erasure Excludes system level overhead (Note 5) Notes. Typical program and erase times assume the following conditions: 25 C, 3. V VCC,,, cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 9 C, VCC = 2.7 V,,, cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table on page 2 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of,, cycles. Document Number: Rev. *B Page 39 of 49

41 S29A8D atchup Characteristics Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Description. V 2.5 V Input voltage with respect to VSS on all I/O pins. V VCC +. V ma + ma VCC Current Note Includes all pins except VCC. Test conditions: VCC = 3. V, one pin at a time. TSOP, SO, and BGA Pin Capacitance Parameter Symbol Parameter Description Test Setup CIN Input Capacitance VIN = COUT Output Capacitance CIN2 Control Pin Capacitance VOUT = VIN = Package Typ Max TSOP, SO BGA TSOP, SO BGA TSOP, SO BGA Unit pf Notes. Sampled, not % tested. 2. Test conditions TA = 25 C, f =. MHz. Document Number: Rev. *B Page 4 of 49

42 S29A8D 6. Physical Dimensions 6. TS Pin Standard TSOP PACKAGE TS/TSR 48 JEDEC MO-42 (B) DD SYMBO NOTES: MIN NOM MA A A A b b c c D D E e.5 BASIC.5.6 CONTROING DIMENSIONS ARE IN MIIMETERS (mm). (DIMENSIONING AND TOERANCING CONFORM TO ANSI Y4.5M-982) 2. PIN IDENTIFIER FOR STANDARD PIN OUT (DIE UP). 3. PIN IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR ASER MARK. 4. TO BE DETERMINED AT THE SEATING PANE -C-. THE SEATING PANE IS DEFINED AS THE PANE OF CONTACT THAT IS MADE WHEN THE PACKAGE EADS ARE AOWED TO REST FREEY ON A FAT HORIZONTA SURFACE. 5. DIMENSIONS D AND E DO NOT INCUDE MOD PROTRUSION. AOWABE MOD PROTUSION IS.5mm (.59") PER SIDE. 6. DIMENSION b DOES NOT INCUDE DAMBAR PROTUSION. AOWABE DAMBAR PROTUSION SHA BE.8mm (.3") TOTA IN ECESS OF b DIMENSION AT MA. MATERIA CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT EAD TO BE.7mm (.28"). 7. THESE DIMENSIONS APPY TO THE FAT SECTION OF THE EAD BETWEEN.mm (.39") AND.25mm (.98") FROM THE EAD TIP. 8. EAD COPANARITY SHA BE WITHIN.mm (.4") AS MEASURED FROM THE SEATING PANE. 9. DIMENSION "e" IS MEASURED AT THE CENTERINE OF THE EADS..7 Θ R N \ \ 7..7 Note For reference only. BSC is an ANSI standard for Basic Space Centering. Document Number: Rev. *B Page 4 of 49

43 S29A8D 6.2 VBK Ball Fine-Pitch Ball Grid Array (FBGA) 8.5 x 6.5 mm. (4) D D A 6 5 e 7 4 E SE E 3 2 H PIN A CORNER INDE MARK 6 B G F fb E D C SD B A A CORNER 7 f.8 M C TOP VIEW f.5 M C A B BOTTOM VIEW A. C A2 SEATING PANE A C.8 C SIDE VIEW NOTES: PACKAGE VBK 48 JEDEC. DIMENSIONING AND TOERANCING PER ASME Y4.5M-994. N/A 2. A DIMENSIONS ARE IN MIIMETERS. 6.5 mm x 8.5 mm NOM PACKAGE SYMBO MIN NOM MA A A A BA POSITION DESIGNATION PER JESD 95-, SPP- (ECEPT AS NOTED). NOTE OVERA THICKNESS BA HEIGHT 8.5 BSC. BODY SIZE E 6.5 BSC. BODY SIZE D 5.6 BSC. BA FOOTPRINT E 4. BSC. MD 8 ROW MATRI SIZE D DIRECTION ME 6 ROW MATRI SIZE E DIRECTION N BA FOOTPRINT TOTA BA COUNT.43 BA DIAMETER e.8 BSC. BA PITCH SD / SE.4 BSC. SODER BA PACEMENT --- DEPOPUATED SODER BAS e REPRESENTS THE SODER BA GRID PITCH. 5. SYMBO "MD" IS THE BA ROW MATRI SIZE IN THE "D" DIRECTION. SYMBO "ME" IS THE BA COUMN MATRI SIZE IN THE "E" DIRECTION. BODY THICKNESS D fb 4. N IS THE TOTA NUMBER OF SODER BAS. 6 DIMENSION "b" IS MEASURED AT THE MAIMUM BA DIAMETER IN A PANE PARAE TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SODER BA IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SODER BAS IN THE OUTER ROW PARAE TO THE D OR E DIMENSION, RESPECTIVEY, SD OR SE =.. WHEN THERE IS AN EVEN NUMBER OF SODER BAS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICA CENTER OF DEPOPUATED BAS. A CORNER TO BE IDENTIFIED BY CHAMFER, ASER OR INK MARK, METAIZED MARK INDENTATION OR OTHER MEANS \ b Document Number: Rev. *B Page 42 of 49

44 S29A8D 6.3 SO Pin Small Outline Package Dwg rev AC; /99 Document Number: Rev. *B Page 43 of 49

45 S29A8D 7. Revision History Spansion Publication Number: S29A8D_ 7. Revision A (September 8, 24) Initial release 7.2 Revision A (February 8, 25) Global Updated Trademark Ordering Information Added Package type designator Valid Combinations Changed Package Type, Material, and Temperature Range designator Under Package Descriptions, change SSOP to SOP 7.3 Revision A2 (June, 25) Global Updated status from Advance Information to Preliminary data sheet. Distinctive Characteristics Updated manufactured process technology. Updated high performance access time. Added extended temperature range. Added cycling endurance information. Production Selector Guide Added ns speed option and column. Ordering Information Added tube and tray packing types. Added extended temperature range Added model numbers. Valid Combinations Table Added speed option. Added packing types. Added model number. Added note for this table. Operating Range Added extended temperature range information. Test Conditions Added ns speed option. AC Characteristics Read Operation Table: Added ns speed option. Word/Byte Configuration Table: Added ns speed option. Erase/Program Operation Table: Added ns speed option. Alternate CE# Controlled Erase/Program Operation Table: Added ns speed option. Erase and Programming Performance: Changed Byte Programing Time values for Typical and Maximum. Document Number: Rev. *B Page 44 of 49

46 S29A8D 7.4 Revision A3 (June 6, 25) Changed from Preliminary to full Data Sheet. Updated Valid Combinations table. 7.5 Revision A4 (February 6, 26) Corrected minor typo on page. Added cover page. 7.6 Revision A5 (May 22, 26) AC Characteristics Added tsr/w parameter to read and erase/program operations tables. Added back-to-back read/write cycle timing diagram. Changed maximum value for tdf and tfqz. 7.7 Revision A6 (September 6, 26) Global Added 6 ns speed option. 7.8 Revision A7 (October 3, 26) Automatic Sleep Mode Changed ICC4 to ICC5 in description. AC Characteristics, Erase / Program Operations Changed tbusy to a maximum value. 7.9 Revision A8 (August 29, 27) TS48 Physical dimensions Changed Revision from AA to E: changed degrees (max) from 5 to 8 7. Revision A9 (September 9, 27) Product Selector Guide Changed TOE for ns access speed Autoselect Codes Table Changed part references to A8D Added A3 to A2 column Command Definitions Table Added F as an alternative 2nd cycle command for Unlock Bypass Reset Test Specifications Table Added C = 3 pf under 6 ns access speed Changed Input Pulse evels, Input and Output timing measurement reference levels Erase/Program Operations Table Changed value of Programming Operation for Byte mode Document Number: Rev. *B Page 45 of 49

47 S29A8D Alternate CE# Controlled Erase/Program Operations Table Changed values of Program Operation for both Byte & Word modes Changed value of Sector Erase Operation 7. Revision A (November 27, 27) Figure: Input Waveforms and Measurement evels Updated figure 7.2 Revision A (February 27, 29) Global Added obsolescence information to Cover Sheet, Distinctive Characteristics, and Ordering Information sections of data sheet. Document History Page Document Title:S29A8D, 8-Mbit (M x 8-Bit/52K x 6-Bit), 3 V Boot Sector Flash Document Number: Rev. ECN No. Orig. of Change ** - BWHA Submission Date Description of Change 9/8/24 Initial release 2/8/25 Global: Updated Trademark Ordering Information Added Package type designator Valid Combinations Changed Package Type, Material, and Temperature Range designator Under Package Descriptions, change SSOP to SOP Document Number: Rev. *B Page 46 of 49

48 S29A8D Document History Page (Continued) Document Title:S29A8D, 8-Mbit (M x 8-Bit/52K x 6-Bit), 3 V Boot Sector Flash Document Number: Rev. ** ECN No. - Orig. of Change BWHA Submission Date Description of Change 6//25 Global Updated status from Advance Information to Preliminary data sheet. Distinctive Characteristics Updated manufactured process technology. Updated high performance access time. Added extended temperature range. Added cycling endurance information. Production Selector Guide Added ns speed option and column. Ordering Information Added tube and tray packing types. Added extended temperature range Added model numbers. Valid Combinations Table Added speed option. Added packing types. Added model number. Added note for this table. Operating Range Added extended temperature range information. Test Conditions Added ns speed option.ac Characteristics Read Operation Table: Added ns speed option. Word/Byte Configuration Table: Added ns speed option. Erase/Program Operation Table: Added ns speed option. Alternate CE# Controlled Erase/Program Operation Table: Added ns speed option. Erase and Programming Performance: Changed Byte Programing Time values for Typical and Maximum. 6/6/25 Changed from Preliminary to full Data Sheet. Updated Valid Combinations table. 2/6/26 Corrected minor typo on page. Added cover page. 5/22/26 AC Characteristics Added tsr/w parameter to read and erase/program operations tables. Added back-to-back read/write cycle timing diagram. Changed maximum value for tdf and tfqz. ** - BWHA 9/6/26 Global Added 6 ns speed option. /3/26 Automatic Sleep Mode Changed ICC4 to ICC5 in description. AC Characteristics, Erase / Program Operations Changed tbusy to a maximum value. 8/29/27 TS48 Physical dimensions Changed Revision from AA to E: changed degrees (max) from 5 to 8 Document Number: Rev. *B Page 47 of 49

49 S29A8D Document History Page (Continued) Document Title:S29A8D, 8-Mbit (M x 8-Bit/52K x 6-Bit), 3 V Boot Sector Flash Document Number: Rev. ** ECN No. - Orig. of Change BWHA Submission Date Description of Change 9/9/27 Product Selector Guide Changed TOE for ns access speed Autoselect Codes Table Changed part references to A8D Added A3 to A2 column Command Definitions Table Added F as an alternative 2nd cycle command for Unlock Bypass Reset Test Specifications Table Added C = 3 pf under 6 ns access speed Changed Input Pulse evels, Input and Output timing measurement reference levels Erase/Program Operations Table Changed value of Programming Operation for Byte mode Alternate CE# Controlled Erase/Program Operations Table Changed values of Program Operation for both Byte & Word modes Changed value of Sector Erase Operation /27/27 Figure: Input Waveforms and Measurement evels Updated figure 2/27/29 Global Added obsolescence information to Cover Sheet, Distinctive Characteristics, and Ordering Information sections of data sheet. *A 5435 BWHA *B PRIT 2/9/25 Updated to cypress template. /24/27 Obsolete document. Completing Sunset Review. Document Number: Rev. *B Page 48 of 49

50 S29A8D Sales, Solutions, and egal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer s representatives, and distributors. To find the office closest to you, visit us at Cypress ocations. Products PSoC Solutions Automotive...cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers... cypress.com/go/clocks PSoC PSoC 3 PSoC 4 PSoC 5P Interface... cypress.com/go/interface Cypress Developer Community ighting & Power Control... cypress.com/go/powerpsoc Community Forums Blogs Video Training Memory... cypress.com/go/memory PSoC...cypress.com/go/psoc Touch Sensing... cypress.com/go/touch Technical Support cypress.com/go/support USB Controllers...cypress.com/go/USB Wireless/RF... cypress.com/go/wireless Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EPRESS OR IMPIED, WITH REGARD TO THIS MATERIA, INCUDING, BUT NOT IMITED TO, THE IMPIED WARRANTIES OF MERCHANTABIITY AND FITNESS FOR A PARTICUAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: Rev. *B Revised January 24, 27 Page 49 of 49 Cypress, Spansion, MirrorBit, MirrorBit Eclipse, ORNAND, EcoRAM, HyperBus, HyperFlash, and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.