ARINC-629 Interface to PMC Sy629PMC-BPM

Transcription

1 ARINC-629 Interface to PMC Sy629PMC-BPM Summary features Interface compatible with 32bit PCI Local bus Specification, revision 2.1, June 1995 PCI interrupts on Module Events Single width PMC Module Uses Boeing approved DATAC device Direct access to XPP and RPP from PCI Block & Independent Modes Choice of: Dual Data Buffers or Cyclic Data Buffers High Resolution System Timer Auto Cyclic Redundancy Checking (CRC) Auto Refresh Counter Support Bus Monitoring Transmit Monitoring Error Status Reporting Rx Time-Stamping External Timer Clock input FIFO buffers for Rx data and Time-Stamp Time-Stamp resolution 0.5μS General Description: The Sy629PMC-BPM card provides a convenient means for transmitting and receiving data over an ARINC 629 bus in accordance with the transmit and receive programme defined by data written into the XPP and RPP memory. The use of the recognised DATAC chip ensures full compliance with ARINC 629 specification with Basic Protocol (BP). ARINC-629 Input/Output is via a connector on the PMC module faceplate. Two further connectors on the faceplate provide Arinc-629 Pseudo-Bus connection and external power for the ARINC-629 SIM and stub cable. The module provides configuration registers which allow the host to: Automatically identify the module and its revision status. Identify connector cables connected to the module. Assign address space for the module s data buffer memory and registers. (Plug-in and Play). Control and monitor the PCI bus interface to the module. Read module interrupt configuration as assigned by the POST software as it initialises and configures the system. Additional features designed into the module are: 16 Independent Cyclic-Data-Buffers, each with a capacity for 4k x 32-bit words. Direct access to the Cyclic-Data-Buffer Read / Write Pointers. High resolution time-stamping of received data. PCI interrupts on Module Events. Direct access to Module registers and application memory. Interface compatible with 32bit PCI Local bus Specification, revision 2.1, June 1995.

2 The PMC module is designed to be used in a "Plug-in and Play" environment which is made possible, not only by the choice of PCI interface, but also by the provision of various identification and module present registers. These include: Device ID Vendor ID Subsystem ID Subsystem Vendor ID Connector ID / Present Module ID Using these registers the host can detect the presence of the module and its connector, determine if this is consistent with system requirements and respond accordingly by configuring the system or reporting system deficiencies. Cyclic Data Buffers: The PMC module provides high speed PCI interfacing to up to 16 Cyclic-Data-Buffers to support transmission and reception of ARINC-629 words. Two of these are configured for transferring ARINC-629 transmit data to the Tx data buffer, while the others are configured for reception of Arinc-629 data from the Rx data buffer. The user is free to read and write to any of the Cyclic-Data-Buffers independent of their type (Tx or Rx). However, the Cyclic-Data-Buffer data transfer system only responds in strict accordance to the channel type. That is, it will transfer data, written to a Tx Cyclic-Data-Buffer, to the appropriate module channel and write received data to the corresponding Rx Cyclic-Data-Buffer. Received data can be transferred automatically to assigned Cyclic-Data-Buffers or accessed directly from Dual Data Buffers. The ARINC-629 data is stored in the least significant 16 bits of the 4 byte Cyclic Buffer locations, while transceiver generated addresses and Control/Status information are stored in the most significant bytes. The Cyclic-Data-Buffers are controlled according to simple rules. The Cyclic-Data-Buffer read pointers and write pointers can be read by the host processor to assist in the data transfer process. In practice, the user writes data for transmission to consecutive long word locations in the Cyclic-Data-Buffer. Only valid words are transmitted. Receive data is automatically written to consecutive locations in the selected Cyclic-Data-Buffer. Receive Sub-System: The RPP defines the required DATAC response to ARINC 629 data reception. This data is arranged in 8 byte cells which define: Labels of interest Requirement for data collection and storage Address for storing data in local memory Assignment of Rx interrupts Address offset The RPP is implemented in 32kbytes of static RAM accessible to the host computer via the PCIbus. All 12 bits of the ARINC 629 labels are decoded to provide a capability for monitoring all bus traffic. The received data can be directed to any of the 14 dual data buffers and/or the Receive Data FIFO.

3 Transmit Sub-System: The transmission is controlled by data placed in the XPP RAM by the user software. Word-strings scheduled for transmission are defined by 8 byte cells in the XPP as specified by ARINC 629. The XPP is implemented in static RAM and provides decoding for all 32 x 32 Cells. Data for transmission is drawn from 32kbytes of static RAM in accordance with the address data written in the XPP. This static RAM is divided into two 16kbyte buffers, where only one buffer is accessible to the DATAC transceiver at a time. The user can request a buffer change whenever necessary by writing to a control register. The transmit buffer will change when the ARINC 629 bus is quiet between messages. An interrupt can be triggered on buffer change and the active buffer can be identified from a status register. Event Monitoring & Interrupt Facilities: When Rx data is directed to the Receive Data Cyclic Buffers, corresponding status information is placed in a Status FIFO. This status information includes: Label + Extension 32 bit Time Stamp (0.5µs resolution) word and word-string count error status This information can also be recorded for transmitted data and/or received data placed in the dual static RAM buffers. Interrupts can be triggered immediately before or after transmission/reception of any assigned labels. A user defined vector can be monitored when such an interrupt occurs. These vectors are stored in an Event-Status- FIFO so that no interrupts will be lost. PCI interrupts can be generated when there is data in the Event-Status- FIFO. The cause of an interrupt can be determined by reading the FIFO. If the FIFO is empty when read, then a zero status is returned. Other events for which interrupts can be generated include: Data/Status FIFOs full/half full Change of data buffer Start of new message Transmit or receive error detected Start/end of transmission External clock reset pulse Control & Status Registers: Control registers are provided to configure the terminal for a particular ARINC 629 system requirement. These include: Assignment of SG, TI, TG Assignment of CID Other control and status registers are provided which enable the full potential of the board to be realised. All of these registers are accessed in 16 bit word mode. Hardware is provided for performing Cyclic Redundancy Checking (CRC) of transmitted and received data.

4 Support for BITE: Three Pulse Outputs and four inputs are provided to support such applications as C-Mode or System Synchronisation. These pulse signal inputs are: External Clock Timer External Clock Reset Pulse Minor Frame Sync. (MIFS) Major Frame Sync. (MAFS) C-Mode Pulse (CMDP) These signal inputs are provided with all necessary support logic to ensure correct system functionality. System Interface: The PMC interface is compatible with 32bit PCI Local bus Specification, revision 2.1, June ARINC-629 Power Stub Connector External Clock/Sync A-629 Module SIM 32 MHz XPP DATAC ARINC-629 Transceiver RPP RAM 2x16k words Write Buff Read Buff Interrupt Status FIFO Registers Channel Interface Space 0 Register Interface Space 1 16 Cyclic Buffers Space 0 Register Interface Space 1 PLX PCI Interface PCIbus Figure 2.1 Functional Block Diagram for the Sy629PMC-BPM Module

5 Mechanical Description: The single width PMC module mechanical design conforms to Common Mezzanine Card Standard P1386 [1]. Connection to the ARINC-629 stub cable is via a 4-pin LEMO connector on the front panel. +/- 15v Power input for Coupler Power to Stub Cable is via a 3-pin LEMO connector on the front panel. Arinc 629 Pseudo Bus connection is via a 2-pin LEMO connector on the front panel. Additional inputs and outputs on the PMC backplane I/O are: Three Pulse outputs and 4 inputs Minor Frame Sync. (MIFS) Major Frame Sync (MAFS) C-Mode Pulse (CMDP) External Clock and Sync inputs Specification: Power Requirements (maximum) + 5v at 2.5 A + 3.3v at 1.0A +15v at 400mA (external supply) - 15v at 400mA (external supply) PCI Interface Interface compatible with 32bit PCI Local bus Specification, revision 2.1, June 1995 Input/Output Connector Type ARINC-629 Stub 4way LEMO socket +/- 15v Input Supply 3way LEMO socket ARINC-629 Pseudo Bus 2way LEMO socket Operating Temperature 0 C to + 70 C Storage Temperature -25 C to + 85 C Relative Humidity 0 to 95% non-condensing

6 Ordering Information and Variants: Sy629PMC-BPM ARINC 629 to PMC Interface Transmit and Bus Monitoring under BP protocol Future developments: Sy625PMC-CPM Sy629PMC-BPT Sy629PMC-BPE ARINC 629 to PMC Interface Transmit and Bus Monitoring under CP protocol ARINC 629 to PMC Interface Multi-Terminal Emulator ARINC 629 to PMC Interface Tx and Rx plus Error insertion Contact Details: Sycos AES Hambledon Manor Iwerne Minster Blandford Forum Dorset. UK. DT11 8QS Tel: Fax: web: