Integrated Device Technology

Transcription

1 Integrated Device Technology DDR2-800 Register Validation Board User Manual Document Name: Prepared by: DDR2-800 Register Validation Board User Manual Chris Macaraeg Revision: 0.03 Date: July 18, /18/ of 54

2 1 Introduction The DDR2-800 Register Validation Board (or RVB800) is a standalone test fixture that was designed to provide testing and validation for a DDR2 register in an environment that simulates actual usage. It is very similar in appearance and usage to the previous designs (RVB553 and RVB667), but makes a major leap in performance to 800MHz. The RVB800 requires no additional equipment except a PC-ATX power supply and a high-speed oscilloscope. If desired, two lab power supplies (+3.3V and +5.0V) can be used instead of the PC-ATX supply. The devices to be tested must be mounted on a DIMM or other DIMM socket compatible test board. The board will accept functional DIMMs, or DIMMs that have been modified especially for designated tests. While it is not the goal of the test fixture to test unbuffered DIMMs, these devices can also be plugged into the test socket. It is also not the goal to test PLL operation on the board, but all clocks are provided to the DIMM, along with the ability to enable spread spectrum if the user wishes to examine this area. 7/18/ of 54

3 2 System Features The RVB800 was designed to drive a DDR2 DIMM in a standard DDR2 DIMM socket. The intended purposes of the board are testing of the DDR2 registers on the DIMM, and limited testing of the DDR2 SDRAM devices on the DIMM. The test capabilities include the following: 1. Provision for virtually any address, control, and data pattern. Up to 256 patterns can be implemented, with 512 vectors per pattern. 2. CKE, ODT, and CS operation relative to clock. These signals can be skewed independently of the clock and address in 10ps increments to allow testing of setup/hold time. 3. Setup and hold time testing of the DIMM register. The address sent to the DIMM can be skewed relative to the clock in 10ps increments, allowing the user to determine the exact point of DIMM failure due to setup/hold time violations. 4. Limited testing of the DIMM data bus. The DIMM data bus driven by the RVB800 can be skewed clock in 10ps increments. DIMM data bus testing limitations are discussed in Section Reset recovery. A test vector controls the reset input to the DIMM; it can be toggled in the midst of a pattern to determine the time required to complete a reset. 6. Corner voltage testing on the DIMM VDD voltage pins. VDD on the DIMM can be set to any point between 1.7V and 2.0V. 7. Corner voltage testing on the DIMM VREF pin. VREF on the DIMM can be set to any point between 750mV and 1.10V, depending upon the DIMM VDD voltage. 8. Provision for driving the board clocks with an external signal source. The external signal source will be automatically selected if its frequency is greater than the on-board crystal s frequency (24.000MHz). 9. Capability to enable or disable Spread Spectrum Clocking (SSC) modulation by reprogramming the IDT5V9885. SSC is enabled by default. 10. Up to 400MHz operation. 11. Simultaneous switching delay testing. 7/18/ of 54

4 12. Noise and signal integrity testing. 13. USB circuitry for board configuration and downloading test vectors (not currently supported). 7/18/ of 54

5 3 Configurable Functions Before testing begins, the user must configure the board properly. All of the functions on the board that can be configured, and the default settings that the board is shipped with, are listed in Table 1 and Table 2. 7/18/ of 54

6 Function Spread Spectrum Clocking Enable Clock Source Select PCB Label N/A (configured through 5V9885) N/A (auto-selection based upon external clock frequency) Adjustment 800MHz Operation Location 1 Values2 (Default Setting) 2 667MHz Operation 2 N/A N/A enabled enabled N/A IDT5T93 SEL pin None W1 5V9885 Frequency Select 3 5V9885 SHUTDOWN/OE pin IDT5T2110 REFSEL pin GIN5_CK_SEL GIN4_TRST# GIN3_SUSP GIN2_TMS None None W8 W7 W6 W5 W9 W10 DIMM Address Delay 4 ADDR_DLY[10:0] S12- [2:0], S11- [7:0] DIMM Control Delay 4 CTL_DLY[10:0] S8- [2:0], S7- [7:0] DIMM Data Delay 4 DATA_DLY[10:0] S6- [2:0], S3- [7:0] DIMM Data Strobe Delay 4 DQS_DLY[10:0] S5- [2:0], S4- [7:0] DQS_OE* Delay CONFIG[7:2] S9-[7:2] One or Two Register Delay for Address, Control, Data Domains Select FLASH test vectors Control/Address FLASH/PROM Select Data FLASH/PROM Select CONFIG[1] CONFIG[0] None None S9-[1] S9-[0] W14 W12 W13 W11 N/A In = select A1/A1# Out = select A2/A2# Binary Decode of Frequency In = device shut down Out = device enabled In = select REF1 Out = select REF0 00b = min dly 1xxxxxxxxxb = max dly 00b = min dly 1xxxxxxxxxb = max dly 00b = min dly 1xxxxxxxxxb = max dly 00b = min dly 1xxxxxxxxxb = max dly b = min delay b = max delay 1b = 2 clock delay 0b = 1 clock delay 1b = not supported 0b = select FLASH vectors 1-2 = PROM 2-3 = FLASH 1-2 = PROM 2-3 = FLASH On-board crystal selected In Out Out On-board crystal selected In Out Out 000 b b 000 b b b b b b b 0b 0b W14 = 2-3 W12 = 2-3 W13 = 2-3 W11 = b 0b 0b W14 = 2-3 W12 = 2-3 W13 = 2-3 W11 = 2-3 Test Pattern Select PATTERN[7:0] S13- [7:0] See Table 7 b b DIMM VREF Adjustment DIMM VREF ADJUST R12 750mV to 1.10V (potentiometer) 950mV 950mV DIMM VDD Adjustment DIMM 1.8V ADJUST R6 1.7V to 2.0V (potentiometer) 1.9V 1.9V Table 1: User Configurable Function Default Values for 800MHz and 667MHz Operation NOTE: All default values in Table 1 are preliminary and subject to change. 1 If multiple switches are listed the first is the MSB, the last is the LSB. 2 1 = switch closed or ON, 0 = switch opened or OFF. 3 Switch settings not listed in the table are not supported. 4 Minimum delay is nominally 2.2ps; additional delay is approximately 10ps per step. Refer to On Semiconductor MC100EP195 data sheet. 7/18/ of 54

7 Function Spread Spectrum Clocking Enable Clock Source Select PCB Label N/A (configured through 5V9885) N/A (auto-selection based upon external clock frequency) Adjustment Location 5 Values6 533MHz Operation 5 400MHz Operation 5 N/A N/A enabled enabled N/A IDT5T93 SEL pin None W1 5V9885 Frequency Select 7 5V9885 SHUTDOWN/OE pin IDT5T2110 REFSEL pin GIN5_CK_SEL GIN4_TRST# GIN3_SUSP GIN2_TMS None None W8 W7 W6 W5 W9 W10 DIMM Address Delay 8 ADDR_DLY[10:0] S12- [2:0], S11- [7:0] DIMM Control Delay 8 CTL_DLY[10:0] S8- [2:0], S7- [7:0] DIMM Data Delay 8 DATA_DLY[10:0] S6- [2:0], S3- [7:0] DIMM Data Strobe Delay 8 DQS_DLY[10:0] S5- [2:0], S4- [7:0] DQS_OE* Delay CONFIG[7:2] S9-[7:2] One or Two Register Delay for Address, Control, Data Domains Select FLASH test vectors Control/Address FLASH/PROM Select Data FLASH/PROM Select CONFIG[1] CONFIG[0] None None S9-[1] S9-[0] W14 W12 W13 W11 N/A In = select A1/A1# Out = select A2/A2# Binary Decode of Frequency In = device shut down Out = device enabled In = select REF1 Out = select REF0 00b = min dly 1xxxxxxxxxb = max dly 00b = min dly 1xxxxxxxxxb = max dly 00b = min dly 1xxxxxxxxxb = max dly 00b = min dly 1xxxxxxxxxb = max dly b = min delay b = max delay 1b = 2 clock delay 0b = 1 clock delay 1b = not supported 0b = select FLASH vectors 1-2 = PROM 2-3 = FLASH 1-2 = PROM 2-3 = FLASH On-board crystal selected In Out Out On-board crystal selected In Out Out 000 b b 000 b b 000 b b b b b 0b 0b W14 = 2-3 W12 = 2-3 W13 = 2-3 W11 = b 1b 0b W14 = 2-3 W12 = 2-3 W13 = 2-3 W11 = 2-3 Test Pattern Select PATTERN[7:0] S13- [7:0] See Table 7 b b DIMM VREF Adjustment DIMM VREF ADJUST R12 750mV to 1.10V (potentiometer) 950mV 950mV DIMM VDD Adjustment DIMM 1.8V ADJUST R6 1.7V to 2.0V (potentiometer) 1.9V 1.9V Table 2: User Configurable Function Default Values for 533MHz and 400MHz Operation NOTE: All default values in Table 2 are preliminary and subject to change. 5 If multiple switches are listed the first is the MSB, the last is the LSB. 6 1 = switch closed or ON, 0 = switch opened or OFF. 7 Switch settings not listed in the table are not supported. 8 Minimum delay is nominally 2.2ps; additional delay is approximately 10ps per step. Refer to On Semiconductor MC100EP195 data sheet. 7/18/ of 54

8 3.1 Configurable Function Details This section contains a detailed discussion of the configurable functions Spread Spectrum Clocking The RVB800 contains an IDT5V9885 Programmable Clock Generator that is used to provide an on-board clock source to the circuitry. This device includes Spread Spectrum Clocking (SSC) with a 0.5% downspread for reduced EMI. The Clock Drivers used to distribute the clocks will pass on the 5V9885 s SSC modulation to the registers under test on the DIMM. Although the RVB800 is shipped with SSC modulation enabled, it is possible to disable SSC it by re-configuring the 5V9885 using IDT s software and hardware solution. Please visit IDT s website ( or contact IDT s Timing Solutions group at clockhelp@idt.com V9885 Frequency Select The IDT 5V9885 has the capability to provide multiple frequencies to the board. Currently, the 200MHz, 266MHz, 333MHz, and 400MHz frequencies to the DIMM are supported. The frequency is selectable through jumpers on the board (see Table 1 and Table 2) Selectable Clock Source There may be occasions where the user would like to drive the board s clocks with a frequency that is not supported by the 5V9885. In this case, a single-ended SMA connector (J12) is provided for the user to connect an external single-ended clock source. This board has the capability to select as a clock source either the on-board MHz crystal, or an external clock source. The crystal oscillator is the default source for the 5V9885. To use an external clock source, it must be connected to J12 through a 50-ohm cable, and its frequency must be greater than MHz in order for the 5V9885 to automatically switch over to it. 7/18/ of 54

9 If an external clock source is used, the user must keep in mind the frequency relationship of the source to the desired output clocks. The 5V9885 as shipped from the factory is configured to provide standard clock frequencies to the DIMM (200MHz, 266MHz, 333MHz, and 400MHz) based upon a MHz crystal input. If an external clock source is used, the relationship between the clock source and the DIMM clocks will remain the same (i.e. the same multiplier will be in effect). The 5V9885 does have operating limits which may be exceeded when an external clock source is used. The user should consult the 5V9885 data sheet for these operating limits, and may have to re-configure the 5V9885 to ensure its correct operation and prevent damage to the device DIMM Address, Control, Data, and Data Strobe Delay Test patterns drive the DIMM address, control, data, and data strobe output enable lines from separate clock domains. These test patterns are stored in FLASH memory devices. Table 5 and Table 6 illustrate the bit assignments for these vectors within the FLASH memories. The control and address lines are listed in the same table since the test vectors that determine the values driven on these lines reside in the same FLASH memory storage device. Similarly, the data and data strobe output enable lines are listed in the same table since these vectors are stored in the same FLASH memory device. The Address, Control, and Data lines can be independently delayed in time by 2.2ns to 12.2ns relative to the DIMM clocks; the adjustability of the data strobe lines is more complicated, and is discussed in Section The ability to skew the Address and Control clocks independently allows the user to test setup and hold times of the DIMM register relative to the DIMM clock A Note on DIMM Testing Although the Data lines (and Data Strobe lines) can also be skewed independently of the other clock domains and are controlled by independent test vectors, their use in testing DIMMs and checking data setup and hold times on the DIMM cannot be guaranteed. This is due to the architecture of the RVB800. Each DIMM operation (i.e. initialization, burst write, burst read, etc.) is executed in a separate test vector. Switching from one test vector to another (for example when following burst writes with burst reads) will introduce delays and timing effects that may preclude correct DIMM operation. Therefore, the RVB800 should not be considered a DIMM Tester, even with Data and Data Strobe control, and even with the inclusion of 7/18/ of 54

10 SDRAM configuration, write, and read test vectors. Instead, the user should consider the RVB800 and the included test vectors as tools to assist in validating the DIMM register. The ability to skew the Data and Data Strobe, in addition to being able to control the transitions on the Data signals, will greatly assist in checking DIMM characteristics such as cross-talk, loading effects, etc Data Strobe Adjustability As stated above, the adjustability of the Data Strobe lines is more complex than the other signals. The complexity comes with generating a usable Data Strobe for DIMM Write commands. To create the DQS/DQSN signals and allow them to be skewed and output enabled with appropriate timing, adjustability is required for both the FPGA input clock that drives the DQS/DQSN clock domain and also for the DQS_OE* vector (see Table 6) that drives the DQS/DQSN signals. The adjustable clock input s purpose is the same as for the other clock domains to enable the user to adjust the DQS/DQSN signals so they have a desired timing relationship to the other signals that drive the DIMM. Since the DQS_OE* is driven by a different clock domain than the DQS/DQSN signals (DQS_OE* is driven by a half-frequency clock), the timing relationship between DQS_OE* and the DQS/DQSN drivers is not optimal at all frequencies and needs adjustment. Therefore, the DQS_OE* adjustment is for obtaining the optimal timing relationship between the two clock domains (i.e. ensuring that DQS_OE*) setup and hold times are met). During DIMM writes, the DQS/DQSN signals are driven for 2-1/2 DIMM clock cycles. If the DQS_OE* is not adjusted correctly, the user will see that DQS/DQSN is driven for only 1-1/2 clock cycles FLASH or PROM select The RVB800 is designed to accept either 4Mbit FLASH or PROM as the nonvolatile storage device for the test patterns. However, two pins are defined differently between the FLASH and PROM. Jumpers (W11-W14) are provided to select the correct pin configuration. This function will be set at the factory and is dependent upon which device the board is populated with. This function never needs to be changed by the user, unless the user replaces the FLASH devices shipped with the board with his own PROM device. In this document, the terms PROM and FLASH are used interchangeably. 7/18/ of 54

11 3.1.6 Test Pattern Select Up to 256 test patterns can be supported by the RVB800. The test pattern is selected by configuring the proper switches. See Section 10 for more details DIMM VREF Adjustment This board has the capability to adjust the VREF input to the DIMM. This will not affect the VREF inputs on any device on the RVB800; it only affects the VREF pin on the DIMM. To adjust VREF to the DIMM, the board must be powered on, the potentiometer at location R12 adjusted, and the voltage checked with a DVM. A probe point, E11, is provided to assist in checking the voltage DIMM VDD Adjustment This board has the capability to adjust the VDD power supply input to the DIMM. This will not affect the power inputs to any device on the RVB800; it only affects the VDD pins on the DIMM. To adjust VDD to the DIMM, the board must be powered on, the potentiometer at location R6 adjusted, and the voltage checked with a DVM. Probe/access points (E2 for the DIMM 1.8V supply and E1 for ground) are provided to assist in checking this voltage. 7/18/ of 54

12 4 Required Equipment The equipment required to operate the RVB800 consists of a power source (such as a PC-ATX power supply), and a high-speed oscilloscope. The 3.3V and 5.0V rails on a PC-ATX power supply are used. If an appropriate PC-ATX power supply is not available, then two lab supplies are required 3.3V and 5.0V. Access points are available to allow easy attachment of lab supplies. E10 can be used to attach a 3.3V source, E9 for the 5.0V source, and E5 and E6 for ground. The power requirements on the board are minimal. The lowestpowered PC-ATX supply available today provides approximately 230W, and this should be sufficient. There are many PC-ATX power supplies available on the market today. A large number of these (particularly older/inexpensive supplies) are sensitive to the loading of the board they are connected to; i.e., if the board does not draw enough current, the power supply will not turn on properly. The result is that the board will not operate correctly. If the board does not operate correctly, check the 3.3V and 5.0V voltages at E10 and E9, respectively. If the measured potential is not approximately as expected, another PC-ATX power supply, or a lab supply, should be used. The usual symptom of an incompatible power supply is that the 3.3V and 5.0V potentials will be very low. 7/18/ of 54

13 The recommended oscilloscope and probe requirements are listed in Table 3, but this depends upon the requirements of the user and will vary. Recommended Oscilloscope Characteristics Sampling Rate (Real Time) Minimum of 4G samples/second RMS Jitter < 6ps +/ % of delay setting Recommended Probe Characteristics Rise Time <140ps Bandwidth (3dB) > 2.5GHz Input Resistance 100kOhm Input Capacitance 0.6pF Table 3: Recommended Oscilloscope and Probe Characteristics 7/18/ of 54

14 5 Probe Points Spread throughout the board are probe points that will assist in understanding the board s operation. These probe points are designated with either the E or T prefix on the board and are listed in Table 4. They allow probing of things such as the different power supplies, PLL clock outputs, and device I/O. In most cases, the probe points are connected to signals that are not used by the RVB800 s logic. However, there are some probe points that are connected to utilized signals. Note that the placement of the probe points on utilized signals may not give an accurate indication of the timing seen by a particular device; in general, the logic probe points are placed as close to the logic device as possible; the clock probe points are placed as close to the driving device as possible; the power probe points are placed as close to the voltage regulator as possible. Probe Point Location Name Description TP13 TIMING_REF0 Timing reference 0 TP14 TIMING_REF1 Timing reference 1 TP15 TIMING_REF2 Timing reference 2 E1 GROUND Ground E2 V_DIMM_1_8V DIMM VDDQ E3 +2.5V +2.5V power supply E4 +1.8V +1.8V power supply E5 GROUND Ground E6 GROUND Ground E7 V_900MV SSTL reference voltage for RVB800 logic E8 V_2_16V +2.16V power supply E9 +5V +5V power supply E V +3.3V power supply E11 DIMM_VREF DIMM SSTL reference voltage E12 PLL5_OUT1* FPGA PLL5_OUT1* pin E13 PLL5_OUT1 FPGA PLL5_OUT1 pin E14 PLL5_FB FPGA PLL5_FB pin E15 PLL5_OUT0 FPGA PLL5_OUT0 pin E16 CLK13 FPGA CLK13 pin 7/18/ of 54

15 E17 CLK12 FPGA CLK12 pin E18 CLK15 FPGA CLK15 pin E19 PLL11_OUT0 FPGA PLL11_OUT0 pin E20 PLL11_OUT1 FPGA PLL11_OUT1 pin E21 PLL5_FB* FPGA PLL5_FB* pin E22 PLL5_OUT0* FPGA PLL5_OUT0* pin E23 CLK13* FPGA CLK13* pin E24 CLK12* FPGA CLK12* pin E25 CLK15* FPGA CLK15* pin E26 PLL11_OUT0* FPGA PLL11_OUT0* pin E27 PLL11_OUT1* FPGA PLL11_OUT1* pin E28 PLL11_FB FPGA PLL11_FB pin E29 PLL11_FB* FPGA PLL11_FB* pin E30 FPLL10CLK FPGA FPLL10CLK pin E31 FPLL10CLK* FPGA FPLL10CLK* pin E32 FPLL7CLK* FPGA FPLL7CLK* pin E33 E34 E35 TEST_DIMM_CLK* CLK_Q2_LVDS CLK_Q2_LVDS* Test clock, intended to replicate the loading of the DIMM clocks. Differential pair with TEST_DIMM_CLK. Test clock, unterminated, identical to the clock that drives the IDTCSPUA877. Differential pair with CLK_Q2_LVDS*. Test clock, unterminated, identical to the clock that drives the IDTCSPUA877. Differential pair with CLK_Q2_LVDS. E36 CLK11 FPGA CLK11 pin E37 CLK11* FPGA CLK11* pin E38 CLK0* FPGA CLK0* pin E39 CLK0 FPGA CLK0 pin E40 TEST_DIMM_CLK Test clock, intended to replicate the loading of the DIMM clocks. Differential pair with TEST_DIMM_CLK*. E41 CLK8 FPGA CLK8 pin E42 CLK8* FPGA CLK8* pin E43 CLK10 FPGA CLK10 pin E44 CLK10* FPGA CLK10* pin E45 CLK1* FPGA CLK1* pin 7/18/ of 54

16 E46 CLK9 FPGA CLK9 pin E47 CLK9* FPGA CLK9* pin E48 CLK2* FPGA CLK2* pin E49 CLK2 FPGA CLK2 pin E50 CLK3* FPGA CLK3* pin E51 CLK3 FPGA CLK3 pin E52 FPLL9CLK FPGA FPLL9CLK pin E53 FPLL9CLK* FPGA FPLL9CLK* pin E54 FPLL8CLK* FPGA FPLL8CLK* pin E55 FPLL8CLK FPGA FPLL8CLK pin E56 CLK_9885_OUT6 IDT5V9885 OUT6 pin. This clock tracks the DIMM clock frequency. E57 PLL6_OUT1 FPGA PLL6_OUT1 pin E58 PLL6_FB* FPGA PLL6_FB* pin E59 CLK_9885_OUT1 IDT5V9885 OUT1 pin. This clock tracks the source clock frequency. E60 PLL6_FB FPGA PLL6_FB pin E61 PLL6_OUT0* FPGA PLL6_OUT0* pin E62 PLL12_OUT1* FPGA PLL12_OUT1* pin E63 PLL12_FB* FPGA PLL12_FB* pin E64 PLL6_OUT1* FPGA PLL6_OUT1* pin E65 PLL6_OUT0 FPGA PLL6_OUT0 pin E66 PLL12_OUT1 FPGA PLL12_OUT1 pin E67 PLL12_FB FPGA PLL12_FB pin E68 GOUT1_LOSSCLKIN IDT5V9885 GOUT1/LOSS_CLKIN pin E69 GOUT0_TDO_LOSSLO CK IDT5V9885 GOUT0/TDO/LOSS_LOCK pin E70 REF1_5T2110* 5T2110 REF1* input pin. Leave unconnected. E71 REF0_5T2110* 5T2110 REF0* input pin. Leave unconnected. E72 TEST_HCLK_M167M* 5T2110 output test clock. The frequency of this clock should be one-half the DIMM clock frequency. Table 4: Probe Points 7/18/ of 54

17 6 Board Setup To set up the board, the following steps must be executed: 1. Install the DIMM in the test socket at J2. 2. Connect the power supply by either inserting the PC-ATX power supply connector into J1 on the board, or attaching two lab power supplies through the large vias at E10 (+3.3V), E9 (+5.0V), and E5 and E6 (ground). The DIMM must be installed or removed from its test socket only when the power is off. 3. Turn the power to the RVB800 on. If a PC-ATX power supply is used, this is done by flipping the switch at S2 to the on position (which is towards pin 1). If a lab supply is used, the power switch on the power supply itself must be used. The LED at DS1 indicates the +3.3V supply is on; the LED at DS2 indicates that the +5.0V supply is on. After these steps are completed, the RVB800 can be initialized (Chapter 7) or configured (Chapter 8). 7/18/ of 54

18 7 Board Initialization The type of DIMM installed in the RVB800 will determine whether or not any board initialization is required. Board initialization takes place after the board is set up and powered on (see Section 5). 7.1 Initialization of a Test DIMM with No SDRAM Devices If the installed DIMM is a test DIMM that does not contain SDRAM devices, then any test pattern can be selected using the Test Pattern Select switches (see Table 1 and Table 7) and run by depressing the Master Reset switch (S1). When the Master Reset switch is depressed, the LED at DS3 will light. 7.2 Initialization of a DIMM with Installed SDRAM Devices If the installed DIMM contains SDRAM devices, then the Initialization Pattern must be run prior to executing any of the SDRAM write patterns. To do this, select the Initialization Pattern using the Test Pattern Select switches and run it by depressing the Master Reset switch. This will initialize the SDRAMs on the DIMM (if installed) and place the DIMM in a state where it is ready to be used. If the power to the board is cycled, the Initialization Pattern must be reexecuted. If the Synchronization Pattern is executed (see Section 8.2), the SDRAMs will be placed in an unknown state. Therefore, the Initialization Pattern must be executed again to place the board in a known state where it is ready to be used. See Section for information regarding DIMM testing. 7/18/ of 54

19 8 Configuring the Validation Board for Testing Before testing can begin, the delay lines and variable voltages on the board must be set up. 8.1 Setting the Variable Voltages On the RVB800, the DIMM VDD and DIMM VREF voltages are adjustable. The user will determine the appropriate level to set these voltages to. The ranges for these voltages are listed in Table 1and Table 2. The DIMM VREF voltage can be probed at test point E11; the DIMM VDD voltage can be probed at E Configuring the Delay Lines There are 5 delay lines on the RVB800 four are implemented using MC100EP195 delay lines (address, control, data, and data strobe), while one is implemented internally within the FPGA DIMM Delay Lines The Address, Control, Data, and Data Strobe delay lines determine the timing relationship of the respective signals driven to the DIMM relative to each other and relative to the DIMM clocks. These delay lines are called DIMM Address Delay, DIMM Control Delay, DIMM Data Delay, and DIMM Data Strobe Delay (see Table 1 and Table 2). These delay lines are configured at the factory such that the Address, Control, Data, and Data Strobe presented to the DDR2 registers and SDRAMs on the DIMM meet the specified setup and hold times (see the appropriate data sheet for the timing specifications). The actual timing may vary slightly from board to board due to production tolerances and may require user adjustment. If the user wants to change the timing of the Address, Control, Data, or Data Strobe domains, then these delay lines need to be re-configured. A test pattern has been implemented to assist in configuring the delay lines. This is the Synchronization Pattern (see Table 7). This pattern will pulse the address and data bits simultaneously every 32 clock cycles. This will assist in not only aligning the address and data register outputs with the clock, but also aligning these registers with each other. 7/18/ of 54

20 Note that the Synchronization Pattern does not toggle the control bus since this would affect the operation of the register on the DIMM. In most cases, the DIMM Control Delay Line should be set to the same value as the DIMM Address Delay Line. To configure the Data Strobe delay line, one of the SDRAM write tests must be run (for example 0x86 in Table 7) so that the timing of DQS/DQSN can be compared with a reference (normally the DIMM clocks) Configuring the DIMM Delay Lines This section discusses the configuration of the DIMM Delay Lines and uses the DIMM Address Delay Line as an example. To configure the DIMM Address Delay Line so that the address signals meet the DDR2 register s setup and hold times, the user must simultaneously probe the clock pin and one of the address pins on the DDR2 register which resides on the DIMM under test. If the timing is not as desired, then the DIMM Address Delay must be changed to suit by modifying the appropriate switches (see Table 1). After the timing has been adjusted and verified, the remaining address bits can be checked. After this process is completed for the Address Register, the same process can be executed to set up the DIMM Data Register Delay Line. 7/18/ of 54

21 Once the DIMM Address, Control, and Data Delay Lines are set up, it is recommended that the switch settings be recorded so they can be used as a baseline setting for future tests. The recommended steps for configuring the registers are summarized below. Note that the steps with the (optional) notation denote steps which can be skipped if SDRAM data or data strobe tests will not be run. 1. Install the DIMM and power supply as described in Section 5. Turn the power on. 2. Set the appropriate switches to select the Synchronization Pattern (see Table 1 and Table 7). When configuring the delay lines after power up, it is not necessary to run the Initialization Pattern. 3. Depress the Master Reset Switch button to load and run the Synchronization Pattern. The LED at DS3 should turn on while the Master Reset Switch button is depressed. 4. Set up the oscilloscope to probe an appropriate address bit and clock on the DIMM. If the timing is not correct, adjust S12 and/or S10 (see Table 1) until the desired timing is attained. 5. (Optional) Set up the oscilloscope to probe an appropriate data bit and clock on the DIMM. If the timing is not correct, adjust S6 and/or S3 (see Table 1) until the desired timing is attained. 6. (Optional) Set up the oscilloscope to probe an appropriate data strobe bit and clock on the DIMM. If the timing is not correct, adjust S5 and/or S4 (see Table 1) until the desired timing is attained. 7. Normally, the control and address bits would be aligned, but this is entirely up to the user. In the situation where the control and address bits are aligned, adjust S8 and S7 to match S12 and S10 (see Table 1). If the control and address bits do not have to be aligned, adjust S8 and S7 until the desired timing is attained. 8. (Optional) Set the appropriate switches to select the All Bits Toggling (SDRAM Write) Pattern (see Table 1 and Table 7). Set up the oscilloscope to probe an appropriate data strobe bit and clock on the DIMM. If the data strobe signal is not output enabled for exactly 2-1/2 clock cycles, adjust S9[7:2] until the data strobe is driven for exactly 2-1/2 clocks consistently. 7/18/ of 54

22 9. (Optional) Rerun the Initialization Pattern to place the SDRAMs in a known state, if required (see Section 7). The board is now ready to be used. 7/18/ of 54

23 9 Theory of Operation Note that all signal names used in this document refer to the board schematics. For reference, the RVB800 Block Diagram is shown in Figure 1. A Master Reset pulse will initiate the driving of test patterns onto the DDR2 DIMM. A Master Reset pulse can be created in two ways: either by powering on the board, or by depressing the START BUTTON at location S1. When a Master Reset pulse occurs, the FPGA on the RVB800 will pass the configuration on the 8-position DIP-switch at S11 (Test Pattern Select) onto the upper 8 bits of the address bus of both FLASH memories to select a stored pattern. The value of the 8-position DIPswitch is meant to be static while a test is being conducted. If the configuration of the DIP-switch at S11 is modified, the Start Button must be depressed again to load the new pattern and begin a new test. A Pattern Word will then be read out of the FLASH devices. A Pattern Word is defined as all the test bits that will be output to the DIMM s I/O pins during a given clock cycle in other words, a single test vector. Each test pattern consists of 512 Pattern Words. Each Pattern Word is 64-bits wide - 32 bits for address and control and 32 bits for data (Table 5 illustrates the Pattern Word for Address and Control while Table 6 illustrates the Pattern Word for Data and Data Strobe). Since the two FLASH devices are only 8-bits wide, the Pattern Word will be read out of the devices 8 bits at a time. For a mapping of the Pattern Word contents to the DDR2 DIMM I/O pins, refer to Section 9.1 When an entire 64-bit Pattern Word has been read out of the FLASH devices and buffered in the FPGA, it will be written into the dual-port RAMs (DPRAMs) within the FPGA on the RVB800, and the next Pattern word will be read from the FLASH. This process will continue until the 512 Pattern Words have been stored in the DPRAMs. After the entire test pattern has been written into the DPRAMs, a state machine will then place the DPRAMs in the test mode, where they are continuously read (i.e., the 512-word test pattern is repeated continuously). For information on the test patterns, refer to Section 10. The test will be continuously run (driving the same pattern onto the DIMM pins continuously) until the START BUTTON is depressed again. 7/18/ of 54

24 Figure 1: RVB800 Block Diagram 7/18/ of 54

25 9.1 Mapping of Test Vectors to DIMM Input Pins Table 5 and Table 6 illustrate the mapping of the test vectors, which are stored in FLASH memory, to the DIMM pins. Stored within the Address and Control FLASH memory are the test vectors that will drive the control and address signals to the DIMM. As shown in Table 5, the address and control vectors are 32-bits wide (defined as ADDRESS[31:0]). The upper 8 bits will drive DIMM register control signals as part of the Control Clock Domain; the remaining lower 24 bits will drive address and certain SDRAM control signals as part of the Address Clock Domain. Stored within the Data FLASH memory are the test vectors that drive the data and data strobe output enable signals to the DIMM. As shown in Table 6, the data vectors are also 32-bits wide (defined as DATA[31:0]). All bits except DATA[21] are part of the Data Clock Domain and determine the signaling for various signals that are part of the data domain. DATA[21] is mapped to DQS_OE*, which is the output enable control for the DQS/DQSN signals and is required to be part of the Data Strobe Domain. DATA[31] is mapped to DQ_OE*, which is the output enable control for the DQ bus. DATA[30:28] are mapped to TIMING_REF[2:0] which are used as timing references. 7/18/ of 54

26 CLOCK DOMAIN CONTROL ADDRESS Test Vector Bit DDR2 DIMM Pin ADDRESS[31] Not Used ADDRESS[30] RESET# ADDRESS[29] S1# ADDRESS[28] CKE1 ADDRESS[27] ODT1 ADDRESS[26] S0# ADDRESS[25] CKE0 ADDRESS[24] ODT0 ADDRESS[23] Not Used ADDRESS[22] PARIN ADDRESS[21] A15 ADDRESS[20] A14 ADDRESS[19] A13 ADDRESS[18] A12 ADDRESS[17] A11 ADDRESS[16] A10 ADDRESS[15] A9 ADDRESS[14] A8 ADDRESS[13] A7 ADDRESS[12] A6 ADDRESS[11] A5 ADDRESS[10] A4 ADDRESS[9] ADDRESS[8] ADDRESS[7] ADDRESS[6] ADDRESS[5] ADDRESS[4] ADDRESS[3] ADDRESS[2] ADDRESS[1] ADDRESS[0] A3 A2 A1 A0 BA2 BA1 BA0 WE# RAS# CAS# Table 5: Address and Control Vector Mapping 7/18/ of 54

27 CLOCK DOMAIN DATA Test Vector Bit DATA[31] DATA[30] DATA[29] DATA[28] DATA[27] DATA[26] DATA[25] DATA[24] DATA[23] DATA[22] DDR2 DIMM Pin DQ_OE* TIMING_REF2 TIMING_REF1 TIMING_REF0 Not used Not used Not used Not used Not used Not used DQS DATA[21] DQS_OE* DATA[20] Not used DATA DATA[19] DATA[18] DATA[17] DATA[16] DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DIMM_CB[3,7] DIMM_CB[2,6] DIMM_CB[1,5] DIMM_CB[0,4] DIMM_DQ[15,31,47,63] DIMM_DQ[14,30,46,62] DIMM_DQ[13,29,45,61] DIMM_DQ[12,28,44,60] DIMM_DQ[11,27,43,59] DIMM_DQ[10,26,42,58] DIMM_DQ[9,25,41,57] DIMM_DQ[8,24,40,56] DIMM_DQ[7,23,39,55] DIMM_DQ[6,22,38,54] DIMM_DQ[5,21,37,53] DIMM_DQ[4,20,36,52] DIMM_DQ[3,19,35,51] DIMM_DQ[2,18,34,50] DIMM_DQ[1,17,33,49] DATA[0] DIMM_DQ[0,16,32,48] Table 6: Data Vector Mapping 7/18/ of 54

28 10 Pattern Definitions As mentioned earlier, an 8-position DIP-switch selects the test pattern stored within the FLASH devices by driving the upper 8-bits of the FLASH address bus (through the FPGA). The outputs of the DIPswitch are called PATTERN [7:0] in the schematics. Each test pattern is 512 Pattern Words long, and is stored in 2048 contiguous locations (bytes) in each of the two FLASH memories. Therefore, during the vector loading period, the lower 11 bits of the two FLASH devices are driven by the FPGA to address these 2048 locations. The currently defined patterns are shown in Table 7. The test patterns can be divided into three groups, as discussed in the following sections NOP, Synchronization, and Initialization Patterns The first group of patterns is allocated the space from 0x00 through 0x3F and currently consists of a NOP pattern (in which essentially no activity occurs), the Synchronization Pattern that is discussed in Section 8.2.1, and the Initialization Pattern that is discussed in Section Initialization Pattern The purpose of the Initialization Pattern is to place the DDR2 SDRAMs into a known state before SDRAM testing begins. To initialize the SDRAMs, first the Initialization Pattern must be selected using the DIP-switches (see Table 7). Then, a Master Reset pulse must be generated as discussed in Section 9. When this is done, the initialization pattern will be driven onto the DIMM I/O pins. The Initialization pattern consists of the following steps to place the DRAMs into the idle state: 1. Drive all DIMM inputs low while Master Reset is low. This will be about 2ms. 2. A NOP command will be applied to the DIMM and CKE[1:0] will be driven high. 3. Wait 400ns. 4. Apply a PRECHARGE ALL command to the DIMM. 5. Apply a Load Mode command to EMR(2) Register. 6. Apply a Load Mode command to EMR(3) Register. 7. Apply a Load Mode command to EMR Register to enable the DLL. 8. Apply a Load Mode command to reset the DLL and program the operating 7/18/ of 54

29 parameters. 9. Apply a PRECHARGE ALL command. 10. Issue two REFRESH commands. 11. Apply a Load Mode command to initialize device operation. 12. Apply a Load Mode command to the EMR Register to enable OCD default. 13. Apply a Load Mode command to the EMR Register to enable OCD exit. After this sequence occurs, the SDRAMs will have been initialized and will be in the idle state. Please see Section for information on DIMM testing DIMM Register Patterns The second group of patterns is allocated the space from 0x40 through 0x7F and contains patterns that are targeted at the DIMM Register. These patterns may or may not treat the SDRAM control signals correctly with respect to timing. Therefore, if a DIMM with SDRAM devices is tested with these patterns, the SDRAM may be placed in an unknown state SDRAM Patterns The last group of patterns is allocated the space from 0x80 through 0xBF and contains patterns that are targeted at SDRAM devices on a DDR2 DIMM. SDRAM write and read patterns are implemented. However, the accuracy and correctness of these vectors, with respect to SDRAM timing, is not guaranteed and may require modification by the user Undefined Patterns The space from 0xC0 to 0xFF is not allocated to any Test Patterns. 7/18/ of 54

30 PATTERN [7:0] 0x00 0x01 0x02 0x03 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 Pattern Name Description Example No Activity or Zero Initialization Synchronization No Activity or Zero ISI Pattern (Register Only) Walking 1 (Register Only) Walking 0 (Register Only) All Bits Toggling (Register Only) All Bits Toggling, A15, D15, S1# Inverted (Register Only) A15, D15, S1# Switching, Remainder Ones (Register Only) A15, D15, S1# Switching, Remainder Zeroes (Register Only) VDD Bounce on A15, D15, S1# (Register Only) Places all zeros on the address bus all the time. SDRAMs are inactive. Goes through an initialization sequence to place the DDR DRAMs in the idle state. This is done once. All bits will pulse high every 8th clock cycle. This will assist in synchronization between the control and address registers. Places all zeros on the address bus all the time. SDRAMs are inactive. The Number of switching bits will increase with each clock cycle Walks a 1 through the address bus. Walks a 0 through the address bus. Every bit will continuously toggle simultaneously between 1 and 0 All bits will toggle simultaneously, but one bit will be inverted from the rest. One bit will be toggling; the rest will be 1 always. One bit will be toggling; the rest will be 0 always. The bit under test will remain at a logic 1 level; all other bits will toggle. N/A /18/ of 54

31 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 Ground Bounce on A15, D15, S1# (Register Only) VDD Bounce on A3, D3, S1# (Register Only) Ground Bounce on A3, D3, S1# (Register Only) VDD Bounce on A4, D4, S1# (Register Only) Ground Bounce on A4, D4, S1# (Register Only) Half Bits Toggling (Register Only) Half Bits Toggling (Register Only) CrossTalk on A4 (Register Only) CrossTalk on A0 (Register Only) CrossTalk on A11 (Register Only) CrossTalk on BA0 (Register Only) CrossTalk Reference (Register Only) The bit under test will remain at a logic 0 level; all other bits will toggle. The bit under test will remain at a logic 1 level; all other bits will toggle. The bit under test will remain at a logic 0 level; all other bits will toggle. The bit under test will remain at a logic 1 level; all other bits will toggle. The bit under test will remain at a logic 0 level; all other bits will toggle. Every other bit will continuously toggle simultaneously between 1 and 0 Every other bit will continuously toggle simultaneously between 1 and 0 A4 is the victim with 1 and 0, A7, A8, A12, A13 are aggressors PRBS (511 length). A0, A3, A14, A15 have PRBS# to limit SSO A0 is the victim with 1 and 0, A8, A13, A14, A15 are aggressors PRBS (511 length). A4, A9, A11, A12 have PRBS# to limit SSO A11 is the victim with 1 and 0, A9, A10, A14, A15 are aggressors PRBS (511 length). A0, A6, A8, A13 have PRBS# to limit SSO BA0 is the victim with 1 and 0, A1, A2, ODT1, CAS are aggressors PRBS (511 length). A5, A6, BA1, BA2 have PRBS# to limit SSO 1 and 0 pattern on A0, A4, A11 and BA /18/ of 54

32 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 All Bits Toggling, except A8 and A13 (Register Only) All Bits Toggling, A15 and S1# inverted (Register Only) Xtalk_ISI_SSO_A4 Xtalk_ISI_SSO_A0 Xtalk_ISI_SSO_CS0 Xtalk_ISI_SSO_ODT0 Xtalk_ISI_SSO_A4_PRBS1 Xtalk_ISI_SSO_A4_PRBS2 Xtalk_ISI_SSO_A4_PRBS3 Xtalk_ISI_SSO_A0_PRBS1 Xtalk_ISI_SSO_A0_PRBS2 Xtalk_ISI_SSO_A0_PRBS3 Xtalk_ISI_SSO_CS0_PRBS1 All bits will toggle simultaneously, except A8 and A13 All bits will toggle simultaneously, but A15 and S1# will be inverted from the rest. A8 and A13 will remain 0. Victim net A4 with PRBS PRBS# 255. RESET high. CS0 low, CS1 low. A3 net 128 high by 128 low for power rail bounce. Allows power and ground bounce measurement on test DIMM. All other bits PRBS PRBS 255. Victim net A0 with PRBS PRBS# 255. RESET high. CS0 low, CS1 low. A3 net 128 high by 128 low for power rail bounce. Allows power and ground bounce measurement on test DIMM. All other bits PRBS 255+ PRBS 255. Victim net CS0 with PRBS PRBS# 255. RESET high. CS1 low. A3 net 128 high by 128 low for power rail bounce. Allows power and ground bounce measurement on test DIMM. All other bits PRBS PRBS 255. Victim net ODT0 with PRBS PRBS# 255. RESET high. CS0 low, CS1 low. A3 net 128 high by 128 low for power rail bounce. Allows power and ground bounce measurement on test DIMM. All other bits PRBS PRBS 255. Victim net A4 with PRBS PRBS1# 255. RESET high. CKE0, CKE1, CS0, CS1 low. All other bits PRBS PRBS Victim net A4 with PRBS PRBS2# 255. RESET high. CKE0, CKE1, CS0, CS1 low. All other bits PRBS PRBS Victim net A4 with PRBS PRBS3# 255. RESET high. CKE0, CKE1, CS0, CS1 low. All other bits PRBS PRBS Victim net A0 with PRBS PRBS1# 255. RESET high. CKE0, CKE1, CS0, CS1 low. All other bits PRBS PRBS Victim net A0 with PRBS PRBS2# 255. RESET high. CKE0, CKE1, CS0, CS1 low. All other bits PRBS PRBS Victim net A0 with PRBS PRBS3# 255. RESET high. CKE0, CKE1, CS0, CS1 low. All other bits PRBS PRBS Victim net CS0 with PRBS PRBS1# 255. RESET high. CKE0, CKE1, CS1 low. All other 7/18/ of 54

33 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 Xtalk_ISI_SSO_CS0_PRBS2 Xtalk_ISI_SSO_CS0_PRBS3 Xtalk_ISI_SSO_ODT0_PRBS1 Xtalk_ISI_SSO_ODT0_PRBS2 Xtalk_ISI_SSO_ODT0_PRBS3 PARIN test (Register Only) No Activity or Zero ISI Pattern (SDRAM Read) Walking 1 (SDRAM Read) Walking 1 (SDRAM Write) Walking 0 (SDRAM Read) Walking 0 (SDRAM Write) All Bits Toggling (SDRAM Read) bits PRBS PRBS Victim net CS0 with PRBS PRBS2# 255. RESET high. CKE0, CKE1, CS1 low. All other bits PRBS PRBS Victim net CS0 with PRBS PRBS3# 255. RESET high. CKE0, CKE1, CS1 low. All other bits PRBS PRBS Victim net ODT0 with PRBS PRBS1# 255. RESET high. CKE0, CKE1, CS1 low. All other bits PRBS PRBS Victim net ODT0 with PRBS PRBS2# 255. RESET high. CKE0, CKE1, CS1 low. All other bits PRBS PRBS Victim net ODT0 with PRBS PRBS3# 255. RESET high. CKE0, CKE1, CS1 low. All other bits PRBS PRBS PARIN bit will toggle every 16 cycles; all other bits 0 (similar to 0x00). Places all zeros on the address bus all the time. SDRAMs are inactive. The Number of switching bits will increase with each clock cycle Walks a 1 through the address bus. Walks a 1 through the address bus. Walks a 0 through the address bus. Walks a 0 through the address bus. Every bit will continuously toggle simultaneously between 1 and /18/ of 54

34 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0xBF 0xC0 0xFF All Bits Toggling (SDRAM Write) All Bits Toggling, A5 Inverted (SDRAM Read) All Bits Toggling, A5 Inverted (SDRAM Write) A15 Switching, Remainder Ones (SDRAM Read) A15 Switching, Remainder Ones (SDRAM Write) A15 Switching, Remainder Zeroes (SDRAM Read) A15 Switching, Remainder Zeroes (SDRAM Write) VDD Bounce on A15 (SDRAM Read) VDD Bounce on A15 (SDRAM Write) Ground Bounce on A15 (SDRAM Read) Ground Bounce on A15 (SDRAM Write) No Activity or Zero Every bit will continuously toggle simultaneously between 1 and 0 All bits will toggle simultaneously, but one bit will be inverted from the rest. All bits will toggle simultaneously, but one bit will be inverted from the rest. One bit will be toggling; the rest will be 1 always. One bit will be toggling; the rest will be 1 always. One bit will be toggling; the rest will be 0 always. One bit will be toggling; the rest will be 0 always. The bit under test will remain at a logic 1 level; all other bits will toggle. The bit under test will remain at a logic 1 level; all other bits will toggle. The bit under test will remain at a logic 0 level; all other bits will toggle. The bit under test will remain at a logic 0 level; all other bits will toggle. Places all zeros on the address bus all the time. SDRAMs are inactive Undefined N/A N/A 7/18/ of 54

35 Notes: Table 7: Test Pattern Definitions 1. All patterns, except for Initialization, will be repeated until the Master Reset button is depressed to reload a new pattern and begin a new test. 2. In the Example column, an 8-bit bus is shown. On the RVB800, the patterns will usually be extended across all 16 address and 3 bank address bits (A[15:0] and BA[2:0]), and the entire data bus (DQ[63:0]). 7/18/ of 54

36 11 Running a Test After setting up the board (Section 5), initializing it (Section 7), and configuring it (Section 8), testing can begin. Testing the board consists of two parts selecting the Test Pattern, and adjusting the delay lines and checking the results Selecting the Test Pattern To select the Test Pattern, set S11 to the proper value for the desired Test Pattern (see Table 1 and Table 7). Then, depress the Master Reset button to load and run the test Adjusting the Register Delay Lines and Checking the Results A very common task that the RVB800 will be used for is checking the register timing, i.e. setup and hold times. This task is described in this section as an example. The recommended procedure for this operation is as follows: 1. Connect the oscilloscope to the clock, at least one register input bit, and the corresponding register output bit(s). The only way to verify test results with the RVB800 is visually. 2. Check on the oscilloscope that the register input waveform looks similar to the register output waveform, but delayed by approximately one clock cycle. If this is not the case, then the delay lines were not configured properly, and a timing parameter is being violated. The delay lines should be reconfigured (see Section 8.2). 3. If the input and output waveforms do look similar, then adjust the delay line timing, moving the input waveform in the direction that would test the desired timing parameter. 4. After each delay line adjustment, the register output should be checked on the oscilloscope, and the timing parameter being validated (for example setup or hold time) should be recorded. Occasionally, the RVB800 FPGA will fall into an undefined state due to the timing adjustment. If this occurs, it may be required to depress the Master Reset button again. 5. When the register output no longer matches the register input waveforms (ignoring the one clock cycle skew), a failure has occurred and the timing specification limit has been reached. The last recorded timing parameter is the limit of the device. 7/18/ of 54

37 If the register output still matches the register input waveforms, then no failure has occurred. Step 3 must be repeated until a failure occurs. If a fine timing resolution is required, it could take a long time to step through enough delays to find where the device fails (since the delay increments would be small). To save time, it is recommended that the delay line adjustment start out as a relatively large delay (for example 160ps) until a failure occurs. When a failure is found, the delay can be set back to the last known good delay, and Step 3 above repeated using smaller increments (for example 10ps or 20ps). The amount of the increment depends upon the desired timing resolution. If 100ps resolution is required, then an increment of 40ps will probably suffice. If 50ps or finer resolution is required, then an increment of 20ps or 10ps could be used. Keep in mind that the minimum step of the delay line is equivalent to approximately 10ps, which is difficult to measure. Also, the delay line has an overall delay of approximately 2.2ns to 12.2ns, so it is very easy to delay a signal multiple clock cycles with the delay line. Also, when adjusting the switch settings and multiple switches have to be flipped to obtain the proper increment, always change the MSB switch bit last. If the MSB bit is not switched last, a false error may occur due to the switches being momentarily set to a longer delay Timing References Finding an appropriate oscilloscope trigger to use can be difficult with some test patterns. The SDRAM write Test Patterns, for example, will refresh the SDRAM, open an SDRAM bank, execute eight 4-word burst writes (non-consecutive) to that bank, close the bank, and then execute eight 4-word bursts for four additional banks before beginning the loop again. If one wanted to trigger an oscilloscope to look at the second of the five burst writes, for example, it would be difficult since all of the burst writes appear the same except for the bank address bits that change during the write command. The RVB800 uses three Timing Reference signals to assist in triggering an oscilloscope. These Timing Reference signals (TIMING_REF[2:0]) can be easily probed at PCB locations TP[11:13]. For all SDRAM Test Patterns, TIMING_REF[0] is asserted simultaneously with the refresh command, TIMING_REF[1] is asserted simultaneously with the first bank activate command (for bank 0), and TIMING_REF[2] is asserted simultaneously with the first write or read command. TIMING_REF[3] is currently used for a specific function within the FPGA and cannot be used as a timing reference. 7/18/ of 54