PC2700 Unbuffered DDR MicroDIMM Reference Design Specification Revision 0.11 March 25, 2001 JC42.5 Item # BOARD OF DIRECTORS BALLOT

Transcription

1 PC2700 Unbuffered MicroDIMM Reference Design Specification Revision 0.11 March 25, 2001 JC42.5 Item # BOARD OF DIRECTORS BALLOT

2 Unbuffered MicroDIMM Contents 1. Product Description... 3 Product Family Attributes... 3 Product Family Variations (Raw Cards) Environmental Requirements Architecture... 4 Pin Description... 4 Input/Output Functional Description... 5 SDRAM MicroDIMM Pinout... 6 Block Diagram: Raw Card Versions A & B, one physical bank of x Block Diagram: Raw Card Version C, two physical banks of x Component Details... 9 Ball Assignments for x16 SDRAM FBGA Components... 9 Ball Assignments for x16 SDRAM TSOP Components Reference SDRAM Component Specifications Reference SPD Component Specifications Unbuffered MicroDIMM Details SDRAM Module Configurations (Reference Designs) SDRAM MicroDIMM Gerber File Releases Example Raw Card Component Placement, TSOP version Example Raw Card Component Placement, FBGA versions MicroDIMM Wiring Details Signal Groups General Net Structure Routing Guidelines Explanation of Net Structure Diagrams Logical Clock Net Structures Clock Net Wiring Data, Data Mask, Strobe Net Structures Select and Clock Enable Net Structures Address/Control Net Structures, Raw Card A Only Address/Control Net Structures, Raw Cards B & C Only Cross Section Recommendations Serial Presence Detect Definition MicroDIMM Mechanical Specifications Reference Simplified Mechanical Drawing with Keying Position Optional Edge Bevel Reference Motherboard Footprint and Shadow Zone Mechanical Clearances Page 2 Revision 0.11

3 Unbuffered MicroDIMM 1. Product Description 1. Product Description This reference specification defines the electrical and mechanical requirements for the 172-pin, 167 MHz clock (333 MT/s data rate), 64-bit wide, Unbuffered Double Data Rate () Synchronous DRAM Micro Dual In-Line Memory Modules ( SDRAM MicroDIMMs). These SDRAM MicroDIMMs are intended for use as main memory when installed in systems such as mobile personal computers. Reference design examples are included which provide an initial basis for Unbuffered MicroDIMM designs. Modifications to these reference designs are permitted as long as they meet all system timing, signal integrity and thermal requirements for 167 MHz clock rate support. Other designs are acceptable, and all Unbuffered MicroDIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design. Product Family Attributes Attribute Value Notes MicroDIMM Organization x 64 MicroDIMM Dimensions (nominal) MicroDIMM Types Supported or mm high, 45.5 mm wide Unbuffered Pin Count 172 SDRAMs Supported 64 Mb, 128 Mb, 256 Mb, 512 Mb, 1 Gb 2 Capacity 32 MB, 64 MB, 128 MB, 256 MB, 512 MB, 1 GB 2 Serial Presence Detect Consistent with JEDEC Rev. 1.0 Voltage Options Interface 2.5 V V DD 2.5 V V DD Q 2.5 V to 3.3 V V DD SPD 1 SSTL_2 Note 1: V DD SPD is not tied to V DD or V DD Q on the MicroDIMM. Note 2: Raw card A MicroDIMMs do not support 1 Gb memories. Raw cards B and C do support them. Product Family Variations (Raw Cards) Raw Card Device Type Module Bus Width Device Width Number of Devices Physical Banks Capacity A TSOP x64 x MB B FBGA x64 x MB C FBGA x64 x MB - 1 GB Revision 0.11 Page 3

4 2. Environmental Requirements Unbuffered MicroDIMM 2. Environmental Requirements SDRAM Unbuffered MicroDIMMs are intended for use in mobile computing environments that have limited capacity for heat dissipation. Absolute Maximum Ratings Symbol Parameter Rating Units Notes T OPR Operating Temperature (ambient) 0 to +65 C 1 H OPR Operating Humidity (relative) 10 to 90 % 1 T STG Storage Temperature -50 to +100 C 1 H STG Storage Humidity (without condensation) 5 to 95 % 1 Barometric Pressure (operating & storage) 105 to 69 kpa 1, 2 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. Architecture Pin Description CK(0:1) Clock Inputs, positive line 2 DQ(0:63) Data Input/Output 64 CK(0:1) Clock inputs, negative line 2 DM(0:7) Data Masks 8 CKE(0:1) Clock Enables 2 DQS(0:7) Data strobes 8 RAS Row Address Strobe 1 SCL Serial Presence Detect (SPD) Clock Input 1 CAS Column Address Strobe 1 SDA SPD Data Input/Output 1 WE Write Enable 1 SA(0:2) SPD address 3 S(0:1) Chip Selects 2 V DD Core and I/O Power 28 A(0:9,11-13) Address Inputs 13 V SS Ground 28 A10/AP Address Input/Autoprecharge 1 V REF Input/Output Reference 2 BA(0:1) SDRAM Bank Address 2 V DD SPD SPD Power 1 DU Reserved for future use 1 Total: 172 Page 4 Revision 0.11

5 Unbuffered MicroDIMM 3. Architecture Input/Output Functional Description Symbol Type Polarity Function CK0 - CK1, CK0 - CK1 Input Cross point The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. CKE0, CKE1 Input Active High S0, S1 Input Active Low Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1. RAS, CAS, WE Input Active Low When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE define the operation to be executed by the SDRAM. BA0 - BA1 Input Selects which SDRAM bank of four is activated. A0 - A9, A11-A13 A10/AP Input During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If AP is low, then BA0 and BA1 are used to define which bank to precharge. DQ0 - DQ63 In/Out Data Bit Input/Output pins. DM0 - DM7 Input Active High DQS0 - DQS7 In/Out The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the SDRAMs and is sent at the leading edge of the data window. V DD, V DD SPD, V SS Supply Power supplies for core, I/O, Serial Presence Detect, and ground for the module. SDA In/Out SCL Input This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected to V DD to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to V DD to act as a pull up. SA0 - SA2 Input Address pins used to select the Serial Presence Detect. Revision 0.11 Page 5

6 3. Architecture Unbuffered MicroDIMM. Unbuffered MicroDIMM Pinout Pin Front # Side Pin Back # Side Pin Front # Side Pin Back # Side Pin Front # Side Pin Back # Side Pin Front # Side Pin Back # Side 1 V REF 2 V REF 45 V DD 46 V DD 89 V DD 90 V DD 133 V SS 134 CK1 3 V SS 4 V SS 47 DQS2 48 DM2 91 BA0 92 RAS 135 V SS 136 V SS 5 DQ0 6 DQ4 49 DQ18 50 DQ22 93 WE 94 CAS 137 DQ DQ52 7 DQ1 8 DQ5 51 V SS 52 V SS 95 S0 96 S1 139 DQ DQ53 9 V DD 10 V DD 53 DQ19 54 DQ23 97 A13 98 RFU 141 V DD 142 V DD 11 DQS0 12 DM0 55 DQ24 56 DQ28 99 V SS 100 V SS 143 DQS6 144 DM6 13 DQ2 14 DQ6 57 V DD 58 V DD 101 DQ DQ DQ DQ54 15 V SS 16 V SS 59 DQ25 60 DQ DQ DQ V SS 148 V SS 17 DQ3 18 DQ7 61 DQS3 62 DM3 105 V DD 106 V DD 149 DQ DQ55 19 DQ8 20 DQ12 63 V SS 64 V SS 107 DQS4 108 DM4 151 DQ DQ60 21 V DD 22 V DD 65 DQ26 66 DQ DQ DQ V DD 154 V DD 23 DQ9 24 DQ13 67 DQ27 68 DQ V SS 112 V SS 155 DQ DQ61 25 DQS1 26 DM1 69 V DD 70 V DD 113 DQ DQ DQS7 158 DM7 27 V SS 28 V SS 71 CKE1 72 CKE0 115 DQ DQ V SS 160 V SS 29 DQ10 30 DQ14 73 A12 74 A V DD 118 V DD 161 DQ DQ62 31 DQ11 32 DQ15 75 A9 76 A8 119 DQ DQ DQ DQ63 33 V DD 34 V DD 77 A7 78 A6 121 DQS5 122 DM5 165 V DD 166 V DD 35 CK0 36 V DD 79 V SS 80 V SS 123 V SS 124 V SS 167 SDA 168 SA0 37 CK0 38 V SS 81 A5 82 A4 125 DQ DQ SCL 170 SA1 39 V SS 40 V SS 83 A3 84 A2 127 DQ DQ V DD SPD 172 SA2 41 DQ16 42 DQ20 85 A1 86 A0 129 V DD 130 V DD 43 DQ17 44 DQ21 87 A10/AP 88 BA1 131 V DD 132 CK1 Note: Page 6 Revision 0.11

7 Unbuffered MicroDIMM 3. Architecture Block Diagram: Raw Card Versions A & B (Populated as 1 physical bank of x16 SDRAMs) DQS0 DM0 DQS1 DM1 CKE1 S1 CKE0 S0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 N.C. N.C. CS CKE D0 DQS4 DM4 DQS5 DM5 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS D2 CKE Load matching Capacitors on A0-AN RAS CAS WE CKE0 S0 X pf Raw card A Raw card B 10 pf 10 pf DQS2 DM2 DQS3 DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS D1 CKE DQS6 DM6 DQS7 DM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS D3 CKE SCL SA0 SA1 SA2 Serial Presence Detect (SPD) A0 SDA A1 A2 WP BA0-BA1 A0-AN* RAS CAS WE V DD SPD V REF V DD SDRAMS D0-D3 SDRAMS D0-D3 SDRAMS D0-D3 SDRAMS D0-D3 SDRAMS D0-D3 SPD SDRAMS D0-D3 SDRAMS D0-D3 V DD and V DD Q #Unless otherwise noted, resistor values are 22 5% * Address A13 is supported on Raw Card B but not on Raw Card A. CK0 CK0 CK1 CK1 2 loads + 2 load caps 2 loads + 2 load caps Note: DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. V SS SDRAMS D0-D3, SPD Revision 0.11 Page 7

8 3. Architecture Unbuffered MicroDIMM Block Diagram: Raw Card Version C (Populated as 2 physical banks of x16 SDRAMs) DQS0 DM0 DQS1 DM1 CKE1 CKE0 S1 S0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS CKE LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D0 CS CKE LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D4 DQS4 DM4 DQS5 DM5 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS CKE LDQS LDM UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D2 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CSCKE LDQS LDM UDQS UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D6 Load matching Capacitors on CKE0 S0 CKE1 S1 X pf Raw card C 10 pf DQS2 DM2 DQS3 DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0-BA1 A0-AN* RAS CAS WE V DD SPD V REF V DD V SS CS CKE CS CKE CS CKE CS CKE LDQS LDQS DQS6 LDQS LDQS LDM LDM DM6 LDM LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 DQ48 DQ49 DQ50 DQ51 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 4 DQ52 I/O 4 I/O 5 D1 D5 I/O 4 I/O 5 DQ53 I/O 5 D3 I/O 5 D7 I/O 6 I/O 7 I/O 6 I/O 7 DQ54 DQ55 I/O 6 I/O 7 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDRAMS D0-D7 SDRAMS D0-D7 SDRAMS D0-D7 SDRAMS D0-D7 SDRAMS D0-D7 SPD SDRAMS D0-D7 SDRAMS D0-D7 DQS7 DM7 SDRAMS D0-D7, SPD DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 V DD and V DD Q UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 #Unless otherwise noted, resistor values are 22 5% * Address A13 is supported on Raw Card C. SCL SA0 SA1 SA2 CK0 CK0 CK1 CK1 Serial Presence Detect (SPD) A0 A1 A2 WP 4 loads 4 loads SDA Note: DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. Page 8 Revision 0.11

9 Unbuffered MicroDIMM 4. Component Details 4. Component Details Ball Assignments for x16 SDRAM FBGA Components (Top View) VSSQ DQ15 VSS A VDD DQ0 VDDQ DQ14 VDDQ DQ13 B DQ2 VSSQ DQ1 DQ12 VSSQ DQ11 C DQ4 VDDQ DQ3 DQ10 VDDQ DQ9 D DQ6 VSSQ DQ5 DQ8 VSSQ UDQS E LDQS VDDQ DQ7 VREF VSS UDM F LDM VDD A13 CK CK G WE CAS A12 CKE H RAS CS A11 A9 J BA1 BA0 A8 A7 K A0 A10/AP A6 A5 L A2 A1 A4 VSS M VDD A3 Note: SDRAM MicroDIMMs support the use of SDRAM FBGA devices. These ball assignments are consistent with the JEDEC standard package definition. A13 not used on densities below 1 Gb. Revision 0.11 Page 9

10 4. Component Details Unbuffered MicroDIMM Pin Assignments for x16 SDRAM TSOP Components (Top View) V DD DQ0 V DD Q DQ1 DQ2 V SS Q DQ3 DQ4 V DD Q DQ5 DQ6 V SS Q DQ7 NC V DD Q LDQS A13 V DD NU,QFC LDM WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 V DD V SS DQ15 V SS Q DQ14 DQ13 V DD Q DQ12 DQ11 V SS Q DQ10 DQ9 V DD Q DQ8 NC V SS Q UDQS NC V REF V SS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 V SS 66-pin Plastic TSOP-II 400 mil Note: SDRAM MicroDIMMs support the use of SDRAM TSOP-II devices. These pin assignments are consistent with the JEDEC standard package definition. A13 not used on densities below 1 Gb. Page 10 Revision 0.11

11 Unbuffered MicroDIMM 4. Component Details Reference SDRAM Component Specifications The SDRAM components used with this MicroDIMM design specification are intended to be consistent with the latest revision of the JEDEC 333, 266, and 200 SDRAM specifications. Refer to standard JESD-79 for component details. Reference SPD Component Specifications The Serial Presence Detect EEPROMs have their own power pin, V DD SPD, so that they can be programmed or read without powering up the rest of the module. The wide voltage range permits use with 2.5V or 3.3V serial buses. DC Electrical Characteristics Symbol Parameter Min Max Units V DD SPD Core Supply Voltage V Revision 0.11 Page 11

12 5. Unbuffered MicroDIMM Details Unbuffered MicroDIMM 5. Unbuffered MicroDIMM Details SDRAM Module Configurations (Reference Designs) Raw Card Version Micro- DIMM Capacity MicroDIMM Organization SDRAM Density SDRAM Organization # of SDRAMs SDRAM Package Type # of Physical Banks # of Banks in SDRAM # Address bits row/col A 32 MB 4 M x Mbit 4 M x TSOP /8 A 64 MB 8 M x Mbit 8 M x TSOP /9 A 128 MB 16 M x Mbit 16 M x TSOP /9 A 256 MB 32 M x Mbit 32 M x TSOP /10 B 32 MB 4 M x Mbit 4 M x FBGA /8 B 64 MB 8 M x Mbit 8 M x FBGA /9 B 128 MB 16 M x Mbit 16 M x FBGA /9 B 256 MB 32 M x Mbit 32 M x FBGA /10 B 512 MB 64 M x 64 1 Gbit 64 M x FBGA /10 C 64 MB 8 M x Mbit 4 M x FBGA /8 C 128 MB 16 M x Mbit 8 M x FBGA /9 C 256 MB 32 M x Mbit 16 M x FBGA /9 C 512 MB 64 M x Mbit 32 M x FBGA /10 C 1 GB 128 M x 64 1 Gbit 64 M x FBGA /10 SDRAM MicroDIMM Gerber Releases Reference design file updates will be released as needed. This specification will reflect the most recent design files, but may be updated to reflect clarifications to the specification only; in these cases, the design files will not be updated. The following table outlines the most recent design file releases: Raw Card Specification Revision Applicable design file Notes A 0.2 A0 B 0.2 B0 C 0.2 C0 Page 12 Revision 0.11

13 Unbuffered MicroDIMM 5. Unbuffered MicroDIMM Details Example Raw Card Component Placement, TSOP Version The component layout for Raw Card A. This example is for reference only; please refer to JEDEC standard MO-214 for details. 1.0 mm Front View 1.0 mm Component Keepout Area SPD SDRAMs Rear View 1.0 mm 1.0 mm SDRAMs Revision 0.11 Page 13

14 5. Unbuffered MicroDIMM Details Unbuffered MicroDIMM Example Raw Card Component Placement, FBGA Versions The component layout for Raw Cards B and C are similar. In the case of Raw Card B, only 4 SDRAMs on one side are stuffed; however, discrete components such as resistors or capacitors are stuffed on both sides of Raw Card B. This example is for reference only; please refer to JEDEC standard MO-214 for details. The maximum FBGA package footprint supported by this layout is 8.5 x 17 mm. 1.0 mm SDRAMs Front View SDRAMs SPD 1.0 mm Component Keepout Area Rear View 1.0 mm 1.0 mm SDRAMs SDRAMs Page 14 Revision 0.11

15 Unbuffered MicroDIMM 6. MicroDIMM Wiring Details 6. MicroDIMM Wiring Details Signal Groups This reference specification categorizes SDRAM timing-critical signals into groups whose members have identical loadings and routings. The following table summarizes the signals contained in each group.. Signal Group Signals In Group Pages Clocks for Unbuffered MicroDIMM CK [1:0], CK [1:0] 16 Data, Check Bits, Data Mask, Data Strobe DQ [63:0], DM[7:0], DQS[7:0] 17 Select, Clock Enable S [1:0], CKE [1:0] 18 Address/Control Ax, BAx, RAS, CAS, WE 19, 20 General Net Structure Routing Guidelines Net structures and lengths must satisfy signal quality and setup/hold time requirements for the memory interface. Net structure diagrams for each signal group are shown in the following sections. Each diagram is accompanied by a trace length table that lists the minimum and maximum allowable lengths for each trace segment and/or net. The general routing recommendations are as follows. Other stackups and layouts are possible that meet the electrical characteristics. Route all signal traces including clocks using 0.10 mm rules, 0.15 mm minimum spacing between adjacent traces. Route clocks as much as possible using the inner layers. No test points are required. Explanation of Net Structure Diagrams The net structure routing diagrams provide a reference design example for each raw card version. These designs provide an initial basis for unbuffered MicroDIMM designs. The diagrams should be used to determine individual signal wiring on a MicroDIMM for any supported configuration. Only transmission lines (represented as cylinders and labeled with trace length designators TL ) represent physical trace segments. All other lines are zero in length. To verify MicroDIMM functionality, a full simulation of all signal integrity and timing is required. The given net structures and trace lengths are not inclusive for all solutions. Once the net structure has been determined, the permitted trace lengths for the net structure can be read from the table below each net structure routing diagram. Some configurations require the use of multiple net structure routing diagrams to account for varying load quantities on the same signal. All diagrams define one load as one SDRAM input. The net structure routing data in this document accurately represent reference Raw Card versions A, B and C. Revision 0.11 Page 15

16 6. MicroDIMM Wiring Details Unbuffered MicroDIMM Logical Clock Net Structures DRAM MicroDIMM MicroDIMM DRAM Connector Connector CK CK DRAM DRAM CK Cap CK DRAM Cap DRAM Two Loads (Raw card A) Four Loads (Raw card C) DRAM MicroDIMM Cap Connector CK CK DRAM Cap Two Loads (Raw card B) CK CK Cap Raw card A: 0.5 pf Raw card B: 1.0 pf Clock Net Wiring TL1 TL2 SDRAM or Cap CK CK MicroDIMM Connector TL0 TL1 TL2 TL2 SDRAM or Cap SDRAM or Cap TL2 SDRAM or Cap Clock Routing Trace Lengths: Segment TL0 TL1 TL2 Raw Card Min Max Min Max Min Max A B, C All distances are given in millimeters and should be kept within a tolerance of ± 0.25 millimeter Page 16 Revision 0.11

17 Unbuffered MicroDIMM 6. MicroDIMM Wiring Details Data Net Structures DQ[63:0], DM[7:0], DQS[7:0] Net Structure Routing for Data, Data Mask, Data Strobe MicroDIMM Connector TL0 22 5% TL1 TL2 TL2 For designs using two physical banks Trace Lengths for Data Net Structure TL0 TL1 TL2 Raw card Min Max Min Max Min Max A B C All distances are given in millimeters and should be kept within a tolerance of ± 0.25 millimeter Revision 0.11 Page 17

18 6. MicroDIMM Wiring Details Unbuffered MicroDIMM Select and Clock Enable Net Structures S [1:0], CKE[1:0] Net Structure Routing for Select and Clock Enable TL3 TL2 TL3 TL1 MicroDIMM Connector TL0 TL4 Load Cap TL1 TL3 TL2 TL3 Trace Lengths for Select and Clock Enable Net Structures TL0 TL1 TL2 TL3 TL4 Raw Card Min Max Min Max Min Max Min Max Min Max A B C All distances are given in millimeters and should be kept within a tolerance of ± 0.25 millimeter Page 18 Revision 0.11

19 Unbuffered MicroDIMM 6. MicroDIMM Wiring Details Address/Control Net Structures Ax, BAx, RAS, CAS, WE Net Structure Routing for Address and Control, Raw Card A Only TL2 TL2 MicroDIMM Connector TL0 TL1 TL3 Load Cap TL1 TL2 TL2. Trace Lengths for Address and Control Net Structures, Raw Card A Only TL0 TL1 TL2 TL3 Raw Card Min Max Min Max Min Max Min Max A All distances are given in millimeters and should be kept within a tolerance of ± 0.25 millimeter. Revision 0.11 Page 19

20 6. MicroDIMM Wiring Details Unbuffered MicroDIMM Address/Control Net Structures Ax, BAx, RAS, CAS, WE Net Structure Routing for Address and Control, Raw Cards B & C TL3 TL3 TL2 Raw Card C only TL3 TL3 Raw Card B only TL1 MicroDIMM Connector TL0 TL4 Load Cap TL3 TL1 TL3 Raw Card C only TL2 TL3 TL3 Trace Lengths for Address and Control Net Structures, Raw Cards B & C Only TL0 TL1 TL2 TL3 TL4 Raw Card Min Max Min Max Min Max Min Max Min Max B C na All distances are given in millimeters and should be kept within a tolerance of ± 0.25 millimeter Page 20 Revision 0.11

21 Unbuffered MicroDIMM 6. MicroDIMM Wiring Details Cross Section Recommendations The MicroDIMM printed circuit board design uses six-layers of glass epoxy material. PCBs must contain full ground plane and full power plane layers. The PCB stackup must be designed with 0.10 mm wide traces with 0.15 mm spacing. The required board impedance is 60 ± 10%. Note: The PCB edge connector contacts shall be gold-plated; beveled edges are optional. PCB Electrical Specifications Parameter Min Max Units Trace velocity: S0 (outer layers) ps/mm Trace velocity: S0 (inner layers) ps/mm Trace impedance: Z0 (all layers) Ohms Example Layer Stackup mm 0.07 mm 0.15 mm 0.13 mm 0.15 mm 0.07 mm Signal Layer 1 = mm Ground Layer 2 = mm Signal Layer 3 = mm Signal Layer 4 = mm Voltage Layer 5 = mm Signal Layer 6 = mm Component Types and Placement Components shall be surface mounted on both sides of the PCB and positioned on the PCB to meet the minimum and maximum trace lengths required for SDRAM signals. Bypass capacitors, for SDRAM devices, must be practically located near the device power pins. Reference Voltage Vias A minimum of two vias located near the connector pins should be used to connect V REF to its inner routing layer. Revision 0.11 Page 21

22 7. Serial Presence Detect Definition Unbuffered MicroDIMM 7. Serial Presence Detect Definition The Serial Presence Detect (SPD) function MUST be implemented on the SDRAM Unbuffered Micro- DIMM. The component used and the data contents must adhere to the most recent version of the JEDEC SDRAM SPD Specifications. Please refer to this document for all technical specifications and requirements of the serial presence detect devices. The following table is intended to be an example of a typical SDRAM MicroDIMM. SPD values indicating different MicroDIMM performance characteristics will be utilized based on specific characteristics of the SDRAMs or MicroDIMMs. This example assumes: Module Organization: 16 M x 64 (128 Mbyte) Device Composition: 2 M x 16 bits x 4 banks (128 Mbit) Module Physical Banks: 2 Refresh: 4 K in 64 ms Serial Presence Detect Data Example (Part 1 of 3) Byte # Description 333 SPD Entry Value 266A 266B 333 Serial PD Data Entry (Hexadecimal) 0 Number of Serial PD Bytes Written during Production 128 bytes 80 1 Total Number of Bytes in Serial PD device 256 bytes 08 2 Fundamental Memory Type SDRAM 07 3 Number of Row Addresses on Assembly 12 0C 4 Number of Column Addresses on Assembly Number of MicroDIMM Banks Data Width of Assembly 64 bits 40 7 Data Width of Assembly (continued) 64 bits 00 8 Assembly Voltage Interface Levels (V DD Q) SSTL_ A 266B 9 SDRAM Device Cycle Time at CL = 2.5 (t CK ) 6.0 ns 7.5 ns 7.5 ns SDRAM Device Access Time from Clock (t AC ) 0.70 ns 0.75 ns 0.75 ns Assembly Error Detection/Correction Scheme Non-parity, non-ecc Assembly Refresh Rate/Type 15.6 s Self Refresh SDRAM Device Width x Error Checking SDRAM Device Width Not used Minimum CK Delay, Random Col Access (t CCD ) 1 clock Burst Lengths Supported 2, 4, 8 0E 17 Number of Device Banks CAS Latency 2.5 and 2.0 0C 1. Minimum application clock cycle time is 7.5 ns (133 MHz). 2. cc = Checksum Data byte, 00-FF (Hex). 3. ww = Binary coded decimal week code, (Decimal) (Hex). 4. yy = Binary coded decimal year code, 0-00 (Decimal) (Hex). 5. ss = Serial number data byte, 00-FF (Hex). 6. Unused bytes are set to the value "00". 7. Unused bits in attribute bytes are set to "0". Notes Page 22 Revision 0.11

23 Unbuffered MicroDIMM 7. Serial Presence Detect Definition Serial Presence Detect Data Example (Part 2 of 3) Byte # Description 19 CS Latency 0 clocks WE Latency 1 clock SDRAM Module Attributes Differential clocks General SDRAM Device Attributes Weak drivers Minimum Clock Cycle at CL = 2.0 (t CK ) 7.5 ns 7.5 ns 10 ns A Maximum Data Access Time (t AC ) from Clock at CL = ns 0.75 ns 0.75 ns Minimum Clock Cycle Time at CL = 1.5 (t CK ) N/A Maximum Data Access Time (t AC ) from Clock at CL = 1.5 N/A Minimum Row Precharge Time (t RP ) 20 ns Minimum Row Active to Row Active delay (t RRD ) 15 ns 3C 29 Minimum RAS to CAS delay (t RCD ) 20 ns Minimum Active to Precharge Time (t RAS ) 42 ns 45 ns 45 ns 2A 2D 2D 31 Module Physical Bank Density 64 MB Address and Command Setup Time Before Clock (t IS ) 0.75 ns 0.9 ns 0.9 ns Address and Command Hold Time After Clock (t IH ) 0.75 ns 0.9 ns 0.9 ns Data Input and Mask Setup Time Before Clock (t DS ) 0.45 ns 0.5 ns 0.5 ns Data Input and Mask Hold Time After Clock (t DH ) 0.45 ns 0.5 ns 0.5 ns Superset information No superset Row cycle time (t RC ) 60 ns 65 ns 70 ns 3C Auto Refresh cycle time (t RFC ) 72 ns 75 ns 80 ns 48 4B Maximum SDRAM device cycle time (t CK max) 12 ns 12 ns 12 ns DQS-DQ Skew (t DQSQ ) 0.45 ns 0.50 ns 0.60 ns 2D 32 3C 45 SDRAM Device Data Hold Skew Factor (t QHS ) 0.60 ns 0.75 ns 1.0 ns A Reserved SPD Revision JEDEC Checksum for bytes 0-62 Calculated value cc cc cc Manufacturers JEDEC ID Code 6 72 Assembly Manufacturing Location Module Part Number Minimum application clock cycle time is 7.5 ns (133 MHz). 2. cc = Checksum Data byte, 00-FF (Hex). 3. ww = Binary coded decimal week code, (Decimal) (Hex). 4. yy = Binary coded decimal year code, 0-00 (Decimal) (Hex). 5. ss = Serial number data byte, 00-FF (Hex). 6. Unused bytes are set to the value "00". 7. Unused bits in attribute bytes are set to "0". SPD Entry Value 266A 266B 333 Serial PD Data Entry (Hexadecimal) 266A 266B Notes Revision 0.11 Page 23

24 7. Serial Presence Detect Definition Unbuffered MicroDIMM Serial Presence Detect Data Example (Part 3 of 3) Byte # Description Module Revision Code Module Manufacturing Date 3, Module Serial Number Manufacturer s Specific Data Open for Customer Use Undefined Minimum application clock cycle time is 7.5 ns (133 MHz). 2. cc = Checksum Data byte, 00-FF (Hex). 3. ww = Binary coded decimal week code, (Decimal) (Hex). 4. yy = Binary coded decimal year code, 0-00 (Decimal) (Hex). 5. ss = Serial number data byte, 00-FF (Hex). 6. Unused bytes are set to the value "00". 7. Unused bits in attribute bytes are set to "0". SPD Entry Value 266A 266B 333 Serial PD Data Entry (Hexadecimal) 266A 266B Notes Page 24 Revision 0.11

25 Unbuffered MicroDIMM 8. MicroDIMM Mechanical Specifications 8. MicroDIMM Mechanical Specifications JEDEC JC-11 has standardized the detailed mechanical information for the 172 Pin MicroDIMM family. This example is for reference only; please refer to JEDEC standard MO-214 for details. Reference Simplified Mechanical Drawing with Keying Position Front mm 1.45 mm max. Side SDRAMs SDRAMs SPD mm or mm * mm 1.45 mm max mm Pin Spacing Detail 0.37 mm 0.25 mm max 2.50 mm min 1.00 mm Component Keepout Area * Note: Raw Card A = MO-214 Variation BD = mm Raw Card B = MO-214 Variation AD = mm Raw Card C = MO-214 Variation AD = mm 0.50 mm Optional Edge Bevel Edge bevels for MicroDIMMs, if implemented, must follow these guidelines. This information is for reference only; please refer to JEDEC JC-11 standard MO-214 for details 0.20 ± 0.05 mm 0.20 ± 0.05 mm Revision 0.11 Page 25

26 8. MicroDIMM Mechanical Specifications Unbuffered MicroDIMM Reference Motherboard Footprint, Standard and Reverse Sockets JEDEC JC-11 has standardized the detailed mechanical information for the 172 Pin MicroDIMM family. This example is for reference only; please refer to JEDEC standard MO-214 for details. Designs using reverse keyed sockets may have applicable patents, including 5,882,211 and 6,113,398. Page 26 Revision 0.11

27 Unbuffered MicroDIMM 8. MicroDIMM Mechanical Specifications Reference Socket Shadow Zone, Standard and Reverse Sockets This example is for reference only; please refer to JEDEC standard MO-214 for details. Revision 0.11 Page 27

28 8. MicroDIMM Mechanical Specifications Unbuffered MicroDIMM Reference Mechanical Clearances Guidelines for base board application of MicroDIMM solutions follow to describe the vertical clearance available. This information is for reference only; please refer to JEDEC JC-11 standard MO-214 for details mm max Module Assembly Length 3.80 mm max Socket thickness MicroDIMM Socket Components MicroDIMM board Components Motherboard clearance Module mating Base board Parameter Socket var XX Socket var YY Units Socket thickness Module mating line (PCB center) Motherboard clearance mm mm mm Parameter Raw Card A Raw Cards B & C Units Module assembly length mm Page 28 Revision 0.11

29 Unbuffered MicroDIMM 8. MicroDIMM Mechanical Specifications 9.0 Product Label The following label should be applied to all PC2700-compatible Unbuffered MicroDIMMs, to fully describe the key attributes of the module. The label can be in the form of a stickon label, silk screened onto the assembly, or marked using an alternate customer-readable format. A minimum font size of 8 points should be used, and the number can be printed in one or more rows on the label. Format: Where: Example: PC2700m-aabc-d-ef m: Module Type M= Unbuffered MicroDIMM (no registers or PLLs on module) aa: SDRAM CAS Latency 20 = CAS Latency = CAS Latency 2.5 b: SDRAM minimum t RCD specification (in clocks) c: SDRAM minimum t RP specification (in clocks) d: JEDEC SPD Revision used on this MicroDIMM 0 = JEDEC SPD revision 0 e: Gerber file used for this design (if applicable) A = Reference design for raw card A is used for this assembly B = Reference design for raw card B is used for this assembly C = Reference design for raw card C is used for this assembly Z = None of the Reference" designs were used for this assembly f: Revision number of the reference design used 1 = 1st revision 2 = 2nd revision Blank = Not applicable (used with Z above) PC2700M B2 is a PC2700 Unbuffered MicroDIMM with CAS Latency = 2.0, t RCD = 3, t RP = 3, using JEDEC SPD revision 2 and produced based on the raw card B Gerber, 2nd release Revision 0.11 Page 29

30 8. MicroDIMM Mechanical Specifications Unbuffered MicroDIMM HISTORY: Date Revision Pages Notes 4/25/ Corrected typo. 3/15/ Added mention of loading caps on clock pairs. 6 Changed DU(BA2) to RFU since no plans for 8 banks are expected for I through 2Gb. 3/12/ Adjusted raw card A trace lengths Added title to pages; clarified wording referencing JC-11 specifications. 12 Split cards A and B in tables. 3/1/01 14 Wording clarification. 24 Corrected dimension from card edge to top of finger. 3 Updated tables to reflect change Raw Card A not supporting 1 Gb memories. 4 Another FrameMaker font problem fixed. 7 Changed loading cap from 11 to 10 pf. Added note stating A13 support for each card. 8 Added loading caps for S, CKE. Added note stating A13 support. 10 Added A12 (typo fix). 2/28/01 12 Adjusted tables to remove 1 Gb support for raw card A. 14 Changed allowable FBGA package size to be 8.5 x 17 mm , 21 Converted trace widths and gaps to metric. 16 Changed raw card A clock cap to 0.5 pf Adjusted trace lengths to allow for A13. 26, 27 Inserted new mechanical drawings. 28 Reorganized to match latest JC-11 proposals and socket thicknesses. 13,14 Eliminated alignment holes 2/23/01 15 Specified clock rules to be same as all other signals. 22 Corrected font problem (15ms -> 15 s)... boy, I dislike FrameMaker. 25 Corrected height dimensions and pin dimensions with respect to card edge, added notch height. Replaced 80 FBGA with 60 FBGA representation. 2/22/ Corrected page references, eliminated requirement for ground ring. 21 Corrected trace velocities, converted to ps/mm. 3, 4, 12 Added 1Gb SDRAM support. 6 Shifted VSS and VDD in address section for better balance. 2/21/ Changed trace length tolerance to 0.25 mm. 19, 20 Split raw card A and raw cards B&C address nets separately. 25 Added MO-214 variation indicators. 28 Redimensioned based on JEITA meeting. 2/9/ Shifted A13 and BA2 to match DIMM shift. Page 30 Revision 0.11

31 Unbuffered MicroDIMM 8. MicroDIMM Mechanical Specifications HISTORY: Date Revision Pages Notes 2/1/ Added optional edge bevel specification. 9 Split capacitance values for all raw card clock pairs. 27 Added product label 1/30/ Added mechanical clearances page 9, Added raw card trace layout data 1/18/ Typo correction. 7 Added load capacitor to S and CKE lines. 10 Inserted latest FBGA ballout. 13 Simplified tables, removed x8 references. 16 Specifies 4/6 rules. 18 Added load capacitor. 19 Added load cap for one bank, clarified two bank option. 20 PCB thickness specified, layers still TBD. 21, 22 Added new SPD fields, and current proposals for Changed board thickness to match newest JC-11 specification. 3 Clarified wording to indicate that changes to these reference specs are not needed but may be done. 10 Removed parallel termination resistor on clocks. 10/13/ , 12, 15, 25 Changed FBGA ballout to match latest proposals for 80FBGA. 23 Added new SPD entries. 26 Added new page for socket footprint. 8/29/ All First draft, edited from SO-DIMM reference specification Revision 0.11 Page 31

32 8. MicroDIMM Mechanical Specifications Unbuffered MicroDIMM Page 32 Revision 0.11