Concurrent Technologies Inc 6 Tower Office Park Woburn, MA USA Tel: (781) Fax: (781)

Transcription

1 Technical Reference Manual for VX 91x/01x VME/VXS 3 rd Generation Intel Core Processor Dual PMC/XMC VITA 41.4 Controller Manual Order code Rev 03 November 2012 Concurrent Technologies Inc 6 Tower Office Park Woburn, MA USA Tel: (781) Fax: (781) Concurrent Technologies Plc 4 Gilberd Court Newcomen Way Colchester, Essex CO4 9WN United Kingdom Tel: (+44) Fax: (+44) info@gocct.com

2 NOTES Information furnished by Concurrent Technologies is believed to be accurate and reliable. However, Concurrent Technologies assumes no responsibility for any errors contained in this document and makes no commitment to update or to keep current the information contained in this document. Concurrent Technologies reserves the right to change specifications at any time without notice. Concurrent Technologies assumes no responsibility either for the use of this document or for any infringements of the patent or other rights of third parties which may result from its use. In particular, no license is either granted or implied under any patent or patent rights belonging to Concurrent Technologies. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Concurrent Technologies. All companies and product names are trademarks of their respective companies. CONVENTIONS Throughout this manual the following conventions will apply: # or * after a name represents an active low signal, e.g. INIT# or INIT* 0x denotes a hexadecimal number, e.g. 0xFF45 byte represents 8-bits word represents 16-bits dword represents 32-bits NOTATIONAL CONVENTIONS NOTE: Notes provide general additional information. WARNING: Warnings provide indication of board malfunction if they are not observed. CAUTION: Cautions provide indications of board or system damage if they are not observed. ii VX 91x/01x

3 GLOSSARY OF TERMS ACPI... Advanced Configuration and Power Interface APIC... Advanced Programmable Interrupt Controller ATA... AT Attachment BIOS... Basic Input Output System CMOS... Complementary Metal Oxide Semiconductor CODEC... Coder / Decoder CPU... Central Processing Unit CUTE... CCT Unified Test Environment DDR3... Double Data Rate, third generation DIL... Dual In Line DMA... Direct Memory Access DMI... Direct Media Interface DRAM... Dynamic Random Access Memory ECC... Error Checking and Correcting EIDE... Enhanced Integrated Drive Electronics EMC... Electromagnetic Compatibility EPROM... Electrically Programmable Read Only Memory EEPROM... Electrically Erasable Programmable Read Only Memory GMCH... Graphics Memory Controller Hub IEEE... Institute of Electrical and Electronics Engineers I/O... Input/Output LED... Light Emitting Diode LFM... Linear Feet per Minute LPC... Low Pin Count N/A... Not Applicable or Not Available NC... Not Connected NMI... Non Maskable Interrupt PC-AT... Personal Computer-Advanced Technology PCH... Platform Controller Hub PCI... Peripheral Component Interconnect PCI-X... PCI Extended PICMG... PCI Industrial Computer Manufacturers Group PIC... Programmable Interrupt Controller PIT... Periodic Interrupt Timer PMC... PCI Mezzanine Card POST... Power-on Self Test PRST... Push Button Reset RoHS... Restriction of Hazardous Substances RST... Reset RTC... Real Time Clock RTM... Rear Transition Module or Transition Module SATA... Serial ATA SMBus... System Management Bus SMI... System Management Interrupt SMM... System Management Mode USB... Universal Serial Bus VITA... VMEbus International Trade Association VME... Versa Module Europe VXS... VME Switched Serial XMC... Switched Mezzanine Card VX 91x/01x iii

4 REVISION HISTORY Revision Summary of Changes Date 01 First Release June Updated current figures in Section A.5 Removed all references to DDR ECC DRAM as DDR ECC DRAM can be supported for all variants including extended temperature Reduced the bottom side cover operating ambient temperature, 55 C to 50 C Minor formatting updates September Updated Section and Section 7.3 to remove references to 3x display support Updated Figure 2-1 to include x8 PCIe for SW7-2 and SW8-2 Updated Hexadecimal notation throughout and updated the related Conventions notes Minor formatting updates November 2012 iv VX 91x/01x

5 TABLE OF CONTENTS 1 INTRODUCTION General Standard and Extended Temperature Variants - Overview The VX 91x/01x Main Features Central Processor Cache Memories Chipset PCI Express Ports PCI Busses DRAM EPROM VME Interface EIDE Controller Serial ATA Controllers USB PMC/XMC Interfaces PMC Expansion Carrier Interface Ethernet Controllers Graphics Controller Serial Communications Keyboard and Mouse Real Time Clock (RTC) Other Interfaces I/O Configuration Options On-board Mass Storage Options Extended Temperature Options Compliance to RoHS 2002/95/EC INSTALLATION General Unpacking and Inspection Default Switch Settings Front Panel Indicators and Controls Run LED (R) Green POST LED (P) Yellow Ethernet Speed LEDs (SPD) Yellow Ethernet Link/Activity LEDs (ACT) Green SATA Disk Activity LED (S) Orange User LED (U) Red Reset Pushbutton Battery Installation/Replacement Clearing the CMOS RAM Installation of CompactFlash Modules Installation of On-Board Mass Storage AD 110/002-wz Mass Storage Kit Installation (N and E Variants) AD 110/002-wzRx Mass Storage Kit Installation (RA variants) VX 91x/01x v

6 2.9 Installing or Removing a PMC or XMC Module V(I/O) Selection for PMC Modules PCI Bus Mode Selection for PMC Modules XMC PCIe Lane Width Installation Board Installation and Removal Installation Removing the Board SOFTWARE INSTALLATION Starting up for the First Time Bootloading from CD-ROM or Floppy Disk Installing Microsoft Windows Operating Systems Installing RedHat Linux MASS STORAGE INTERFACES Serial ATA Interfaces ETHERNET INTERFACES Ethernet Channel Ethernet Channel Ethernet Channels 2 and VME/VXS INTERFACE VME Bus Interface Features VME Reset VXS Interface OTHER INTERFACES Serial Ports BIOS Serial Console BIOS Serial Console Port Serial I/O Configuration Register RS485 Termination Keyboard and Mouse Ports Graphics (VGA) Controller Real-Time Clock Universal Serial Bus (USB) Power On Self Test LED/Speaker FLASH EPROM AND DRAM Flash EPROM DRAM vi VX 91x/01x

7 9 ADDITIONAL LOCAL I/O FUNCTIONS Onboard Status & Control Registers Status & Control Register Status & Control Register Status & Control Register Watchdog Timer Watchdog Status & Control Register Status & Control Register Status and Control Register Status and Control Register Long Duration Timer / Periodic Interrupt Timer Long Duration Timer / Periodic Interrupt Timer Low Byte Long Duration Timer / Periodic Interrupt Timer Mid-low Byte Long Duration Timer Mid-high Byte Long Duration Timer High Byte LDT / PIT Status and Control Register Programming the LDT/PIT BIOS Entering the BIOS The BIOS Startup Sequence Boot device selection The Setup Boot Menu Normal Advanced One-time Boot Override PXE Network Boot PCI Bus Resource Management PCI Express Ports PCI Resource Allocation PCI Device IDs Tsi148 Outbound Image Allocation Tsi148 Inbound Image Allocation VME Reserved Memory Data Structure BIOS Defaults The Recovery BIOS VXS PCIe Routing VXS PCIe Non-Transparent Bridge Setup Outbound Windows Inbound Windows NT Bridge Address Translation SYSTEM MANAGEMENT Thermal Management Adaptive Thermal Monitor (ATM) CPU Thermal Trip Processor Speed Step Processor Thermal Status Indication VX 91x/01x vii

8 A SPECIFICATIONS... A-1 A.1 Functional Description... A-1 A.2 Environmental Specifications... A-2 A.3 Shock and Vibration Specification... A-3 A.4 MTBF Values... A-4 A.5 Dimensions (All variants)... A-5 A.6 Electrical Specification... A-6 A.7 Connectors... A-8 A.7.1 VME Interface P1... A-9 A.7.2 Auxiliary Connection P2... A-10 A.7.3 VXS Connector P0... A-11 A.7.4 Console Connector P4... A-12 A.7.5 PMC Site Connectors... A-13 A.7.6 XMC Connectors J15 and J25... A-17 A.7.7 XMC Interface J16... A-18 A.7.8 Ethernet Interface P3... A-19 B REAR TRANSITION MODULES... B-1 B.1 Introduction... B-1 B.2 RTM List... B-1 B.3 AD VP2/ B-2 B.3.1 Layout... B-2 B.3.2 Pin-out Tables... B-3 B.3.3 RTM Switch Settings... B-4 B.3.4 USB NAND Flash Module... B-5 B inch Mass Storage Drive... B-6 B.4 Header/Connector Pin-out Tables... B-7 C INTERFACE CHARACTERISTICS... C-1 C.1 Ethernet... C-1 C.2 General Purpose I/O... C-2 C.3 PMC Rear I/O... C-3 C.4 SATA... C-4 C.5 Serial Ports... C-5 C.6 USB... C-6 C.7 DVI-D Interface... C-7 C.8 Power On Self Test/Speaker... C-8 C.8.1 Electrical Characteristics... C-8 C.9 External Reset... C-9 C.9.1 Electrical Characteristics... C-9 viii VX 91x/01x

9 TABLE OF FIGURES Figure 1-1 Standard and Extended Temperature Board Variants Figure 2-1 Default Switch Settings (Solder Side) Figure 2-2 Front Panel Indicators and Controls Figure 2-3 Front Panel Pushbutton Mode Switch Figure 2-4 Battery Installation Figure 2-5 CMOS Clear Switch Figure 2-6 ME CMOS Clear Switch Figure 2-7 Installing a CompactFlash card Figure 2-8 Mass Storage Connector and Fixing Screws Figure 2-9 Disk Drive Installation Figure 2-10 AD 110/002-wzRx Installation - Stage Figure 2-11 AD 110/002-wzRx Installation Stage Figure 2-12 PMC Sites V(I/O) Jumpers Figure 2-13 PMC PCI-X Capability Switch Figure 2-14 XMC Configuration Switches Figure 2-15 PMC/XMC Module Installation Figure 6-1 VME Reset Switch Figure 6-2 VXS Enable Mode Switch Figure 7-1 Console Type Switch Figure 7-2 Console Port Select Switch Figure 7-3 RS485 Termination Switches Figure 9-1 User Switch Figure 9-2 Watchdog Configuration Switch Figure 9-3 GPIO Signal Switches Figure 10-1 Boot Mode Switch Figure 10-2 Force Optimal Defaults Switch Figure 10-3 Boot Type Switch Figure 11-1 Front Panel LED Mode Switch Figure A-1 Connector Layout Component Side... A-8 Figure A-2 Connector Layout Front Panel... A-8 Figure A-3 Console Connector P4 - Pin Map... A-12 Figure A-4 Ethernet Interface P3 - Pin Map... A-19 Figure B-1 AD VP2/027 RTM - Connectors and Switches... B-2 Figure B-2 AD VP2/027 RTM Switch Settings... B-4 Figure B-3 Location of USB NAND Flash Module and P8 connector... B-5 Figure B-4 Location of 1.8-inch Mass Storage Drive and S2 Connector... B-6 VX 91x/01x ix

10 TABLE OF TABLES Table 1-1 Processor Options Table 1-2 Processor Option Details Table 1-3 VME RTM Interfaces Table 2-1 Default Switch Setting Functions Table 7-1 Serial I/O Configuration Table 9-1 I/O Address Map Table 10-1 Interrupt Structure in PIC Mode Table 10-2 Interrupt Structure in APIC Mode Table 10-3 PCI Device Numbers Table A-1 Environmental Specifications... A-2 Table A-2 Shock and Vibration Specifications (Operating)... A-3 Table A-3 MTBF Values... A-4 Table A-4 Voltage and Current Requirements... A-6 Table A-5 Maximum Current Requirements for PMC/XMC modules... A-7 Table A-6 VME Interface P1 - Pin-out... A-9 Table A-7 Auxiliary Connector P2 - Pin-out... A-10 Table A-8 VXS Connector P0 - Pin-out... A-11 Table A-9 Console Connector P4 - Pin-out... A-12 Table A-10 PMC Connectors J11 and J21 - Pin-out... A-13 Table A-11 PMC Connectors J12 and J22 - Pin-out... A-14 Table A-12 PMC Connectors J13 and J23 - Pin-out... A-15 Table A-13 PMC Connector J14 - Pin-out... A-16 Table A-14 XMC Connector J15 and J25 - Pin-out... A-17 Table A-15 XMC Interface J16 - Pin-out... A-18 Table A-16 Ethernet Interface P3 - Pin-out... A-19 Table B-1 USB Connector - Pin-out... B-7 Table B-2 Ethernet RJ-45 Connector - Pin-out... B-7 Table B-3 DB9 Serial COM port - Pin-out... B-7 Table B-4 GPIO IDC Header - Pin-out... B-7 Table B-5 PMC I/O Connector (68-way D-Type) - Pin-out... B-8 Table B-6 DVI-D Connector - Pin-out... B-9 Table B-7 PC Speaker Header - Pin-out... B-9 Table B-8 SATA Connector - Pin-out... B-9 Table B-9 esata Connector - Pin-out... B-10 Table B-10 USB Flash Module Header - Pin-out... B-10 Table C-1 COM2 Serial Port Signals... C-5 Table C-2 DVI-D Interface Signals... C-7 Table C-3 DVI-D Signal Guidelines... C-7 Table C-4 Speaker Signals... C-8 x VX 91x/01x

11 1.1 General 1 INTRODUCTION This manual is a guide and reference handbook for engineers and system integrators who wish to use the Concurrent Technologies VX 91x/01x ultra high-performance 3 rd generation Intel Core i7 processor single board computer. The board has been designed for high-speed multiprocessing applications using a PC-AT architecture operating in a VME or VXS Bus environment. The VX 91x/01x board is available in several different variants which differ by the processor type, amount of fitted DDR3 DRAM and the rear I/O connector configuration. The processor type options are listed in Table 1-1. Processor Board Variant 2.1 GHz 4-core Intel Core i7-3612qe VX 915/ GHz 2-core Intel Core i7-3555le VX 913/012 Table 1-1 Processor Options The board is currently available as standard temperature, extended temperature and ruggedized Air-Cooled (RA-Series) variants; an overview of the first two types is shown in Figure 1-1. Ruggedized Air-Cooled variants support the same functionality except for no support for an on board battery for the real time clock and some restrictions on the types of PMC/XMC modules that can be fitted. Ruggedized conduction-cooled versions are planned for the future. Refer to Section A.2 for variant temperature ranges and selection and Section A.3 for the shock and vibration specifications. Further details of other board options are given in Section 1.3. References to the board in this document will use the name VX 91x/01x unless they apply only to a specific variant, in which case the full name will be used. Configuration options (e.g. memory size, I/O type) are specified by a coded suffix appended to the board name; for configuration options please contact your distributor or Concurrent Technologies directly. Further details of the I/O configuration options are given in Section 1.4. The information contained in this manual has been written to provide the information necessary to configure, install and use the VX 91x/01x as part of a system. Familiarity with VME or VXS bus and PC-AT bus architectures and features is assumed. VX 91x/01x 1-1

12 INTRODUCTION 1.2 Standard and Extended Temperature Variants - Overview 1 x RS232 DVI-D DVI-I 2 x USB x Ethernet 10/100/1000Mbps PMC/XMC Interface 1 PMC/XMC Interface 2 CF TM DRAM DDR3 PCI-X 100 PCI-X 100 SATA to EIDE 3rd Gen Intel Core CPU XMC x8 or x4 + x4 x8 or x4 + x4 XMC SATA Super I/O Board Logic Mobile Intel QM77 Express Chipset x2 Intel 82580EB Quad x8 PCIe Switch +DMA +NT x4 + x4 MUX Optional Pn6 Rear I/O x8 x4 x2 PCIe-to- PCI-X Bridge PCIe-to- PCI-X Bridge IDT Tsi148 SATA x8 or x4 + x4 1 x RS232/ RS422/ RS485 (P2) 4 x GPIO (P2) DVI-D Speaker 2 x (P2) (P2) USB 2 x SATA (P2) (P2) 2 x USB (P0) 2 x 1000Mbps 1 x Ethernet SerDes 10/100/ x SATA VITA 41.6 Mbps (P0) (P0) (P0) VXS VITA 41.4 (P0) Pn4 Rear I/O VITA 35 (P2) VME Figure 1-1 Standard and Extended Temperature Board Variants 1-2 VX 91x/01x

13 1.3 The VX 91x/01x Main Features INTRODUCTION The VX 91x/01x is a member of the Concurrent Technologies range of single board computers for the VME and VXS bus architectures. It has been designed as a powerful single board computer based upon the 3 rd generation Intel Core i7 processors, the Mobile Intel QM77 Express chipset Platform Controller Hub (PCH), an Intel 82580EB quad channel Gigabit Ethernet controller and a PCI-to-VME bus bridge chip. It also provides two IEEE PMC (with XMC) interfaces, optional on-board mass storage and interfaces for standard PC-AT based peripherals Central Processor A summary of the processor options on the VX 91/01x is shown in Table 1-2. Base Frequency (GHz) Turbo Frequency (GHz) Intel Hyper Threading (All Cores) Intel Turbo Boost (All Cores) Processor Cores Voltage i7-3612qe Yes Yes Standard i7-3555le Yes Yes Low Table 1-2 Processor Option Details The Intel Core i7 processors are upwardly code-compatible with the other members of the x86 family of microprocessors. They have in-built floating point coprocessors for compatibility with 486 and 386/387 designs. The Intel Core i7 processors also support Intel 64 Technology (64-bit computing) Cache Memories The Level 1, Level 2 and Last Level caches are implemented on the processor die for maximum performance. Each of the execution cores has its own Level 1 and Level 2 caches and they share a common Last Level cache. The Level 1 cache is organized as 32 Kbytes of instruction cache and 32 Kbytes of data cache. The Level 2 cache is organized as a 256 Kbyte cache and stores both instructions and data. The i7-3612qe has 6 Mbytes and the i7-3555le has 4 Mbytes of Last Level cache which stores both instructions and data Chipset The processor contains an integrated graphics controller and memory controller to provide direct connection between the processor and DDR3 DRAM memory. The DDR3 DRAM interface operates up to 1600 MT/s in dual channel mode. Each channel is 72 bits wide and the memory path is therefore 144 bits wide. Up to 16 Gbytes of memory can be supported. The maximum memory bandwidth is 25 Gbytes/s. The integrated HD4000 Graphics controller contains an updated Intel seventh generation graphics core. The graphics memory is shared with the system DDR3 DRAM memory. The graphics core supports Intel Dynamic Video Memory Technology, Intel Graphics Performance Modulation Technology, Intel Smart 2D Display Technology and Intel Clear Video HD Technology. There is one analog port and three digital ports. These ports are supported via the Intel Flexible Display Interface (FDI) connected to the QM77 PCH. The VX 91x/01x provides the full dual x4 FDI interface for maximum video performance. The main function of the QM77 PCH is to provide a communication link between the processor/memory and the various peripheral interfaces, namely; USB, SATA, LPC and PCI Express. This communication link is called the Direct Media Interface (DMI) and provides a maximum bandwidth of 2 Gbytes/s in each direction, i.e. a total maximum bandwidth of 4 Gbytes. VX 91x/01x 1-3

14 INTRODUCTION PCI Express Ports The Core i7 processor has a 16-lane PCIe interface which is bifurcated into two 8-lane ports. One 8-lane port is connected directly to XMC site 2. The second 8-lane port connects to an IDT PCIe Packet switch which provides a further 16 PCIe lanes, configured as an 8-lane port to XMC site 1 and two 4-lane ports which connect to the VXS P0 connector VITA 41.4 interfaces. The 8-lane ports can alternatively operate as 4-, 2- or 1-lane ports and the 4-lane ports can alternatively operate as 2- or 1-lane ports. Both XMC interfaces can be bifurcated further to support two 4-lane ports. The PCH PCIe interfaces are configured as one 4-lane and two 2-lane ports. The 4-lane port connects to a PCIe-to-PCI bridge which provides the PMC Expansion interface. One 2-lane port connects to the quad Gigabit Ethernet controller. The other 2-lane port connects to a separate PCIe-to-PCI-X bridge which in turn connects to the VME bus bridge. All PCIe interfaces support both Gen1 and Gen2 transfer rates, except those that connect to PCIeto-PCI bridge devices, which operate only at Gen PCI Busses There are two on-board PCI busses provided by separate PCIe-to-PCI-X/PCI bridges. One bus connects to an IDT Tsi148 VME to-pci-x bridge and operates in PCI-X mode at 66 MHz. The bus other connects to both PMC sites and supports both PCI and PCI-X bus modes at a range of bus clock speeds DRAM The DRAM controller within the processor supports dual DDR MT/s memory channels with ECC data protection. These provide a maximum memory transfer bandwidth of 25 Gbytes/s. The board can be fitted with 8 or 16 Gbytes of soldered on-board memory EPROM The board contains an 8 Mbyte SPI Flash device for the BIOS code, fixed data and factory test software VME Interface The VME bus interface is provided by an IDT Tsi148 VME-to-PCI-X Bridge. The interface will operate in any VME slot. The VME interface is 32/64-bits wide. All modes of access and cycle types are supported, including 2eSST and 2eVME. The board can act as system controller when in the first VME Bus slot. The VME P2 connector is normally a 160-way type which supports 64 PMC I/O signals on rows A and C, and various peripheral interfaces on rows Z and D. There is a build option to fit a 96-way connector which isolates rows Z and D, and hence does not support the various peripheral interfaces. Contact your sales representative for ordering information for variants with 96-way P2 connector EIDE Controller The VX 91x/01x has one EIDE interface which connects to a CompactFlash site. The EIDE interface is implemented with a SATA to EIDE device Serial ATA Controllers The VX 91x/01x has two SATA600 interfaces which are available from the VXS P0 connector and three SATA300 interfaces, two of which are available from the rear P2 connector and the other is available as an on board connection for a 2.5-inch SATA hard disk or solid state disk drive. 1-4 VX 91x/01x

15 USB INTRODUCTION Six USB 2.0 channels are provided by the board - two via the front panel shared console connector, two via the VXS P0 connector and two via the P2 connector. All six USB channels support USB 1.1 (1.5 and 12 Mbps) and USB 2.0 (480 Mbps) operation. A splitter cable (part number CB 60D/125-00) is required to access the USB interfaces on the front panel shared console connector PMC/XMC Interfaces Two PMC interfaces which support single width PMC modules complying with the IEEE standard are provided. Both PMC sites have a 32/64-bit 33/66 MHz PCI or 66/100 MHz PCI-X bus interface, and support 3.3V and 5V signaling. They also have an XMC connector with an 8-lane PCIe port. Both 8-lane PCIe ports can be individually configured as dual 4-lane PCIe ports. The PMC interfaces will also accept dual function and Processor PMC modules. The latter will operate only in non-monarch mode. PMC/XMC site 1 supports 64 PMC I/O signals via P2, these are routed as 32 differential pairs. There is an XMC I/O build option for this site. If Pn6 is fitted a x8 or dual x4 fabric interface can be connected between Pn6 and VXS P0 connector. Active multiplexers select either the PCIe switch or XMC Pn6 to connect to the VXS P0 VITA 41 fabric interfaces. The active multiplexers contain repeaters that support up to 6.25 Gbps signal rates. Contact your sales representative for ordering information for variants with the Pn6 connector PMC Expansion Carrier Interface The VX 91x/01x supports the AD CR3/PMC PMC Expansion Carrier board. The carrier board supports two single width PMC modules complying with the IEEE standard, in a second backplane slot adjacent to the VX 91x/01x. Using the AD CR3/PMC, one PMC site is occupied on the VX 91x/01x, and the two additional sites on the carrier board support only 3.3V PCI signaling environments at 33 or 66 MHz Ethernet Controllers A single Intel 82580EB Gigabit Ethernet controller is used to provide four high-performance PCIeto-Gigabit Ethernet interfaces. Two interfaces are configured for 1000Base-BX (SerDes) and hence only support 1000 Mbps operation. These interfaces are connected to VXS P0 connector for supporting VITA 41.6 backplane networking. The other two interfaces are configured for 1000Base-T, but also support 100Base-TX and 10Base-T. One interface is accessed via a front panel RJ45 connector and the other via the VXS P0 connector Graphics Controller The VX 91x/01x provides graphics using the integrated HD4000 2D and 3D graphics controller built in to the Core i7 processor. It provides up to two display pipes which allow the simultaneous display of two different images on separate display monitors. This device shares the main memory and offers resolutions up to 1920 x 75 Hz with 32-bit color support. The VX 91x/01x supports three digital (DVI) and one analog video interfaces. One digital interface is accessed via the P2 connector and the remaining three video interfaces are accessed via the front panel shared console connector. A splitter cable, part number CB 60D/125-00, is required to access the interfaces on the front panel shared console connector. This cable is supplied with a DVI-I-to-VGA D15 adaptor. VX 91x/01x 1-5

16 INTRODUCTION Serial Communications The VX 91x/01x provides two serial data communication ports. These are implemented by the SCH3114 SuperI/O controller. The COM1 RS232 serial interface is available via the front panel shared console connector. The full set of modem control signals is provided. A splitter cable, part number CB 60D/125-00, is required to access the interface on the front panel shared console connector. The COM2 RS232/422/485 serial interface is available via the P2 connector. The full set of modem control signals are provided in RS232 mode Keyboard and Mouse The VX 91x/01x supports PS/2 type keyboard and mouse interfaces though these are not connected externally. They are provided for operating systems that require them to be present even if they are not used. The VX 91x/01x supports USB keyboard and mouse. These devices may either be connected to any of the USB ports supported by the VX 91x/01x or the RTM, or to the front panel shared console connector Real Time Clock (RTC) A battery backed RTC device provides PC-AT clock, calendar and configuration RAM functions. The ruggedized variants do not provide an on-board battery holder. The clock and configuration RAM functions can be maintained from an external supply for battery free operation if required Other Interfaces The VX 91x/01x has 4 TTL compatible I/O pins accessible via P2 which are available for user defined I/O. 1-6 VX 91x/01x

17 1.4 I/O Configuration Options INTRODUCTION The VX 91x/01x can be supplied in various hard-wired configurations to support different combinations of rear I/O. In particular, there are two options available with or without the VXS P0 connector fitted. Not fitting P0 results in the following rear access interfaces being lost: dual Gigabit SerDes backplane networking, two ports x4-lane PCIe data plane, 1000Base-T Ethernet interface and two SATA600 interfaces. Note that additional interfaces are available on the P2 connector. With a 96-way P2 connector, only PMC 1 rear I/O is supported via P2. Each board is typically used with an appropriate Rear Transition Module (RTM) to provide connections behind the backplane, and the standard options are described in Appendix B. Table 1-3 indicates the interfaces provided by each of these RTMs. The RTMs must be ordered in addition to the VX 91x/01x board. VME P2 Connector pins VXS P0 Connector SATA600 Gigabit Ethernet RTM AD VP2/ bit 2 * AD VP2/027-1w AD VP2/027-2w bit 2 * AD VP2/ AD VP2/ bit 2 * AD VP2/027-5w AD VP2/027-6w AD VP2/ bit 2 * Table 1-3 VME RTM Interfaces Note that all RTMs are fitted with 160-way P2 connectors as many of the I/O interfaces are connected via rows D and Z of the VX 91x/01x P2 connector. Some configurations of the VX 91x/01x also use the P0 connector to provide some of the I/O interfaces. In these cases, the appropriate backplane (typically for VXS) will be required to connect the RTMs. * SATA300 and esata300 ports are user-selectable and a maximum of two ports may be selected (e.g. 2 x SATA or 2 x esata or 1 x SATA and 1 x esata). The 1.8-inch SATA drive uses one of these user-selectable ports. the RTM variant code w = 1 or 2 selects either a 1.8-inch hard-disk drive or solid-state drive. The -30 and -70 variants include the mechanical assembly to allow the end-user to fit a 1.8-inch drive. RTMs with a P0 connector support the AD 235/001 USB Flash Drive module. DVI-D USB USB FlashDrive module PMC1 Rear I/O General Purpose I/O Serial Port COM 2 esata/sata Inch SATA Drive VX 91x/01x 1-7

18 INTRODUCTION 1.5 On-board Mass Storage Options Additional mass storage option kits are available for the VX 91x/01x: 2.5-inch SATA hard disk drive (Non-ruggedized variants only) 2.5-inch SATA solid-state drive NOTE: The mass storage option kits utilize one of the PMC site areas. It is not possible to fit both a mass storage option kit and a PMC module to the same site simultaneously. 1-8 VX 91x/01x

19 1.6 Extended Temperature Options INTRODUCTION All variants of the board are qualified for the standard operating and storage temperature ranges indicated in Section A.2. Some variants of the board are available which offer a wider range of operating and storage temperatures, but certain board features are no longer available with these variants, for example not all processor types are supported. In particular the option for on-board mass storage using a 2.5-inch rotating media hard disk drive is not supported for the extended temperature specifications. Consult your distributor or Concurrent Technologies directly for details of the extended temperature options. NOTE: A bottom side cover should not be fitted if the operating ambient temperature will exceed 50 C. This restriction is necessary to prevent overheating of some devices on the bottom side of the board. VX 91x/01x 1-9

20 INTRODUCTION 1.7 Compliance to RoHS 2002/95/EC This product is offered in a form which complies with the RoHS 2002/95/EC directive, including any technology-specific exemptions where applicable. The European Union RoHS 2002/95/EC directive restricts the use of six materials in electronic components and assemblies. Specifically, these materials are Lead (Pb), Mercury (Hg), Cadmium (Cd), Hexavalent Chromium (Cr VI), Polybrominated Biphenyls (PBB) and Polybrominated Diphenyl Ethers (PBDE). Concurrent Technologies is committed to compliance to the RoHS directive VX 91x/01x

21 2.1 General 2 INSTALLATION This chapter contains general information on unpacking and inspecting the VX 91x/01x after shipment, and information on how to configure board options and install the board into a VME/VXS chassis. CAUTION: It is strongly advised that an earthing strap should be worn at all times when handling the VX 91x/01x and its associated components in order to prevent damage to the board as a result of electrostatic discharge. CAUTION: Care should be taken when handling the board as the heatsink and some components will be hot during and after use. The list below outlines the steps necessary to configure and install the board. Each entry in the list refers to a section in this chapter which will provide more details of that stage of the procedure. It is recommended that the board is prepared for installation by following this sequence: Unpack the board - see Section 2.2. Locate the board indicators and switches and check that the settings match the required operating mode - see Sections 2.3 and 2.4. Fit the battery if required - see Section 2.5. Fit a CompactFlash module if required - see Section 2.7. Fit any optional mass storage modules - see Section 2.8. Fit a PMC/XMC module if required - see Section Install the board - see Section CAUTION: It is strongly recommended that the user reads all the sections in this chapter before installing the board in a VME backplane, or before fitting a PMC/XMC module. In particular, additional cautionary notes will highlight areas needing special consideration. VX 91x/01x 2-1

22 INSTALLATION 2.2 Unpacking and Inspection A thorough inspection of the package and contents should be carried out immediately after the board is delivered, to check for any damage caused in transit. CAUTION: If the external packaging is damaged or water-stained, the carrier s agent must be present when the board is unpacked. Once unpacked, the board should be inspected carefully for physical damage such as loose components. Should the board be damaged, notify Concurrent Technologies or its authorized agent immediately. 2-2 VX 91x/01x

23 2.3 Default Switch Settings INSTALLATION SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW2 SW6 ON OFF User - 0 Boot Mode - BIOS Console Port - COM2 Console Type - VGA ON OFF ME CMOS Clear - Disabled CMOS Clear - Disabled Force Optimal Defaults - Disabled Boot Type - Normal SW3 SW7 ON OFF Front Panel P button Mode - Reset RFU VME Reset - Disabled Front Panel LED Mode - User ON OFF RFU PMC PCI-X Capability - Auto XMC 2 Configuration - x8 PCIe PMC V(I/O) - 3.3V SW4 SW8 ON OFF VXS Enable Mode - Auto RFU RFU Watchdog - Disabled OFF ON RFU XMC 1 Configuration - x8 PCIe TxD Termination - Disabled RxD Termination - Disabled SW5 ON OFF GPIO3 Signal - GPIO GPIO2 Signal - GPIO GPIO1 Signal - GPIO GPIO0 Signal - GPIO Figure 2-1 Default Switch Settings (Solder Side) VX 91x/01x 2-3

24 INSTALLATION Switch Default Function Default Position Section Reference SW2-4 User 0/1 OFF Section 9.2 SW2-3 Boot Mode - BIOS OFF Section 10.1 SW2-2 Console Port COM 2 OFF Section SW2-1 Console Type - VGA OFF Section SW3-4 Front Panel Pushbutton Mode Reset OFF Section SW3-3 RFU OFF N/A SW3-2 VME Reset Disabled OFF Section SW3-1 Front Panel LED Mode User OFF Section SW4-4 VXS Enable Mode Auto OFF Section 6.2 SW4-3 RFU OFF N/A SW4-2 RFU OFF N/A SW4-1 Watchdog Disabled OFF Section 9.5 SW5-4 GPIO3 Signal - GPIO OFF Section 9.6 SW5-3 GPIO2 Signal GPIO OFF Section 9.6 SW5-2 GPIO1 Signal GPIO OFF Section 9.6 SW5-1 GPIO0 Signal - GPIO OFF Section 9.6 SW6-4 ME CMOS Clear Disabled OFF Section 2.6 SW6-3 CMOS Clear Disabled OFF Section 2.6 SW6-2 Force Optimal Defaults - Disabled OFF Section 10.5 SW6-1 Boot Type Normal OFF Section 10.6 SW7-4 RFU OFF N/A SW7-3 PMC PCI-X Capability Auto OFF Section SW7-2 XMC 2 Configuration x8 OFF Section SW7-1 PMC V(I/O) 3.3V ON Section SW8-1 RFU OFF N/A SW8-2 XMC 1 Configuration x8 OFF Section SW8-3 TxD Termination Disabled OFF Section SW8-4 RxD Termination - Disabled OFF Section Table 2-1 Default Switch Setting Functions 2-4 VX 91x/01x

25 2.4 Front Panel Indicators and Controls INSTALLATION LEDs are provided for development and debug purposes. When installing or removing the board for the first time or when checking its operation, it can be very useful to note the behavior of the LEDs on the front panel. Figure 2-2 shows the location of the LEDs, and their purpose is outlined below. Front Ethernet Link/Activity Speed Reset Pushbutton Figure Run LED (R) Green POST SATA User Rear Ethernet Link/Activity Rear Ethernet Speed Run Front Panel Indicators and Controls The Run LED indicates that activity is occurring on the internal LPC bus, to quickly assess how active the bus is POST LED (P) Yellow The POST LED is used to indicate that a power on self test has failed. This LED will also flash when outputting sound on the speaker interface Ethernet Speed LEDs (SPD) Yellow These LEDs indicate the operating speed of the Ethernet interfaces, as follows: Off = 10 Mbps Steady On = 100 Mbps Flashing = 1000 Mbps Ethernet Link/Activity LEDs (ACT) Green These LEDs light when connection has been made on the Ethernet interfaces. They will flash to indicate link activity SATA Disk Activity LED (S) Orange This LED lights when there is activity on any of the SATA interfaces, including accesses to the CompactFlash via the SATA-to-EIDE bridge User LED (U) Red This LED is available for use by user software. It is manipulated via an I/O register. Alternatively, the User LED may be configured to light when the CPU reaches its maximum specified operating temperature. In either mode, the User LED will flash rapidly if the CPU Thermal Trip activates. See Section for further details. VX 91x/01x 2-5

26 INSTALLATION Reset Pushbutton This pushbutton may be configured via SW3-4 (Front Panel Pushbutton Mode switch) to perform one of two functions: 1. A board and optionally a system reset. 2. A local Non-Maskable Interrupt (NMI). When the Front Panel Pushbutton Mode switch is in the NMI position (SW3-4 ON) operating the pushbutton causes an NMI to the local CPU. The source of the NMI can be determined by reading a Status & Control Register, as detailed in Section 9.4. When the Front Panel Pushbutton Mode switch is in the Reset position (SW3-4 OFF), operating the pushbutton causes a reset locally on the board. Optionally the system can be reset via the VME backplane SYSRESET# signal, as detailed in Section Both the reset and NMI functions of the pushbutton can be disabled by a Status & Control Register, as detailed in Section 9.4. ON 4 SW3-4 - Front Panel Pushbutton Mode OFF - Reset ON - NMI OFF Figure 2-3 Front Panel Pushbutton Mode Switch When the VX 91x/01x has entered a chipset sleep state, the front panel pushbutton acts as a wake-up request. Under these circumstances, a system reset is not generated. If a system reset is required then the pushbutton must be activated again, once the board has exited the sleep state. 2-6 VX 91x/01x

27 2.5 Battery Installation/Replacement INSTALLATION The on-board Real Time Clock and CMOS memory used by the BIOS firmware and chipset Management Engine are powered by a 3V Lithium battery when the board is powered off. It is advisable, though not essential, for the battery to be fitted prior to using the board as shown in Figure 2-4. One battery is supplied with the board, but it is not normally fitted when the board is shipped. NOTE: The battery holder is not fitted for ruggedized variants. To maintain the real time clock in the absence of the backplane 5V rail, an external 5V source has to be provided via the VME Bus VCC_STANDBY supply. Top is marked positive Bottom is negative + BR2032 slide in or out Figure 2-4 Battery Installation The battery should be replaced when the voltage falls below 2.5V. Depending on how the board is operated and stored, battery life should be in excess of 3 years. Battery life expectancy will fall if the battery is subjected to long periods at temperatures of 45 C or above, or if the battery is fitted to a board that is stored in its conductive bag even at room temperature. Operation without a battery is possible by connecting the VME Bus VCC_STANDBY supply to an external 5V source. The contents of the CMOS memory will be maintained and the Real Time Clock will continue to function as long as the VCC_STANDBY supply is maintained to the board. NOTE: When replacing the board it is not necessary to remove power from the VCC_STANDBY supply. CAUTION: When replacing the battery, anti-static precautions must be observed. Battery Never dispose of batteries in a fire. Always dispose of batteries according to local regulations. Please recycle when possible. Do not dispose of batteries as household waste. Always replace battery with manufacturer s recommended type. VX 91x/01x 2-7

28 INSTALLATION 2.6 Clearing the CMOS RAM If the BIOS Setup screens have been used to set up the board for an invalid configuration, or in other fault conditions it may be necessary to reset all board settings to the factory default configuration. Some settings used by the BIOS and chipset management engine (ME) are held in battery backed CMOS memory, other BIOS settings are held in Flash memory. To clear the CMOS RAM to a known state, fit the battery and with the main power rails off, then switch SW6-3 (CMOS Clear switch) ON, then OFF. Figure 2-5 shows the location of this switch. ON SW6-3 - CMOS Clear OFF - Disabled 1 ON - Enabled OFF Figure 2-5 CMOS Clear Switch To clear the chipset management firmware CMOS settings, use the same procedure as above, but use SW6-4 (ME CMOS Clear switch) instead, as shown in Figure 2-6. ON SW6-4 - ME CMOS Clear OFF - Disabled 1 ON - Enabled OFF Figure 2-6 ME CMOS Clear Switch NOTE: An alternative method of clearing both CMOS functions is to remove the battery for at least 30 seconds. To return the BIOS settings to the factory configured optimal defaults, remove power from the board and set SW6-2 (Force Optimal Defaults) to the Factory Settings position (SW6-2 ON). Power on the board and wait until output appears on the console device, remove power and return SW6-2 back to the User Settings Position (SW6-2 OFF). Section 10.5 details SW VX 91x/01x

29 2.7 Installation of CompactFlash Modules INSTALLATION The VX 91x/01x has the option to have a CompactFlash card installed the site and associated components are shown in Figure 2-7. CompactFlash Site Retaining Screw Slide to Fit Retaining Bracket Retaining Screw Figure 2-7 To install a CompactFlash card: Installing a CompactFlash card 1. Remove the retaining bracket (if fitted) by undoing the two fixing screws and lifting the bracket clear of the board. 2. Orientate the card so that the connector end is facing the socket and the label side is away from the board. 3. Slide the CompactFlash card between the guides until it locks into the connector. 4. Refit the retaining bracket (if required) by placing it behind and over the card and screwing it into place. NOTE: The retaining bracket is only suitable for Type I modules. Removal of a CompactFlash card is the reversal of the above procedure. NOTE: If the board is likely to be subjected to mechanical vibration consider applying a suitable thread lock compound to the screw thread. VX 91x/01x 2-9

30 INSTALLATION 2.8 Installation of On-Board Mass Storage The mass storage option is fitted to connector pads and is secured via screws and spacers using the four HDD mounting holes and two adaptor mounting holes as shown in Figure 2-8 below. Outline of Mass Storage Option Mass Storage Option Connector Figure 2-8 Mass Storage Connector and Fixing Screws 2-10 VX 91x/01x

31 2.8.1 AD 110/002-wz Mass Storage Kit Installation (N and E Variants) The option kit comprises: A 2.5-inch SATA disk drive (dependent upon variant ordered) An adaptor assembly Four M3 x 4 mm screws Four M3 x 5 mm pillars Two M2 x 6 mm screws INSTALLATION The adaptor assembly has a 20-way connector on one side and a 22-way SATA connector on the other side. The 22-way SATA connector plugs into the disk drive and the 20-way connector attaches to the main board. 1. Screw the four pillars into the bottom of the disk drive until the pillar and the disk drive meet, i.e. there should be no gap between them. Do not over tighten the pillars. 2. Remove PMC site polarizing key if fitted in the 3.3V V(I/O) position. 3. Plug the 22-way SATA connector into the disk drive as shown in Figure note the orientation. 22-way SATA Connector Power Segment Data Segment 20-way Connector S1 or S2 Pads Figure 2-9 Disk Drive Installation 4. Fix the disk drive into position, placing the four M3 screws provided through the appropriate holes in the host board and screwing them into the bottom of the pillars. Do not over tighten the screws. 5. Secure the adaptor to the base board using the two M2 screws provided. Do not over tighten the screws. NOTE: If the board is likely to be subjected to mechanical vibration consider applying a suitable thread lock compound to the screw thread. VX 91x/01x 2-11

32 INSTALLATION AD 110/002-wzRx Mass Storage Kit Installation (RA variants) This storage kit comprises: A 2.5-inch SATA SSD drive (capacity dependent upon variant) An adaptor assembly Four M3 x 4mm screws Four M3 x 5mm pillars Two M2 x 6mm screws Prior to installation of the SSD there is a spine of the heat frame, which must be removed to avoid it fouling the drive, as shown in Figure Retaining Screws Removable Spine Figure 2-10 AD 110/002-wzRx Installation - Stage 1 Once the heat frame spine has been removed, the SSD can be fitted using the same procedure detailed in Section The orientation and positioning of the drive and adaptor assembly are shown in Figure VX 91x/01x

33 INSTALLATION SSD Adapter Assembly M3 5mm Pillar M3 4mm Screw Figure 2-11 AD 110/002-wzRx Installation Stage 2 NOTE: If the board is likely to be subjected to mechanical vibration consider applying a suitable thread lock compound to the screw thread. VX 91x/01x 2-13

34 INSTALLATION 2.9 Installing or Removing a PMC or XMC Module V(I/O) Selection for PMC Modules The VX 91x/01x allows the selection of 3.3V or 5V V(I/O) to both PMC sites by use of SW7-1 (PMC V(I/O)). Before installing a PMC module check that the VX 91x/01x board PMC V(I/O) is configured to match the requirements and/or configuration of the PMC modules being used. See Figure The PMC sites have provision for fitting a polarizing key for 3.3V V(I/O) or 5V V(I/O) PMC modules. Only one key must be fitted on each site and both keys must be in the same position, corresponding with the setting of SW7-1. ON SW7-1 - PMC V(I/O) OFF - 5V 1 ON - 3.3V OFF Figure 2-12 PMC Sites V(I/O) Jumpers CAUTION: Ensure that the switch and polarizing keys are configured correctly for the PMC cards being used. Failure to do so may result in damage to the VX 91x/01x and/or to the PMC cards VX 91x/01x

35 2.9.2 PCI Bus Mode Selection for PMC Modules INSTALLATION The 64-bit PCI bus connecting to both PMC sites can operate at various bus speeds and modes: 33 MHz PCI, 66 MHz PCI, 66 MHz PCI-X and 100 MHz PCI-X. The speed of the bus is determined by the type of PMC modules fitted and the mode by the setting of option switch as shown in Figure SW7-3 (PMC PCI-X Capability) should normally be in the OFF position. This allows the bus to operate at the optimum mode for the PMC modules fitted, namely PCI-X mode when PCI-X capable PMC modules are fitted, otherwise PCI mode. If SW7-3 is in the ON position, the bus will always operate in 33 MHz or 66 MHz PCI mode. ON SW7-3 - PMC PCI-X Capability OFF - Auto 1 ON - Force PCI OFF Figure 2-13 PMC PCI-X Capability Switch VX 91x/01x 2-15

36 INSTALLATION XMC PCIe Lane Width It is possible to configure each XMC site to accept dual 4-lane PCIe XMC cards by use of SW8-2 (XMC 1 Configuration switch) and SW7-2 (XMC 2 Configuration switch), as shown in Figure ON OFF SW7-2 - XMC 2 Configuration OFF - x8 PCIe ON - dual x4 PCIe OFF ON SW8-2 - XMC 1 Configuration OFF - x8 PCIe ON - dual x4 PCIe Figure 2-14 XMC Configuration Switches 2-16 VX 91x/01x

37 2.9.4 Installation INSTALLATION Figure 2-15 shows the method of installation of a PMC module on the board. Use the same approach when fitting an XMC module. For RA variants only PMC/XMC modules that are compatible with middle and rear heat transfer spines on the heat frame can be fitted. However, the middle spine on PMC/XMC site 2 can be removed as detailed in Section NOTE: The VX 91x/01x is supplied with PMC blanking plates which must be removed before a new module can be fitted. NOTE: Only PMC modules which meet the required standard for shock and vibration should be used. 1. Remove the front panel blanking plate from the appropriate PMC slot on the VX 91x/01x. 2. Check that the standoffs are attached to the PMC and then align the front of the PMC with the opening in the front panel of the VX 91x/01x. 3. Install the PMC, component side down, aligning the PMC connectors with their mating connectors on the VX 91x/01x. Press them together so that the friction from the pins holds the PMC in place. 4. Screw the PMC in place using the four mounting screws. PMC Module Front Panel 1 2 CMC Bezel 10mm Standoff 3.3 Volt Key 5 Volt Key 3 4 x M2.5 x 6mm Screws Figure 2-15 PMC/XMC Module Installation VX 91x/01x 2-17

38 INSTALLATION 2.10 Board Installation and Removal Before the board is installed in a VME/VXS chassis, check the following points: When installing a variant of the board which is fitted with a P0 connector into a backplane which does not have the corresponding socket, check to see that no strengthening bars or other tall objects are present on the backplane before inserting the board. If bars or other objects are present then verify that the P0 connector and/or the backplane will not be damaged when the board is fully seated in the slot. The system Power Supply Unit must have sufficient current capabilities. The board draws current primarily from the +5V rail, and the details are provided in Section A.6. The board can be installed in any standard VME slot. When installed in the first occupied slot the board will become the system controller. CAUTION: The high current supply requirements of these boards when operating at maximum performance mean that all the available +5V pins on the VME P1 and P2 connectors are utilized. It is therefore strongly recommended that this board is installed only in backplanes with 5-row P1 connectors and (at least) a 3-row P2 connector supplying +5V power through all the pins defined in the VME64 specifications. Failure to comply with this recommendation may result in the board malfunctioning or, in extreme cases, board or system damage Installation The board is installed and powered up as follows: 1. Ensure that system power is turned OFF (VCC_STANDBY may be left ON if used). 2. Slide the board into the designated slot, ensuring that the board fits neatly into the runners. 3. Push the board into the card-cage until the P0, P1 and P2 connectors are firmly located. Use the ejector handles to push the board home. 4. Screw the ejector handle retaining bolts into the holes in the chassis. 5. Connect the I/O cables to the connectors on the board s front panel and fix in place with the connectors retaining screws. 6. If using an RTM, install it at the rear of the backplane and connect the I/O cables. 7. Power-up the system. The following sequence of events should then occur: a. The green RUN LED and the yellow POST LED on the front panel will illuminate. b. The yellow POST LED will switch OFF. c. The green RUN LED will continue to flash. If power-up does not follow the sequence described above this will indicate that the board is not operational. NOTE: This sequence of events assumes the VX 91x/01x has Concurrent Technologies standard BIOS firmware and that the board is configured to the factory settings described in Section Removing the Board To remove the board, shut down the application and operating system software before powering down the system, disconnecting any I/O cables, unscrewing the ejector handle retaining bolts, opening the ejector handles and extracting the board. CAUTION: The VX 91x/01x is not Hot Swappable. The main system power must be OFF before attempting to install or remove the board VX 91x/01x

39 3 SOFTWARE INSTALLATION In most cases, installing operating system software on the VX 91x/01x board follows the same sequence as installing on a PC. However, there are some additional points to note. The sections below summarize the special actions required for a few common operating systems. 3.1 Starting up for the First Time Many operating systems running on the board will want to use the standard Real Time Clock hardware. To maintain the date and time settings, and several other settings recorded by the BIOS, the battery must be fitted (or VCC_STANDBY connected). When the board is first powered up, or at the first power-up after changing the battery, carry out the following steps to set up the board. 1. Fit a battery, if required, as shown in Section Ensure you correctly set the Console switches to the correct state for the console device which will be used (VGA monitor and keyboard, or serial terminal) - see Section and Section for further details. NOTE: Most operating systems which install on the target hardware will require a monitor and keyboard during installation, even if they can subsequently be reconfigured to use only a serial terminal. 3. Connect any additional modules and peripherals especially any mass storage devices. 4. Connect the console device, power the board ON and wait for the BIOS to sign on. 5. It may be necessary to enter the BIOS menus for setup options and/or to initialize the time and date. This can be achieved by pressing <F2> as soon as the keyboard Num Lock indicator comes on. Set the time and date by using the cursor keys to move around the screen and reading the help information in the right-hand screen panel. When the time and date have been set, move the cursor to any other field on the same screen, then press <F4> to exit. Press <y> to accept the changes and restart. The BIOS will then completely restart and should complete bootloading. To proceed with software installation, check that all necessary mass storage devices are connected before continuing with one of the sequences below. VX 91x/01x 3-1

40 SOFTWARE INSTALLATION 3.2 Bootloading from CD-ROM or Floppy Disk Operating systems which install on the target hardware will generally install from CD-ROM, or may require both a CD-ROM and floppy disk. Bootloading from floppy disk requires the use of a USB floppy disk drive. To bootload from USB floppy disk drive or CD-ROM, use the following procedure: 1. While the BIOS is starting, press <Esc>. 2. Wait for the pop-up boot device menu to be displayed. 3. Select the USB floppy disk drive or CD-ROM drive (as required) using the cursor keys, and then press <Enter>. 3-2 VX 91x/01x

41 3.3 Installing Microsoft Windows Operating Systems SOFTWARE INSTALLATION Installing these operating systems on the VX 91x/01x is generally very similar to installing them on a desktop PC. However, Concurrent Technologies also offers a Board Support Package on CD or DVD (part number CD WIN/BSx-x0) which provides installation and configuration information, including appropriate drivers. Please refer to your supplier for further details or to obtain this package. VX 91x/01x 3-3

42 SOFTWARE INSTALLATION 3.4 Installing RedHat Linux Installing these operating systems on the VX 91x/01x is generally very similar to installing them on a desktop PC. However, Concurrent Technologies also offers a Board Support Package on CD-ROM (CD LNX/BS1-L0) which includes VME bus drivers and additional information. Please refer to your supplier for more details or to obtain this package. NOTE: If virtualization is to be used, it may be necessary to refer to the Board Support Package for further installation instructions. 3-4 VX 91x/01x

43 The VX 91x/01x has six Serial ATA (SATA) interfaces: 4 MASS STORAGE INTERFACES Two interfaces are accessible via the rear P0 connector for connecting mass storage devices. Two interfaces are accessible via the rear P2 connector for connecting mass storage devices. Two interfaces are used to support on-board mass storage devices and one of these ports is converted to EIDE to support an on-board CompactFlash card. The order in which the BIOS firmware bootloads from these drives can be changed via the BIOS setup screen for Boot. 4.1 Serial ATA Interfaces The board provides two SATA600 interfaces which support maximum transfer rates of 600 Mbytes/s and four SATA300 interfaces which support maximum transfer rates of 300 Mbytes/s. Each interface supports connection of a single SATA device and will support a drive that has maximum transfer rates lower than that stated for the interface. The BIOS setup screens for Advanced IDE Configuration Serial ATA Port 0 etc. show what is connected to these interfaces, and allow selection of some characteristics of the drives manually. Normally the BIOS firmware will automatically determine the drive characteristics from the drives themselves. SATA 0 and SATA 1 are used to support single SATA600 drives via the optional VXS P0 connector. The SATA 0 and SATA 1 interfaces are disabled if the VXS PEN# signal is false - this signal can be forced true using the VXS Enable Mode switch, as detailed in Section 6.2. SATA 2 is used to support a CompactFlash module via a SATA-to-EIDE bridge. SATA 3 is used to support an on-board SATA300 disk drive. SATA 4 and SATA 5 are used to support single SATA300 devices via the VME P2 connector. VX 91x/01x 4-1

44 MASS STORAGE INTERFACES This page is intentionally unused. 4-2 VX 91x/01x

45 5 ETHERNET INTERFACES The VX 91x/01x is fitted with four independent Gigabit Ethernet interfaces. These are implemented with an Intel 82580EB controller which is configured as two SerDes interfaces (connected to P0 to support VITA 41.6 backplane networking) and two copper Ethernet interfaces (one accessed via P0 and the other via the front panel RJ45 connector). In this manual the Ethernet interfaces are numbered using the 82580EB port assignment convention of 0 to 3. Operating system drivers may renumber these devices to conform to their driver conventions. When the VXS P0 PEN# signal is detected as being false at power up, the Ethernet interfaces on P0 are disabled in the 82580EB controller and do not appear in the device s PCI configuration register space. In this configuration the front panel Ethernet interface is the only one enabled and appears as function 0 in the device s PCI configuration register space. The VXS PEN# signal can be forced true by using the VXS Enable Mode switch, as detailed in Section 6.2. It is possible to bootload the board through the Ethernet interfaces by setting appropriate BIOS configuration options. See Section 10.3 for more details. 5.1 Ethernet Channel 0 This port is routed to on-board magnetics, the isolated side then connects to the optional VXS P0 connector. Due to the clearance between the isolated signals and power planes on the circuit board and the VXS connector, only 50V isolation is maintained. This interface supports 1000Base-T, 100Base-TX or 10Base-T through auto-negotiation. 5.2 Ethernet Channel 1 This port connects to the front panel RJ45 connector with integrated magnetics. This interface supports 1000Base-T, 100Base-TX or 10Base-T through auto-negotiation. 5.3 Ethernet Channels 2 and 3 These Ethernet interfaces are available at the P0 connector are configured for Gigabit SerDes (1000Base-BX) only operation. These interfaces are expected to be routed on the backplane to a target device or switch slot. VX 91x/01x 5-1

46 ETHERNET INTERFACES This page is intentionally unused. 5-2 VX 91x/01x

47 6 VME/VXS INTERFACE The VX 91x/01x is fitted with an IDT Tsi148 PCI-to-VME bus bridge device together with additional support logic. This hardware implements a flexible interface to and from the VME bus with the following key characteristics. 6.1 VME Bus Interface Features The VX 91x/01x can be programmed as a VME master supporting off-board VME memory addressing accessible by any PCI bus master. The VX 91x/01x can also be programmed as a VME slave allowing other VME masters to access any PCI bus slave. This access is achieved by programming the appropriate Tsi148 device register. PCI slave registers are used for VX 91x/01x master accesses and VME slave registers for VME accesses to the VX 91x/01x. The VME interface supports A64/A32/A24/A16/MBLT64 addressing modes and D64/D32/D16/D08 (EO) data widths in both user and supervisor address space. The VME interface performs auto-syscon detect at power up to provide system controller functionality, if the board is located in the first VME slot. As system controller, the Tsi148 will arbitrate VME mastership of the bus using DEMAND request mode. The VX 91x/01x can act as an interrupt controller for any combination of VME interrupts and can be an interrupter generating either a software interrupt or any of the Tsi148 internal interrupt sources on any IRQ level. All VME interrupts are directly mapped between the Tsi148 registers and the VME bus backplane. Of the PCI INT [A:D] lines, PCI INTA is mapped into the PCI interrupt (PIRQG) on the PCH and PCI INTD is mapped to NMI. PCI INTB and PCI INTC are not used. The Tsi148 device uses the linear incrementing mode when being accessed by a PCI master. The Tsi148 supports VME mailbox interrupts. See the Tsi148 data sheet for further details. WARNING: VME bus access is allowed to the full VX 91x/01x memory map. Care must be taken to ensure that no accesses are made to areas that will corrupt the system memory or the configuration of any of the interfaces. The BIOS firmware fitted to this board includes several setup screens which allow up to 2 PCI Slave and VME Slave access windows to be configured. The configuration is retained in Flash EPROM and is programmed automatically into the Tsi148 chip when the board starts up. This allows basic access to or from the VME bus to be established without the need to write any operating software for the board, or for the Tsi148 chip. For further details, refer to the BIOS setup screens for the VME Bridge VME Bridge Outbound Images and VME Bridge Inbound Images options. The VX 91x/01x will assert the VME SYSFAIL signal after a power-on or system reset. In some cases it may be desirable to deactivate this signal early in the boot process, while in others it can be left to the operating software to do this at a later stage. The SYSFAIL signal is controlled by the Tsi148 chip. The BIOS provides a user setup option to allow this signal to be deactivated by the BIOS itself during its initialization sequence, or to simply leave it unchanged after the restart. In the latter case, SYSFAIL will remain asserted until the operating software deactivates it. The setup option is provided on the menu for VME Bridge. The Tsi148 provides VME bus error detection and reporting capabilities. VX 91x/01x 6-1

48 VME/VXS INTERFACE VME Reset The VX 91x/01x supports two backplane resets, namely SYSRESET# on P1 pin C11 and TM_RST# on P2 pin Z17. SYSRESET# is the system reset signal defined in the VME standard. The TM_RST# is a proprietary reset signal that can reset the board and optionally the system. Both signals are bi-directional, the board can either respond to or generate an asserted signal. The Tsi148 chip generates out-going SYSRESET# assertions for the following events; During initial board power-up. Under software control via the Tsi148 VCTRL register. Watchdog timer expiry reset if enabled to generate a system reset, see Section 9.5. Activation of the front panel pushbutton switch, when configured for reset generation, see Section In-coming assertion of the TM_RST# signal. The last two events are further qualified with the VME Reset switch, detailed below, and if not acting as the system controller they are also qualified with bit 1 in the Status & Control Register 2 detailed in Section 9.4. In-coming board reset requests via the SYSRESET# can be enabled/disabled by bit 3 in the Status & Control Register 2 detailed in Section 9.4. When the board is in a chipset sleep state an asserted to de-asserted transition on SYSRESET# is a chipset wake-up event. This action cannot be disabled by bit 3 in Status & Control Register 2. An out-going TM_RST# assertion occurs during any board reset and when the chipset is in a sleep state. In-coming local and system reset requests via TM_RST# can only occur when the board is not in reset or in a sleep state. SW3-2 (VME Reset switch) enables or disables both the reset action of the front panel pushbutton and the TM_RST# signal from activating the VME bus reset signal SYSRESET#. When this switch is in the Disabled position (SW3-2 OFF), the pushbutton reset and TM_RST# reset will only act locally on the board. When this switch is in the Enabled position (SW3-2 ON), both the pushbutton reset and TM_RST# reset will cause a VME bus reset via the SYSRESET# signal. Figure 6-1 shows the location and settings of the VME Reset switch. ON SW3-2 - VME Reset OFF - Disabled 1 ON - Enabled OFF Figure 6-1 VME Reset Switch 6-2 VX 91x/01x

49 6.2 VXS Interface VME/VXS INTERFACE The optional P0 connector provides the VXS VITA 41.4 and VITA 41.6 interfaces. The VX 91x/01x supports both Port A and B of VITA The two VITA 41.4 ports connect to an active 2-to-1 multiplexer via 100nF AC coupling capacitors. The multiplexers provide receive and transmit signal conditioning for signal rates up to 6.25 Gbps and route the ports to either an IDT PCIe Packet Switch or to the optional XMC I/O connector on XMC site 1 (connector P16). Routing selection is done on a per port basis with a BIOS setup option, see Section 10.7 for details. When routed to the XMC I/O connector the XMC module defines the protocol and signal speeds, both the transmit and receive signals to the XMC I/O connector use 100nF AC coupling capacitors. When routed to the PCIe Packet Switch each port is a 4-lane PCIe port with each lane supporting Gen1 (2.5 Gbps) or Gen2 (5.0 Gbps). The peak transfer rate on each transmit and receive link of a port is 1 Gbyte/s and 2 Gbytes/s, for Gen1 and Gen2 respectively. The 8-lane upstream PCIe port of the PCIe Packet Switch connects to a processor PCIe interface. The 8-lane PCIe port to XMC site 1 also connects to the PCIe Packet Switch. The PCIe Packet Switch can configure each port to be either Transparent or Non-Transparent, BIOS setup options under the VXS sub-menu can be used for port configuration, see Section 10.8 for further details. When in Non-Transparent mode, several in-coming and out-going address windows can be defined to allow other boards to access the VX 91x/01x memory or vice versa. Within the PCIe Packet Switch is a DMA Controller to support data movement between boards without utilizing the processor. VITA 41.6 defines two 1000Base-BX (SerDes) interfaces, the VX 91x/01x supports both interfaces which are connected to the 82580EB Ethernet controller. These interfaces are normally used for backplane networking and are connected to either other rack slots or a network switch slot. The VXS P0 connector PEN# signal, together with SW4-4 (VXS Enable Mode switch), is used to enable or disable the VITA 41.1, VITA 41.6, SATA 0 and SATA 1 interfaces. When SW4-4 is in the Auto position (SW4-4 OFF) the VXS PEN# signal has to be asserted (low) for the interfaces to be enabled. The PEN# signal pin on the mating backplane connector would normally be connected to signal ground. With the switch in the Force Enabled position (SW4-4 ON), the interfaces are always enabled. The disadvantage of this configuration is the additional power consumption when the P0 interfaces are not used. ON SW4-4 - VXS Enable Mode OFF - Auto 1 ON - Force Enabled OFF Figure 6-2 VXS Enable Mode Switch VX 91x/01x 6-3

50 VME/VXS INTERFACE This page is intentionally unused. 6-4 VX 91x/01x

51 7 OTHER INTERFACES Many additional standard interfaces are provided on the VX 91x/01x. These interfaces consist primarily of those found in a regular desktop or mobile PC, and are outlined below. 7.1 Serial Ports Two serial interfaces are provided. Serial port COM2 is connected via P2. Serial port COM1 is accessed via the front panel 60-way console connector. A splitter cable (part number CB 60D/125-00) is required to access this interface. The serial ports are implemented in the PC chipset used on the board, using standard style devices. The serial lines may be configured for speeds up to 115 Kbaud BIOS Serial Console With some operating systems, or in some applications, it is preferable to use a serial terminal as an operator console device for the board, in which case it will be necessary to configure the board accordingly. When configured in this mode, the BIOS firmware will re-direct its output to a COM port, and similarly will take its input from this port, rather than using the VGA screen and PC keyboard. SW2-1 (Console Type switch) allows selection of this mode. ON SW2-1 - Console Type OFF - VGA and KBD 1 ON - Serial OFF Figure 7-1 Console Type Switch The serial line speed used for the Serial Console mode may be selected from the BIOS setup screen Advanced Console Redirection. VX 91x/01x 7-1

52 OTHER INTERFACES BIOS Serial Console Port If the Console Port switch (SW2-1) is set for Serial (SW2-1 ON) to use the BIOS console, then either COM1 or COM2 can be selected by using SW2-2 (Console Port switch). ON SW2-2 - Console Port OFF - COM2 1 ON - COM1 OFF Figure 7-2 Console Port Select Switch 7-2 VX 91x/01x

53 7.1.3 Serial I/O Configuration Register OTHER INTERFACES Register Serial I/O Configuration Register Address 0x0215 Bit Access Name Description 7 RW COM2 232/485 See Table RW COM2 DUPLEX See Table RW COM2 TX CTRL Controls which signal enables the transmitter when operating in RS485/422 mode. 0 = SCH3114 SuperI/O RTS is the enable signal 1 = GPIO1 (when high) is the enable signal 4 RW COM2 SLEW See Table RFU Reserved 2 RFU Reserved 1 RFU Reserved 0 RFU Reserved This register is used to configure the serial I/O port COM2 for operation at RS232 or RS485/422 signal levels. By default the ports will power up disabled to prevent conflicts with attached devices. The BIOS configures the interfaces after power-on to the interface as determined by the setup options for Advanced Peripheral configuration. This will automatically enable the port drivers. Bit 7 Bit 6 Bit 4 Configuration Selected Interface disabled 0-1 RS232 Full Duplex mode (Standard Interface) RS485 Full Duplex, Fast Slew RS485 Full Duplex, Slow Slew RS485 Half Duplex, Fast Slew RS485 Half Duplex, Slow Slew. Table 7-1 Serial I/O Configuration In RS485 Half Duplex mode no hardware flow control is available. Slew rate is only valid in RS485 mode and slow slew rate allows operation without termination resistors at low data rates only. RS485 Full Duplex mode is for operation over two twisted pairs and can be used in RS485 and RS422 systems; Half Duplex mode is for operation over a single twisted pair and can only be used in RS485 systems. Half Duplex mode uses only the Sn_Tx/TX- and Sn_RTS/TX+ signals on P2. Transmitted data is also looped back to the receiver. The board provides termination facilities on the RS485 transmit and/or receive data lines as detailed in Section For initial configuration after power on, the BIOS when in serial console mode will choose RS232 Full Duplex when no specific configuration has been previously set up. BIOS serial console mode does not support Half Duplex modes and it is advisable not to select these modes. The user application code can then set up the required mode later. For RS485 Full and Half Duplex mode the SCH3114 SuperI/O RTS signal or GPIO1 signal control the transit enable, selection is by bit 5 of this register. The SCH3114 provides several options for controlling the RTS signal, including support for automatically enabling the transmitter whenever data is written to the transmit FIFO. There is a BIOS option to select the transmit control configuration. CAUTION: When changing the configuration of the serial ports from RS232 to RS485 (or vice versa) or setting up ports for the first time, ensure that the interfaces are disconnected to prevent any damage to connected equipment. VX 91x/01x 7-3

54 OTHER INTERFACES RS485 Termination In RS485 mode it may desirable to terminate the differential transmit and receive data signal pairs when using high transfer rates with fast slew rates. The board has switches to enable 120Ω termination on each of the differential pair, as shown in Figure 7-3. For Half Duplex mode, the RS485 transmit differential signals are used for both transmit and receive data and hence only the TxD termination switch needs to be ON to provide signal termination OFF ON SW8-4 - RxD Termination OFF - Disabled ON - 120Ω Enabled OFF ON SW8-3 - TxD Termination OFF - Disabled ON - 120Ω Enabled Figure 7-3 RS485 Termination Switches 7-4 VX 91x/01x

55 7.2 Keyboard and Mouse Ports OTHER INTERFACES The console connector provides two USB interfaces, which may be used to connect a USB keyboard and mouse. A splitter cable, part number CB 60D/125-00, is required to access these interfaces. Alternatively a USB keyboard and mouse may be connected to the USB ports provided by the RTM. VX 91x/01x 7-5

56 OTHER INTERFACES 7.3 Graphics (VGA) Controller The VX 91x/01x contains a graphics controller within the Core i7 processor and video interface drivers within the PCH. The graphics controller uses main memory for graphics RAM and supports many different modes of operation including VGA and SVGA, with resolutions up to 1920 x 1200 on the analog interface and 1600 x 1200 or 1920 x 1080 on the digital interfaces. Color depths up to 32 bits (4294 million colors) are supported. The graphics controller also provides both 2D and 3D acceleration. The analog CRT interface from the PCH and two of the digital interfaces are routed to the front panel console connector. A splitter cable, part number CB 60D/125-00, is required to access these interfaces. The splitter cable provides one DVI-I (analog and digital) and one DVI-D connector. A third digital interface is provided on the P2 connector and can be accessed via a DVI-D connector on the AD VP2/027 RTM. A maximum of two monitors can be connected via the three connectors. Each monitor can display the same or different images. NOTE: It is not recommended that two monitors are connected to the DVI-I interface as only one monitor will be recognised by the operating system. Also see Section 7.1 for information about how to enable the BIOS serial console. 7-6 VX 91x/01x

57 7.4 Real-Time Clock OTHER INTERFACES A conventional PC Real-Time Clock is included on this board, and it can be powered by an onboard Lithium battery when main power to the board is removed. Section 2.5 details how to fit or replace the battery. The clock device also provides 242 bytes of CMOS RAM, in which the BIOS keeps its setup data and other information. Alternatively the CMOS settings and Real-Time clock can be maintained in the absence of power by connecting a 5V source to the VME bus VCC_STANDBY input. VX 91x/01x 7-7

58 OTHER INTERFACES 7.5 Universal Serial Bus (USB) Six USB 2.0 interfaces are provided on the VX 91x/01x. Two channels are routed to P2, two channels are routed via VXS P0 and two are available at the front panel console connector (a splitter cable, part number CB 60D/ is required to access the front panel interfaces). All six channels can operate at 1.5, 12 or 480 Mbps. The BIOS firmware supports bootloading via all of these ports. 7-8 VX 91x/01x

59 7.6 Power On Self Test LED/Speaker OTHER INTERFACES The Power On Self Test (POST) LED is controlled via the speaker port. The POST LED replaces a PC speaker and is programmed in the same way a speaker is programmed. The board also outputs the speaker port via a high current open collector driver on the P2 connector for connection to an external speaker if required. VX 91x/01x 7-9

60 OTHER INTERFACES This page is intentionally unused VX 91x/01x

61 8.1 Flash EPROM 8 FLASH EPROM AND DRAM The VX 91x/01x is fitted with one Flash EPROM part, namely a 64 Mbit SPI Flash device. This device is soldered to the board and is programmed at the factory with BIOS and factory test firmware. This EPROM will not normally be reprogrammed by the user, but Concurrent Technologies has programming software which allows BIOS updates to be carried out in the field when necessary, perhaps to add new features. Contact Concurrent Technologies for a copy of this software and for the BIOS reprogramming information if such an update is required. Also programmed into the SPI Flash at the factory is a Recovery BIOS, which allows the board to be restarted in a basic functional mode even if the main BIOS firmware has been corrupted. See Section 10.6 for further details of this feature. 8.2 DRAM The VX 91x/01x supports a large amount of DDR DRAM. Soldered memory on board supports up to 16 Gbytes capacity with ECC protection. A part of the first 4 Gbytes of DRAM will be unavailable due to the requirements of other memory mapped resources (for example the BIOS ROM and PCIe Extended Configuration address space). The BIOS remaps this lost memory above the top of fitted DRAM, so that it remains accessible to operating systems capable of addressing more than 4 Gbytes. The DRAM can be accessed from the processor, the local PCI bus, PCIe ports and the VME backplane. VX 91x/01x 8-1

62 FLASH EPROM AND DRAM This page is intentionally unused. 8-2 VX 91x/01x

63 9 ADDITIONAL LOCAL I/O FUNCTIONS The VX 91x/01x supports a variety of I/O functions whose addresses are summarized in Table 9-1. I/O Address Range Description 0x0000-0x001F DMA Controller (PCH) 0x0020-0x002D Interrupt Controller (PCH) 0x002E-0x002F Configuration Index and Data Registers (SuperI/O) 0x0030-0x003D Interrupt Controller (PCH) 0x0040-0x0043 PIT Timers (PCH) 0x0050-0x0053 PIT Timers (PCH) 0x0060 Keyboard Controller (SuperI/O) 0x0061 NMI Status (PCH) 0x0064 Keyboard Controller (SuperI/O) 0x0070 NMI Enable/RTC Address (PCH) 0x0071 RTC Data (PCH) 0x0080 Port 80 Debug Port 0x0092 Port 92 Reset Generator (PCH) 0x00A0-0x00A1 Slave Interrupt Controller (PCH) 0x00C0-0x00DF Slave DMA Controller (PCH) 0x00F0 Maths Coprocessor Error 0x0210-0x021F Control & Status Registers, Long Duration Timer 0x02F8-0x02FF COM2 Serial (SuperI/O) 0x03BC-0x03BF Parallel Port LPT1 (SuperI/O) (Not Used) 0x03F0-0x03F7 Floppy Controller (SuperI/O) (Not Used) 0x03F8-0x03FF COM1 Serial (SuperI/O) 0x04D0-0x04D1 Interrupt Control (PCH) 0x0CF8-0x0CFF PCI Configuration Registers (CPU) 0x0D00-0xFFFF PCI Free I/O Space Table 9-1 I/O Address Map Most of the addresses are standard PC-AT compatible values, but addresses 0x0210-0x021F provide custom Status & Control registers for board specific features. VX 91x/01x 9-1

64 ADDITIONAL LOCAL I/O FUNCTIONS 9.1 Onboard Status & Control Registers There are 13 byte wide status and control registers. They are accessed directly via the chipset s LPC bus at the following addresses: 0x0210 for Status & Control Register 0. 0x0211 for Status & Control Register 1. 0x0212 for Status & Control Register 2. 0x0213 for Watchdog Status & Control Register. 0x0214 for Status & Control Register 3. 0x0215 for Serial I/O configuration. 0x0216 for Status & Control Register 4. 0x0217 for Status & Control Register 5. 0x0218 for Long Duration Timer LS byte. 0x0219 for Long Duration Timer Mid Low byte. 0x021A for Long Duration Timer Mid High byte. 0x021B for Long Duration Timer MS byte. 0x021C for Long Duration Timer Status & Control Register. The following terms are used to describe the bit addressing: RO - Read Only RW - Read / Write RC - Read / Clear (writing 0 to this bit clears it to 0, writing 1 leaves it unchanged.) RS - Read / Set (writing 0 to this bit leaves it unchanged, writing 1 sets it to 1) WARNING: Changing the state of any RFU (Reserved for Factory Use) bits could have unpredictable results, therefore do not alter these states. 9-2 VX 91x/01x

65 9.2 Status & Control Register 0 ADDITIONAL LOCAL I/O FUNCTIONS Register Status & Control Register 0 Address 0x0210 Bit Access Name Description 7 Board revision. 6 RO REVISION 000 = Rev A = Rev B etc 4 - RFU Reserved 3 RO CONSOLE PORT SELECT 2 RO CONSOLE 1 RO USER 0 RO MODE Indicates the setting of the Console Port selection switch. See Section = COM1 1 = COM2 Indicates the setting of the Console Type switch. See Section = input via keyboard/output via VGA 1 = input /output via selected COM port Indicates the setting of the User Switch. See Figure 9-1 for the switch settings. 0 = switch is OFF 1 = switch is ON Indicates the setting of the Boot Mode Switch. See Section = CUTE operation 1 = BIOS operation ON SW2-4 - User switch OFF ON - 1 OFF Figure 9-1 User Switch VX 91x/01x 9-3

66 ADDITIONAL LOCAL I/O FUNCTIONS 9.3 Status & Control Register 1 Register Status & Control Register 1 Address 0x0211 Bit Access Name Description PMC PCI bus speed. 7 RO PMC SPD Mode RFU RFU 6 RO PMC SPD RFU MHz PCI-X MHz PCI MHz PCI 5 RO PMC SPD MHz PCI-X RFU 4 RO 3 RO XMC2 MODULE PRESENT XMC1 MODULE PRESENT 2 RO PMC/XMC INIT COMP 1 RO 0 RO PMC2 MODULE PRESENT PMC1 MODULE PRESENT This bit indicates whether an XMC module is present on XMC site 2. 0 = XMC module not present 1 = XMC module present This bit indicates whether an XMC module is present on XMC site 1. 0 = XMC module not present 1 = XMC module present 1 = PMC/ XMC module ready for enumeration 0 = PMC/ XMC module not ready for enumeration. Indicates whether a PMC module is present on PMC site 2. 0 = PMC module not present 1 = PMC module present Indicates whether a PMC module is present on PMC site 1. 0 = PMC module not present 1 = PMC module present 9-4 VX 91x/01x

67 9.4 Status & Control Register 2 ADDITIONAL LOCAL I/O FUNCTIONS Register Status & Control Register 2 Address 0x0212 Bit Access Name Description Front panel switch is the cause of NMI. 7 RC FP_NMI 6 RO TSI_NMI 5 RO 4 RO BDFAIL 3 RW 2 RW 1 RW VME SYSRESET STATUS VME SYSRESET INCOMING PUSH BUTTON RESET ENABLE VME SYSRESET OUTGOING 0 RC WD_NMI 0 = event has not occurred 1 = event has occurred TSI_NMI signal from the PCI-to-VME Bridge is the cause of NMI. This bit is set by the Tsi148 and should be cleared by writing to the appropriate Tsi148 register. 0 = TSI_NMI has occurred 1 = TSI_NMI has not occurred Indicates the state of the VME system reset signal. 0 = signal is de-asserted (high) 1 = signal is asserted (low) Provides the value of a signal driven by the Tsi148 device. 0 = signal is asserted (low) 1 = signal is de-asserted (high) Determines whether a VME backplane SYSRESET signal can cause a board reset. See Section for further details. 0 = VME backplane reset disabled 1 = VME backplane reset enabled This bit determines the front panel push button reset can cause board reset (or NMI), but does not prevent it requesting a chipset wake-up. See Section = push button disabled 1 = push button enabled Determines whether the board generates a VME backplane reset via SYSRESET signal only when acting as the System Controller. See Section for details of events that would assert SYSRESET. The VME Reset switch has to be in the Enabled position for the value of this bit to have any effect. 0 = allow SYSRESET to always be asserted 1 = allow SYSRESET to be asserted only when System Controller Watchdog is the cause of NMI. 0 = event has not occurred 1 = event has occurred VX 91x/01x 9-5

68 ADDITIONAL LOCAL I/O FUNCTIONS 9.5 Watchdog Timer The VX 91x/01x includes a hardware Watchdog timer which can be used by the operating software to monitor the normal operation of the system. The Watchdog is enabled by SW4-1 (Watchdog switch) and is controlled by software. Once enabled (SW4-1 ON) it must be restarted at regular intervals. If it is not restarted the timer will expire and cause a Non-Maskable Interrupt (NMI) or reset to the local processor and optionally a system reset. The Watchdog timer facility is provided by the SCH3114 SuperI/O Controller and details are provided in the SMSC data sheet. ON SW4-1 - Watchdog OFF - Disabled 1 ON - Enabled OFF Figure 9-2 Watchdog Configuration Switch The VX 91x/01x provides the Watchdog Status & Control Register to determine the action taken when the SuperI/O Watchdog timer expires and the signal is asserted - Section provides details of the register bits. 9-6 VX 91x/01x

69 9.5.1 Watchdog Status & Control Register ADDITIONAL LOCAL I/O FUNCTIONS Register Watchdog Status & Control Register Address 0x0213 Bit Access Name Description 7 - RFU Reserved 0 = local reset only (default) 1 = local and system reset 6 RW SYSTEM RESET ENABLE 5 RW SOFTWARE ENABLE The Watchdog action (Bit 2) must be set to 1 for this bit to have any effect. If both bits 6 and 2 are set to 1 and the Watchdog timer expires, then the VMEbus SYSRESET signal will be activated. Watchdog software enable 0 = Watchdog disabled (default) 1 = Watchdog enabled Watchdog enable switch status 4 RO HARDWARE ENABLE 0 = Watchdog is under software control 1 = Watchdog disabled in hardware Reports the status of the SCH3114 Watchdog signal. 3 RO STATUS 0 = Watchdog OK 1 = Watchdog timed out Selects the following actions when the Watchdog times out: 2 RW ACTION 0 = generate an NMI (default) 1 = generate a board and (optionally) a system reset 1 - RFU Reserved 0 - RFU Reserved VX 91x/01x 9-7

70 ADDITIONAL LOCAL I/O FUNCTIONS 9.6 Status & Control Register 3 Register Status & Control Register 3 Address 0x0214 Bit Access Name Description 7 RW GPIO3 DIR These bits set the data direction for the GPIO pins. 6 RW GPIO2 DIR 5 RW GPIO1 DIR 4 RW GPIO0 DIR 3 RW GPIO3 DATA 2 RW GPIO2 DATA 0 = pin is an input 1 = pin is an output Data written to these bits will be output on the GPIO pins when the direction is set for output. Reads of these bits will read the data present on the GPIO pins. If the direction is set for input and no external device is connected to the pin then the data will read as a one. There are switches on the GPIO signals to enable them to be used as software option inputs, as shown in Figure RW GPIO1 DATA 0 RW GPIO0 DATA Refer to Section C.2 for details of the GPIO electrical characteristics. Signal transitions on the GPIOs can generate an interrupt, as detailed in Section 9.8. ON 4 GPIO3 SW5 - GPIO Signals 3 GPIO2 2 GPIO1 1 GPIO0 OFF - GPIO function pulled up OFF ON - GPIO function forced low Figure 9-3 GPIO Signal Switches 9-8 VX 91x/01x

71 9.7 Status and Control Register 4 ADDITIONAL LOCAL I/O FUNCTIONS Register Status and Control Register 4 Address 0x0216 Bit Access Name Description 7 RO PH LED MODE Processor Hot LED mode. Reports the setting of the User/Processor Hot LED selection switch 0 = user LED mode 1 = processor HOT mode User LED control. 6 RW USER LED 5 RW XMC 2 MVMRO 4 RO CF PRESENT 3 RW XMC 1 MVMRO 2 RO BIOS DEFAULTS 1 RO VXS CONNECTED 0 = off 1 = on XMC site 2 write prohibit (MVMRO) signal control. The XMC module can use the state of the MVMRO signal to disable writes to memory on the module. 0 = Site 2 MVMRO driven low to enable writes 1 = Site 2 MVMRO pulled high to disable writes, another device can drive signal low to override the 10K pull up CompactFlash present. 0 = CompactFlash not fitted 1 = CompactFlash fitted XMC site 1 write prohibit (MVMRO) signal control. The XMC module can use the state of the MVMRO signal to disable writes to memory on the module. 0 = Site 1 MVMRO driven low to enable writes 1 = Site 1 MVMRO pulled high to disable writes, another device can drive signal low to override the 10K pull up Reports the setting of SW6-2 (Force Optimal Defaults switch) as detailed in Section = force optimal defaults 1 = use working set defaults Reports the status of the VXS connector PEN# signal which is asserted when the optional P0 connector mates with a VXS capable backplane. This signal can be forced true by SW4-4 (VXS Enable Mode switch) as detailed in Section = PEN# signal is false (high) 1 = PEN# signal is true (low) 0 - RFU Reserved VX 91x/01x 9-9

72 ADDITIONAL LOCAL I/O FUNCTIONS 9.8 Status and Control Register 5 Register Status & Control Register 5 Address 0x0217 Bit Access Name Description 7 RC GPIO3 TFLAG Transition Flag 6 RC GPIO2 TFLAG 5 RC GPIO1 TFLAG 4 RC GPIO0 TFLAG 3 RW GPIO3 TIE Transition Interrupt Enable 2 RW GPIO2 TIE 1 RW GPIO1 TIE 0 RW GPIO0 TIE A bit is set if the GPIO has transitioned from high to low. If the corresponding TIE bit is set, then an interrupt is generated and remains asserted until the flag bit or the TIE bit is set to zero. A high to low transition on the GPIO can generate an interrupt via IRQ5 (shared with the LDT), when the enable bit is set. 0 = disabled 1 = enabled 9-10 VX 91x/01x

73 9.9 Long Duration Timer / Periodic Interrupt Timer ADDITIONAL LOCAL I/O FUNCTIONS The Long Duration Timer (LDT) consists of a 32-bit free running counter with a 32-bit holding register and a Status & Control register. The LDT may be used by user software to timestamp events to a resolution of 1µs. The counter bytes are laid out in little-endian format to permit multibyte read/write operations. The Status & Control register controls the operation of the LDT. A 32-bit holding register is provided to ensure stable count values are read. Read operations return the holding register byte values. A read operation on the low byte of the counter causes the count value to be transferred to the holding register. The low byte should be read first to ensure a stable count value. The counter may be preset by writing to the registers. The counter bytes may be written independently. The counter should be stopped before writing to it or the outcome may be indeterminate. The counter registers are cleared at power-on, but not by subsequent reset operations. If necessary, the LDT can be cleared by writing zero to all four counter bytes. An interrupt may be generated when the counter rolls over (from 0xFFFFFFFF to zero). This occurs approximately every 72 minutes (1 MHz clock). The LDT doubles as a simple Periodic Interrupt Timer (PIT). It offers 7 fixed interrupt rates, namely: 100, 200, 500, 1,000, 2,000, 5,000 and 10,000 Hz (1 MHz clock). The mode / interrupt rate is set by three bits in the LDT status & control register. NOTE: If the LDT clock frequency is not 1 MHz (i.e. Clock = KHz), the above rates should be scaled accordingly. In PIT mode, the counter counts up to a pre-determined maximum value and then goes back to zero. To ensure a full first interval, the low and mid-low bytes of the counter should be cleared before the counter is started. VX 91x/01x 9-11

74 ADDITIONAL LOCAL I/O FUNCTIONS Long Duration Timer / Periodic Interrupt Timer Low Byte Register Long Duration Timer / Periodic Interrupt Timer Low Byte Address 0x0218 Bit Access Name Description 7 Low byte of LDT / PIT (Bits 7 0) RW LDT_PIT LOW_BYTE Reading this register causes the current value of the LDT to be transferred to a holding register. This allows a stable 4 byte count to be read. The low byte of the holding register is returned by the read. Writing to this register loads a value into the low byte of the LDT / PIT counter. The counter should be stopped when writing or the result will be indeterminate Long Duration Timer / Periodic Interrupt Timer Mid-low Byte Register Long Duration Timer / Periodic Interrupt Timer Mid-low Byte Address 0x0219 Bit Access Name Description RW LDT_PIT MID_LOW_BYTE Mid-low byte of LDT / PIT (Bits 15 8) Reading this register returns the mid-low byte of the holding register. Writing to this register loads a value into the mid-low byte of the LDT / PIT counter. The counter should be stopped when writing or the result will be indeterminate Long Duration Timer Mid-high Byte Register Long Duration Timer Mid-high Byte Address 0x021A Bit Access Name Description RW LDT MID_HIGH_BYTE Mid-high byte of LDT (Bits 23 16) Reading this register returns the mid-high byte of the holding register. Writing to this register loads a value into the mid-high byte of the LDT counter. The counter should be stopped when writing or the result will be indeterminate Long Duration Timer High Byte Register Long Duration Timer High Byte Address 0x021B Bit Access Name Description RW LDT HIGH_BYTE High byte of LDT (Bits 31 24) Reading this register returns the high byte of the holding register. Writing to this register loads a value into the high byte of the LDT counter. The counter should be stopped when writing or the result will be indeterminate VX 91x/01x

75 9.9.5 LDT / PIT Status and Control Register ADDITIONAL LOCAL I/O FUNCTIONS Register LDT / PIT Status and Control Register Address 0x021C Bit Access Name Description 7 RW INTERRUPT MASK Enable or disable IRQ5 interrupt generation when bit 4 becomes set. 0 = enable interrupts 1= disable interrupts 6 RFU Reserved 5 RW CLOCK SELECT 4 RC LDT/PIT INTERRUPT LDT / PIT clock source. 0 = 1 MHz 1 = khz LDT / PIT interrupt event flag which is active whenever the timer is running. It is set if the LDT RUN bit is set AND either the LDT rolls over or the PIT interval expires. It can be cleared by writing to the register with a zero in its bit position. This should be done in the LDT / PIT interrupt service routine. 3 2 RW MODE 1 0 RW RUN 0 = LDT / PIT interrupt event has not occurred 1 = LDT / PIT interrupt event has occurred LDT / PIT mode = LDT = PIT 100 Hz = PIT 200 Hz = PIT 500 Hz = PIT 1,000 Hz = PIT 2,000 Hz = PIT 5,000 Hz = PIT 10,000 Hz NOTE: The above PIT rates require bit 5 to be 0. LDT / PIT run. This bit controls whether the LDT / PIT runs or is stopped. 0 = stop (default) 1 = run The LDT clock signal is obtained from a PCH 48 MHz clock which is divided down by board logic device to provide two selectable clock rates of 1 MHz or khz. VX 91x/01x 9-13

76 ADDITIONAL LOCAL I/O FUNCTIONS Programming the LDT/PIT The following code fragments illustrate how the system software, by using the on-board hardware, can create accurate time delays and measure elapsed times, accurate to 1µs, irrespective of the CPU s operating frequency. The LDT and PIT control registers and operational modes are defined thus: #define TIMER_BYTE_0 (0x0218U) #define TIMER_BYTE_1 (0x0219U) #define TIMER_BYTE_2 (0x021AU) #define TIMER_BYTE_3 (0x021BU) #define CONTROL_STATUS (0x021CU) #define INTERRUPT_MASK #define INTERRUPT_ENABLE #define INTERRUPT_DISABLE #define INTERRUPT_SET #define INTERRUPT_RESET #define TIMER_ROLLOVER #define MODE_MASK #define MODE_PIT_10000Hz #define MODE_PIT_5000Hz #define MODE_PIT_2000Hz #define MODE_PIT_1000Hz #define MODE_PIT_500Hz #define MODE_PIT_200Hz #define MODE_PIT_100Hz #define MODE_LDT #define MODE_RUN_MASK #define MODE_RUN_GO #define MODE_RUN_STOP (0x10U) (0x10U) (0x00U) (0x10U) (0x00U) (0x10U) (0x0EU) (0x0EU) (0x0CU) (0x0AU) (0x08U) (0x06U) (0x04U) (0x02U) (0x00U) (0x01U) (0x01U) (0x00U) The following code fragment illustrates how a simple delay of 10ms is implemented. outbyte (CONTROL_STATUS, MODE_RUN_STOP); outbyte (TIMER_BYTE_0, 0); outbyte (TIMER_BYTE_1, 0); outbyte (TIMER_BYTE_2, 0); outbyte (TIMER_BYTE_3, 0); outbyte (CONTROL_STATUS, MODE_PIT_100Hz MODE_RUN_GO); /* wait until the PIT rolls over... */ while (inbyte (CONTROL_STATUS) & TIMER_ROLLOVER) == 0) ; /* do nothing... */ /* reset the PIT "rollover" flag... */ outbyte (CONTROL_STATUS, MODE_RUN_STOP); 9-14 VX 91x/01x

77 ADDITIONAL LOCAL I/O FUNCTIONS It is possible to implement delays of 5ms, 2ms, 1ms, 500μs, 200μs and 100μs by utilizing other PIT modes. The PIT can generate an interrupt whenever the PIT rolls over. The system programmer must initialize the interrupt vector, enable PIC interrupts, etc. The following code fragment shows the basic interrupt handling function. static volatile signed long int dcounter; #pragma interrupt (vinterrupthandler) static void far vinterrupthandler (void) { /* * clear the source of the interrupt by resetting the rollover * flag, thus: */ outbyte (CONTROL_STATUS, inbyte (CONTROL_STATUS) & ~INTERRUPT_MASK); /* * perform the relevant actions to acknowledge the interrupt * in the PIC, etc... */ } dcounter--; The following code fragment used in conjunction with the previous code fragment illustrates another method of implementing a timed delay. The dcounter variable is declared to be volatile which prevents any C compilers, which conform to the ANSI standard, from optimizing accesses to the dcounter variable. outbyte (CONTROL_STATUS, MODE_RUN_STOP); outbyte (TIMER_BYTE_0, 0); outbyte (TIMER_BYTE_1, 0); outbyte (TIMER_BYTE_2, 0); outbyte (TIMER_BYTE_3, 0); outbyte (CONTROL_STATUS, MODE_PIT_100Hz MODE_RUN_GO); dcounter = 500; /* 500 * (1 / 100) == 5 seconds */ /* * install the interrupt for the PIT counter, modify the * PIC settings, etc. and ensure interrupts are enabled. */ while (dcounter > 0) ; /* do nothing... */ outbyte (CONTROL_STATUS, MODE_RUN_STOP); VX 91x/01x 9-15

78 ADDITIONAL LOCAL I/O FUNCTIONS The following code fragment uses the LDT to measure the elapsed time to a resolution of 1ms. In this example, the LDT is zeroed at the start of the test and so there is no need to subtract the LDT s initial value from its final value. static UINT32 delapsedtime; outbyte (CONTROL_STATUS, MODE_RUN_STOP); outbyte (TIMER_BYTE_0, 0); outbyte (TIMER_BYTE_1, 0); outbyte (TIMER_BYTE_2, 0); outbyte (TIMER_BYTE_3, 0); outbyte (CONTROL_STATUS, MODE_LDT MODE_RUN_GO); /* * perform action to be timed... */ outbyte (CONTROL_STATUS, MODE_STOP); delapsedtime = (UINT32) inbyte (TIMER_BYTE_0); delapsedtime = ((UINT32) inbyte (TIMER_BYTE_1)) << 8; delapsedtime = ((UINT32) inbyte (TIMER_BYTE_2)) << 16; delapsedtime = ((UINT32) inbyte (TIMER_BYTE_3)) << 24; printf ("Elapsed time = %u.%06u seconds\n", delapsedtime / U, delapsedtime % U); The TIMER_BYTE_0, TIMER_BYTE_1, TIMER_BYTE_2 and TIMER_BYTE_3 control registers are at successive addresses and form a 32-bit register in little endian format. It is possible to read and write the timer s value in a single 32-bit I/O operation. For example, to read the timer s value, the following C statement suffices. dcountervalue = inlong (TIMER_BYTE_0); 9-16 VX 91x/01x

79 10 BIOS The VX 91x/01x is supplied with a UEFI BIOS implemented using InsydeH2O from Insyde Software. The BIOS on Concurrent Technologies board products looks and behaves very similar to that found on laptops or desktop computers, however, it also includes a number of internal adaptations, which tailor it to the embedded computing environment. In particular, the BIOS allows redirection of the console function to a serial terminal or emulator program rather than using a video adaptor and it provides extensions to configure the VME interface. A complete description of the functions provided by the VX 91x/01x BIOS can be found in the associated document Technical Reference Manual for the VX 91x/01x BIOS (Manual Order Number ) Entering the BIOS The startup mode of the board may be selected using the SW2-3 (Boot Mode switch) and can be either the factory default setting BIOS mode (SW2-3 OFF), which generally follows the behavior of a desktop PC or CUTE mode (SW2-3 ON). CUTE mode (Concurrent Technologies Unified Test Environment) is a more flexible and comprehensive testing mode, which can be used for system or board testing. ON SW2-3 - Boot Mode OFF - BIOS 1 ON - CUTE OFF Figure 10-1 Boot Mode Switch Users can exit CUTE mode (SW2-3 ON) by operator command and the board will enter BIOS mode and continue as if this mode had been selected with the switch. When the board is reset, it will restart in the switch-selected operating mode. Operator communication with the BIOS is normally through the VGA display and a separate keyboard. This can be reconfigured with on-board switches to use a serial terminal connected to the COM1 or COM2 ports as described in Section 7.1. A VT100-compatible serial terminal or emulator program should be used. By default the serial line is programmed to operate at 115,200 Baud with 8 data bits, 1 stop bit and no parity (8N1). There is no flow control. For slow terminals, the baud rate can be decreased via the Baud Rate field of the Advanced Console Redirection menu. VX 91x/01x 10-1

80 BIOS 10.2 The BIOS Startup Sequence When the board starts up without operator intervention, it will run a basic POST sequence including ECC DRAM initialization and a DRAM test. Once the DRAM test has completed, the board will try to bootload application software from any attached mass storage media or through one of the Ethernet interfaces. Pressing <F2> during the BIOS startup sequence will enter the BIOS Setup menu. The Setup menu is extensive and has context-sensitive help displayed in the right-hand panel on screen. NOTE: When <F2> is pressed, a few seconds may elapse before the BIOS Setup menu appears. The BIOS will always run BIOS Extensions for any PMC or XMC modules it detects before responding to a keypress VX 91x/01x

81 10.3 Boot device selection The Setup Boot Menu BIOS The order in which the BIOS searches for bootable media is pre-configured but may be altered by the operator using the Boot Legacy setup sub-menu. When the order is changed using this menu it will be retained in non-volatile memory so that the order is maintained after a restart. The boot order menu has two configuration modes: Normal and Advanced. This can be selected via the Boot Legacy Normal Boot Menu setup sub-menu Normal In Normal mode, the user specifies the boot order using device categories. The Boot Type Order sub-menu specifies the relative ordering for Hard Disk, CD/DVD-ROM, Floppy and Others device categories. The <+> and < > keys can be used to raise or lower the relative priority of each device category. For each category where a physical device is attached an additional sub-menu will be created. Through this menu, the relative boot order of devices within that category can be further configured, again using the <+> and < > keys Advanced In Advanced mode, the user specifies the boot order for all attached devices through a unified device list. The <+> and < > keys can be used to raise or lower the relative priority of each device. This mode provides complete control over the boot order; however, the user requires a greater understanding of the attached boot devices One-time Boot Override It is also possible to specify a one-time override of the boot device when the board starts, by pressing <F12>. This will result in the BIOS entering the Boot Manager. From here, the required boot device may be selected from a list using the cursor keys and pressing <Enter>. However, this selection is not retained in non-volatile memory, so the correct device must be re-selected if necessary at a subsequent restarts. NOTE: When <F12> is pressed, a few seconds may elapse before the boot device selection menu appears. The BIOS will always run BIOS Extensions for any PMC modules it detects before responding to a key press. Alternatively, the Boot Manager can be quit by pressing <Esc>, which offers the options to enter Setup or Continue and boot using the order previously configured through Setup PXE Network Boot The on-board Ethernet channels require their PXE Firmware to be enabled before they can be used as boot devices. A BIOS setup option controls whether PXE Firmware runs for the front or rear Ethernet channels, this can be found under Main Boot Features PXE Boot. The Ethernet boot firmware allows remote booting using the Pre-Boot Execution (PXE) protocols. Further information on the capabilities of this software is available from the Intel web site at: NOTE: The BIOS has limited space available for Extension ROMs. If a PMC module containing extension firmware is fitted to the board, it may be necessary to disable one or more of the on-board firmware extensions before the PMC firmware can be loaded. VX 91x/01x 10-3

82 BIOS 10.4 PCI Bus Resource Management The bus structure of the VX 91x/01x is complex. There are two on-board PCI busses and several PCIe ports. A 64-bit PCI bus connects between a PCIe-to-PCI-X bridge and the two PMC sites. This bus operates with 5V or 3.3V signalling levels and supports PCI bus mode at 33 or 66 MHz, or PCI-X mode at 66 or 100 MHz. A 64-bit PCI bus connects between a PCIe-to-PCI-X bridge and the Tsi148. This bus operates with 3.3V signaling levels and runs at 66 MHz in PCI-X mode PCI Express Ports The CPU, PCH and IDT PCIe switch provide several PCIe ports. The CPU provides two 8-lane ports connected as follows: An 8-lane port to XMC site 2. This can also be configured as two 4-lane ports. An 8-lane port to the IDT PCIe switch. The IDT PCIe switch 8-lane upstream port connects to the CPU and the downstream ports are connected as follows: An 8-lane port to XMC site 1. This can also be configured as two 4-lane ports. A 4-lane port to VXS P0 connector, to support VITA 41.4 Port A. A 4-lane port to VXS P0 connector, to support VITA 41.4 Port B. The PCH ports are configured and assigned as follows: A 2-lane port to a PCIe-to-PCI-X bridge which provides the Tsi148 PCI-X bus interface. A 2-lane port to an 82580EB quad Ethernet controller. A 4-lane port to a PCIe-to-PCI-X bridge which provides the PCI/PCI-X bus for the PMC sites VX 91x/01x

83 PCI Resource Allocation BIOS The BIOS initializes all devices on the local PCI bus, and allocates appropriate memory address ranges, I/O address ranges, and interrupt routings for all these devices. This process is automatic as part of the BIOS Plug-and-play setup. The Intel chipset allows for a flexible allocation of many PCI bus interrupts to the available interrupt inputs on the PC-compatible interrupt controllers provided on the board. The BIOS uses this feature to program default settings which it considers appropriate for the combination of on-board devices and any device fitted to the PMC sites. The interrupt controller in the PCH can operate in two basic modes, namely PIC (or Non-APIC) mode and APIC mode. PIC mode corresponds to the legacy PC interrupt structure. APIC mode provides additional interrupts and several functional improvements. No PCI or PCIe devices are hard-wired to interrupt inputs on the PCH, except for Tsi148 INTA# which connects to PIRQG# on the PCH. Table 10-1 lists the typical interrupt structure in PIC mode. A total of 15 usable interrupts are available. The actual allocation of PCI bus interrupts to available interrupt controller inputs will depend on both the default Plug-and-play settings programmed by the BIOS. When more than one PCI bus interrupt is routed to the same interrupt controller input, that input will remain active while any of the sources connected to it are active. Interrupt Device(s) IRQ0 Timer 0 IRQ1 Keyboard controller IRQ2 Slave PIC IRQ3 Serial Port COM2 IRQ4 Serial Port COM1 IRQ5 Long Duration Timer / GPIOs IRQ6 PCI device interrupt IRQ7 PCI device interrupt IRQ8 Real Time Clock IRQ9 PCI device interrupt IRQ10 PCI device interrupt IRQ11 PCI interrupt IRQ12 Mouse controller IRQ13 Floating Point Error IRQ14 Primary IDE in Legacy mode IRQ15 Secondary IDE in Legacy mode Table 10-1 Interrupt Structure in PIC Mode VX 91x/01x 10-5

84 BIOS Table 10-2 lists the typical interrupt structure in APIC mode. A total of 24 interrupts are available. The PCH interrupt inputs PIRQA PIRQH are mapped to IRQ16 IRQ23 respectively. Interrupt Device(s) IRQ0 Legacy PIC Interrupt IRQ1 Keyboard Controller IRQ2 Timer 0 IRQ3 Serial Port COM2 IRQ4 Serial Port COM1 IRQ5 Long Duration Timer / GPIOs IRQ6 IRQ7 IRQ8 Real Time Clock IRQ9 IRQ10 IRQ11 IRQ12 Mouse Controller IRQ13 Floating Point Error IRQ14 Primary IDE in Legacy mode IRQ15 Secondary IDE in Legacy mode IRQ16 PIRQA IRQ17 PIRQB IRQ18 PIRQC IRQ19 PIRQD IRQ20 PIRQE IRQ21 PIRQF IRQ22 PIRQG - Tsi148 INTA# IRQ23 PIRQH Table 10-2 Interrupt Structure in APIC Mode NOTE: IRQ16 to IRQ23 can be used for PCH internal devices VX 91x/01x

85 PCI Device IDs BIOS Each PCI bus, and each device on an individual PCI bus, has a unique ID. The VX 91x/01x bus and device IDs are listed in Table Bus numbers shown are the default assignments by the BIOS and can change depending upon fitted optional devices, e.g. XMC or PMC card, and/or BIOS CMOS settings. Device Bus ID PCI Function Code Vendor ID Device ID Host bridge / DRAM controller x8086 0x0154 Host to PCIe bridge x8086 0x0151 Host-to-PCIe bridge - XMC x8086 0x0155 Internal graphics controller x8086 0x0166 PCH - Reserved x8086 0x1E31 PCH - Reserved x8086 0x1E3A PCH - USB EHCI # x8086 0x1E2D PCH - x2 PCIe Port x8086 0x1E10 PCH - x2 PCIe Port x8086 0x1E14 PCH - x4 PCIe Port x8086 0x1E18 PCH - USB EHCI # x8086 0x1E26 DMI-to-PCI Bus bridge x8086 0x2448 LPC Bus bridge x8086 0x1E55 SATA controller x8086 0x1E01 SMBus Controller x8086 0x1E22 SATA controller x8086 0x1E09 PES32NT8 - Upstream x111D 0x808F PES32NT8 - DMA Controller x111D 0x808F PES32NT8 - Down VXS PB x111D 0x808F PES32NT8 - Down VXS PA x111D 0x808F PES32NT8 - Down XMC x111D 0x808F PI7C9X x12D8 0xE130 Tsi148 VME bridge x10E3 0x EB Ch x8086 0x150E 82580EB Ch x8086 0x150E 82580EB Ch x8086 0x EB Ch x8086 0x1510 PI7C9X130 PMC bridge x12D8 0xE130 Table 10-3 PCI Device Numbers VX 91x/01x 10-7

86 BIOS Tsi148 Outbound Image Allocation Boards fitted with 4 or more Gbytes of DRAM do not have a convenient hole in the address map where Tsi148 Local Outbound Slave Images can be mapped. Therefore the BIOS must reserve a block of address space for this purpose. The VME Bridge Outbound Reserved Size setup option is used to specify the size of the reserved memory block. If desired VME Outbound Images 0 and 1 can be configured using the VME Outbound Images sub-menu, however, the total of the two image sizes must not exceed the reserved size. The BIOS reserves memory by increasing the size of the block used by PCI devices, i.e. the top of DRAM is lowered. The BIOS creates a data-structure in DRAM that defines details of the reserved memory, this is described below Tsi148 Inbound Image Allocation Some operating systems wishing to map Tsi148 VME Slave (Inbound) Images into DRAM can encounter problems allocating the required buffers. To overcome this, the BIOS can reserve a block of DRAM (below 4 Gbytes) that is hidden from the operating system memory-manager. The size of the reserved block is specified through the VME Bridge Inbound Reserved Size option. The BIOS allocates this memory by marking the specified block of memory as reserved, thus preventing the operating system memory-manager from utilizing it. Details of the data structure are described below VX 91x/01x

87 VME Reserved Memory Data Structure BIOS Details of the Outbound and Inbound memory reservations are provided by the VME Reserved Memory data structure, which the BIOS constructs in DRAM. Software requiring details of this reserved memory block can locate this structure by searching for the signature bytes between addresses 0xE0000 and 0xFFFFF. /* Header part */ UINT32 vmelsi_header = EMV$'; /* signature, $ in LSB */ UINT8 vmelsi_version = 0x02; /* version of structure */ UINT8 vmelsi_length; /* total length of structure */ UINT16 vmelsi_reserved = 0; /* Version 1 payload */ UINT32 vmelsi_mem_base; /* physical address of reserved block */ UINT32 vmelsi_mem_size; /* size (in bytes) of reserved block */ UINT32 vmelsi_image_0_base; /* base address of enabled LSI images / UINT32 vmelsi_image_1_base; UINT32 vmelsi_image_2_base; UINT32 vmelsi_image_3_base; UINT32 vmelsi_image_4_base; UINT32 vmelsi_image_5_base; UINT32 vmelsi_image_6_base; UINT32 vmelsi_image_7_base; /* Version 2 payload */ UINT32 vmevsi_mem_base; /* physical address of reserved block */ UINT32 vmevsi_mem_size; /* size (in bytes) of reserved block */ UINT32 vmevsi_image_0_base; /* base address of enabled VSI images */ UINT32 vmevsi_image_1_base; UINT32 vmevsi_image_2_base; UINT32 vmevsi_image_3_base; UINT32 vmevsi_image_4_base; UINT32 vmevsi_image_5_base; UINT32 vmevsi_image_6_base; UINT32 vmevsi_image_7_base; VX 91x/01x 10-9

88 BIOS 10.5 BIOS Defaults The BIOS provided with the VX 91x/01x stores configuration data in Flash NVRAM, rather than battery-backed CMOS RAM, so that settings are not lost if the board is powered-off and the battery removed. The BIOS contains three sets of configuration data: a Working Set, a set of Optimal Defaults and a set of Custom Defaults. When the board is shipped from the factory, the Working Set will contain the Optimal Defaults. The Optimal Defaults are pre-configured in the factory and cannot be changed by the user. The user can restore the board to the factory default settings at any time using the Exit Load Optimal Defaults option. When the board is powered-on, configuration settings will always get loaded from the Working Set. When settings are modified and saved via the Exit Exit Saving Changes option, only the Working Set will be updated with these changes. If desired, the user can save their preferred settings as Custom Defaults via the Exit Save Custom Defaults option; this will also save the selected configuration to the Working Set. Later, if the settings are subsequently changed, the user can quickly return to their preferred configuration using the Exit Load Custom Defaults option. If the board ever fails to boot due to changes made via Setup, the board can be forced back to the factory configured settings using the SW6-2 (Force Optimal Defaults switch). Once the board is booted with the switch in the Factory Settings position (SW6-2 ON), it should be powered off and the switch returned to the User Settings position (SW6-1 OFF), otherwise changes made via Setup will be lost each time the board is power cycled. ON SW6-2 - Force Optimal Defaults OFF - User Settings 1 ON - Factory Settings OFF Figure 10-2 Force Optimal Defaults Switch NOTE: If the board is ever returned to the factory for repair the saved NVRAM settings may be changed or invalidated VX 91x/01x

89 10.6 The Recovery BIOS BIOS In the unlikely event that the board s BIOS ROM contents becomes corrupted and it is not possible to perform the normal BIOS update procedure, the VX 91x/01x has a minimal Recovery BIOS that will allow the board to boot from a disk and restore a known-good BIOS image. The BIOS recovery process can also be forced using SW6-1 (Boot Type switch), as shown in Figure ON SW6-1 - Boot Type OFF - Normal 1 ON - Recovery Mode OFF Figure 10-3 Boot Type Switch The Recovery BIOS requires a suitable firmware image which can be obtained from Concurrent Technologies, if required. VX 91x/01x 10-11

90 BIOS 10.7 VXS PCIe Routing The VXS Ports A and B are connected to a multiplexer and can be routed to either the IDT PES32NT8AG2 PCIe Packet switch or to the XMC site 1 rear I/O. BIOS Setup options for VXS VXS Port A Route and VXS VXS Port B Route select the desired routing. Other Setup options found under the VXS menu are provided for selecting the VXS Port A and B PCIe lane width and speed (2.5 Gbps or 5.0 Gbps). These settings together with the routing information are stored in a small EEPROM attached to the multiplexer. Whenever the multiplexer Setup options are changed, the new configuration is written to the EEPROM when the user saves the BIOS Setup. NOTE: The multiplexer settings stored in the EEPROM are loaded at power on. Any changes to the multiplexer configuration will require the board to be power cycled for the changes to take effect VX 91x/01x

91 10.8 VXS PCIe Non-Transparent Bridge Setup BIOS The IDT PES32NT8AG2 PCIe Packet switch that implements the VITA 41.4 backplane PCIe ports allows one or both ports to be configured as a Non-Transparent (NT) bridge. The BIOS has support for enabling the NT bridge function of the switch and configuring the PCI base address registers (BARs) on either side of the NT bridge. The NT bridge Setup options are located under the VXS PCIe top-level menu. The VXS VXS Port A NT Mode or VXS VXS Port B NT Mode options enable the NT bridge function on a per-port basis. This can be set to Enabled or Disabled ; the default is "Disabled". When the NT port is enabled (for either port) two sub-menus are revealed that allow configuration of up to four BAR registers for outbound access and four BAR registers for inbound access to the NT bridges. For each BAR, options are provided for enabling the BAR, specifying the decode size, port assignment, translation address and prefetchable status. When a VXS interface is configured for NT mode, the Transparent PCI-to-PCI bridge function in the IDT PCIe Packet Switch that is normally present to support the VITA 41.4 port is disabled and not present. To support the NT interface, a new function #1 appears on the upstream device of the switch NOTE: VXS Port-A connects to port-12 of the PES32NT8AG2 and VXS Port-B connects to port Outbound Windows The Outbound Windows BARs give the local CPU access to the VXS PCIe interfaces via the IDT PCIe Packet Switch Upstream NT function. Four 32-bit BAR registers are provided by the Outbound Windows. When only one VXS port is configured to NT mode, the BARS are automatically assigned to that port. When both VXS ports are in NT mode, the windows can be assigned to a particular port Inbound Windows The Inbound Windows BARs give a device on the VXS PCIe interface access to the local board memory via the IDT PCIe Packet Switch port NT end-point functions. Four 32-bit BAR registers are provided by the Inbound Windows. The BARs can be assigned to a particular VXS port if both are in NT mode, otherwise they default to the enabled NT port when only one is in NT mode. VX 91x/01x 10-13

92 BIOS NT Bridge Address Translation The NT bridge forms PCI addresses by concatenating the least significant bits from the CPU generated address and the most significant bits from the BAR translation address; the contribution from each part is fixed and is determined by the BAR size. The translation address must be a multiple of the BAR size, which in turn must be a power of two. The BAR Setup option for Image Size allows selection from a series of pre-configured sizes, the option for Translation Address allows the address to be specified directly. The following example illustrates the address translation mechanism for a CPU access via the NT function interface to VXS Port A. The same principle applies in the reverse direction. Out BAR size: 0x Mbytes Out BAR translation address: 0x specified by User via Setup Out BAR PCI address: 0xDC allocated by the BIOS CPU address: 0xDC generated by driver or application Offset within BAR: 0x Address on VXS Port A: 0x BAR offset + translation address The BAR translation address can be configured (or changed) by an application program, however the BAR size must be specified before the PCI bus is enumerated by the BIOS (or re-enumerated by an operating system VX 91x/01x

93 11.1 Thermal Management 11 SYSTEM MANAGEMENT Under typical load conditions, the heatsink (and cooling airflow) will keep the processor die temperature within specification. However, if the board is running CPU-intensive or stress software or if the airflow is inadequate, the heatsink alone may not be able to prevent the processor overheating. To ensure that the processor always operates within its thermal specifications, it includes several thermal management and protection functions. Each of these is described below Adaptive Thermal Monitor (ATM) ATM uses temperature sensors located near to the hottest parts of each CPU core on the processor die. If a sensor detects a critically high temperature a thermal control circuit (TCC) will adjust the processor and graphics engine operating frequencies and core voltage. These actions cause the CPU core to decrease its power consumption, which in turn lowers the die temperature. If further power reduction is required, the processor clock is modulated i.e. will alternatively stop and start. Intel individually calibrates the temperature sensors. The ATM characteristics are also fixed by Intel and cannot be modified. ATM is disabled after Reset and has to be enabled by the BIOS CPU Thermal Trip The processor chip also contains a thermal trip circuit. This is intended to protect the processor in the event of a catastrophic cooling failure. If the die temperature reaches approximately 130 C, it shuts down the processor core and asserts the THERMTRIP# signal. Logic on the board responds to this assertion by removing power to most of the board within a few milliseconds. After about 8 seconds, power is re-applied and, if the over temperature condition still exists, power will again be removed. The thermal trip circuit is always operational and cannot be disabled. NOTE: The User LED will flash rapidly at a rate of approximately 1 Hz whilst the thermal trip circuit activates Processor Speed Step In addition to the thermal management options described above, the BIOS also includes a feature that can restrict the maximum CPU operating frequency, giving a more predictable reduction in the CPU power consumption. The setup option for Main Boot Features CPU Operating Frequency controls this. This option also ensures that an operating system will not subsequently increase the frequency above the specified setting. VX 91x/01x 11-1

94 SYSTEM MANAGEMENT Processor Thermal Status Indication The User/Processor Hot LED may be programmed to indicate if the processor die has reached the critical temperature at which thermal management is activated. This is done by using SW3-1 (Front Panel LED Mode). Figure 11-1 shows the location of this switch on the board, its settings and default position. ON SW3-1 - Front Panel LED Mode OFF - User 1 ON - Processor Hot OFF Figure 11-1 Front Panel LED Mode Switch The User/Processor Hot LED will also report a CPU thermal trip, as detailed in Section , regardless of the above switch setting VX 91x/01x

95 A.1 Functional Description A SPECIFICATIONS Processor: 4-core 2.1 GHz Intel Core i7-3612qe or 2-core 2.5 GHz Intel Core i7-3555le Level 1 Cache: 32 Kbytes instruction cache and 32 Kbytes data cache per core. Level 2 Cache: 256 Kbytes shared instruction and data cache per core. Last Level Cache: 6 Mbytes (3612QE) or 4 Mbytes (3555LE) Memory: 8 Mbytes SPI Flash EPROM for BIOS and other firmware. Up to 16 Gbytes DDR ECC DRAM as defined by order number. Interfaces: 64-bit VME interface utilizing the IDT Tsi148 VME-to-PCI-X bridge supporting up to 2eSST and 2eVME. Dual 4-lane PCIe ports connected to P0 to support VXS VITA 41.4 backplane. Option to connect VXS fabric interfaces to XMC P16 connector. One RS232 serial channel via front panel connector using compatible UART. Full set of signals. One RS232/RS485 serial channel via rear P2 connector using compatible UART. Full set of signals. Two SATA600 interfaces via rear P0 connector. Two SATA300 interfaces via rear P2 connector One SATA300 to support on-board mass storage option interface. CompactFlash socket. Two USB interfaces via front panel connector, two USB interfaces via rear P0 connector and two USB interfaces via rear P2 connector. USB 1.1 (1.5 and 12 Mbps) and USB 2.0 (480 Mbps) operation are supported. Two single-width PMC sites supporting 64/32-bit 66/33 MHz PCI or 66/100 MHz PCI-X interface with 3.3V or 5V signaling. Both 5V and 3.3V power rails are provided. An 8-lane XMC interface on both PMC sites. XMC power rail connected to 5V. Four Gigabit Ethernet interfaces using 82580EB controller. Two interfaces support 10/100/1000 Mbit/s connections, one via front panel and the other via P0 connector. Two interfaces support 1000 Mbit/s SerDes mode via P0 using VITA 41.6 pin assignments. Front panel Push Button Reset. Four general purpose I/Os via rear P2. DVI-I and DVI-D monitor interfaces via front panel console connector. DVI-D monitor interface on rear P2 connector. Analog interface on DVI-I supports up to 1920 x 1200, 16M colors. All digital interfaces support up to 1600 x 1200, or 1920 x M colors. Up to two interfaces can be used simultaneously. Peripherals: Intel QM77 PCH providing standard PC-AT peripherals. PC-AT Real Time Clock. 32-bit Periodic Interval Timer with processor interrupt capability. Watchdog timer. VX 91x/01x A-1

96 SPECIFICATIONS A.2 Environmental Specifications Standard Temperature (N-Series) Extended Temperature (E-Series) Extended Temperature (K-Series, 2.5 GHz) Ruggedized Air-Cooled (RA Series 2.5 GHz Temperature Range (operating) 0 C to +55 C -25 C to +70 C -40 C to +70 C -40 C to +75 C Temperature Range (storage) -40 C to +85 C -40 C to +85 C -40 C to +85 C -50 C to +100 C Temperature Rate of Change 1 C / min 2 C / min 3 C / min 3 C / min Airflow 400 LFM 400/500 LFM 400 LFM 500 LFM (linear feet per (note 1) (note 2) (note 1) (note 1) minute) Relative Humidity (operating) 5% to 95% 5% to 95% 5% to 95% 5% to 95% Relative Humidity (storage) 5% to 95% 5% to 95% 5% to 95% 5% to 95% Humidity Protection Optional Optional Yes Yes Altitude (operating) 0 to 15,000 ft 0 to 15,000 ft 0 to 15,000 ft to 33,000 ft (0 to 4,572m) (0 to 4,572m) (0 to 4,572m) (-305 to 10,058m) Altitude (storage) 0 to 50,000 ft 0 to 50,000 ft 0 to 50,000 ft to 50,000 ft (0 to 15,240m) (0 to 15,240m) (0 to 15,240m) (-305 to 15,240m) Table A-1 Environmental Specifications NOTE 1: The specified airflow is required to achieve the maximum operating temperature whilst the board is sustaining an intensive level of concurrent activity on all the processor cores and the graphics display engine. NOTE 2: The specified airflow of 400 LFM is required to achieve the maximum operating temperature whilst the board with a 2.5 GHz 2-core processor is sustaining an intensive level of concurrent activity on all the processor cores and the graphics display engine. For a board fitted with a 2.1 GHz 4-core processor the 400 LFM airflow is for a more typical processor and graphics display engine level of activity, whereas, airflow of 500 LFM is required for a substantial level of concurrent activity on all processor cores and the graphics display engine. NOTE: If the on-board hard disk drive option is fitted, the operating temperature range will be restricted to +5 to +55ºC and the storage temperature range will be restricted to -40 to +65ºC. NOTE: If the battery is fitted, the storage temperature range will be restricted to 20 C to +70ºC. This is because the QM77 PCH device is partially operational when the battery is connected. The battery life will be reduced by storage at high temperatures due to an increase in self-discharge. It is therefore recommended that the battery be removed during storage. A-2 VX 91x/01x

97 A.3 Shock and Vibration Specification SPECIFICATIONS Shock Sinusoidal Vibration Random Vibration Table A-2 Standard Temperature, N-Series 20g, 11ms, ½ sine 0.38mm pk at 5 Hz to 36Hz 2g at 36Hz to 2kHz Extended Temperature, E-Series 20g, 11ms, ½ sine 0.38mm pk at 5Hz to 36Hz 2g at 36Hz to 2kHz Extended Temperature, K-Series (2.5 GHz) 20g, 11ms, ½ sine 0.38mm pk at 5Hz to 36Hz 2g at 36Hz to 2kHz Ruggedized Air-cooled RA Series (2.5 GHz) 40g, 11ms, ½ sine N/A N/A N/A N/A 0.04g 2 /Hz (Note 1) VITA 47 Class V2 Shock and Vibration Specifications (Operating) NOTE 1: VITA 47 Class V2: 5 Hz to 100 Hz, PSD increasing at 3dB/octave. 100 Hz to 1000 Hz, PSD = 0.04 g 2 /Hz Hz to 2000 Hz, PSD decreasing at 6dB/octave. NOTE: All the above figures are for boards without an on-board mass storage drive. VX 91x/01x A-3

98 SPECIFICATIONS A.4 MTBF Values Board Variant Test used Temperature Environment MTBF VX 915/ MIL C Table A-3 MTBF Values Ground benign 297,900 hrs A-4 VX 91x/01x

99 A.5 Dimensions (All variants) Height cm Depth cm Width cm SPECIFICATIONS Weight... N, E and K-grade: Not exceeding 560g (without Mass Storage Kit fitted)... RA-grade: Not exceeding 660g (without Mass Storage Kit fitted) NOTE: Several variants of the VX 91x/01x are supplied, with different heat sinks. While 560g represents the heaviest combination for N, E and K-grades, other permutations may give a lighter overall weight. VX 91x/01x A-5

100 SPECIFICATIONS A.6 Electrical Specification Variant VX 915/011 VX 913/012 Activity Level 5 CPU Cores Operating Frequency +5V 4 +5%/-3% Typical 6 Maximum 2, 7 +12V -12V ±5% max 2,7 ±5% max 2, 7 A 2.8 GHz 9.5A 16.3A B 2.8 GHz 9.0A 14.0A C 2.1 GHz 8.0A 15.2A 0.0A 0.0A D 2.1 GHz 7.5A 9.8A 1.2 GHz 6.5A 8.4A A 3.0 GHz 8.0A 13.2A B 3.0 GHz 7.5A 9.5A C 2.5 GHz 7.5A 13.0A 0.0A 0.0A D 2.5 GHz 7.0A 8.3A 0.8 GHz 5.8A 6.9A Table A-4 Voltage and Current Requirements 1. These figures are for a board with 8 or 16 Gbytes DRAM and with no Mass Storage Kit or PMC Modules fitted. 2. Maximum currents during startup are below the Maximum figures stated above for the particular processor operating frequency. 3. ±12V supplies are provided for the PMC interface. These supplies do not need to be present if the PMC module does not require them. Current requirements will be those of the fitted PMC module. 4. If VCC_STANDBY is connected to 5.0V the current drawn is a maximum of 0.17mA 5. Key to Activity Level: A = Concurrent intensive activity on all CPU cores, graphics engine and DRAM with processor Turbo mode enabled B = Intensive activity on all CPU cores with processor Turbo mode enabled C = Concurrent intensive activity on all CPU cores, graphics engine and DRAM with processor Turbo mode disabled D = Intensive activity on all CPU cores with processor Turbo mode disabled, current figures provided for both maximum and minimum processor frequencies. For the above intensive activity implies running a processor and graphics (if applicable) benchmark program. 6. Typical figures are the average current requirement whilst maintaining a 50% program execution load on all processor cores and, if applicable, a 60% load on the graphics core with the board operating at an ambient temperature of 25 C. For most applications the typical figures can be used to calculate the sustained power requirements. 7. Maximum figures are the current requirements that may occur for periods of at least 100ms duration with a very high level of activity on the functions indicated in the A to D class of activity level with the board at the maximum operating ambient temperature. For activity levels B and D the maximum +5V current can increase by up to 1.8A with an application that generates a very high level of DRAM activity, assuming the same high level of processor activity is maintained. 8. Add 0.1A to the above figures for each connected Ethernet interface with a link established. 9. Add 0.7A (typical) and 1.2 A (maximum) to the above figures if the VPX VITA 41.4 PCIe interfaces are utilised. CAUTION: The high supply current requirements of these boards mean that all the available +5V pins on the VME P1 connector must be utilized. It is therefore strongly recommended that this board is installed only in backplanes with 5- row P1 and (at least) 3-row P2 connectors supplying +5V power through all the pins defined in the VME64 specifications. Failure to comply with this recommendation may result in the board malfunctioning or, in extreme cases, board or system damage. NOTE: RA Variants use the 2.5 GHz 2-core processors. A-6 VX 91x/01x

101 SPECIFICATIONS Variant VX 91x/01x (All Variants) Table A-5 Max power dissipation per PMC or XMC module Max 3.3V per PMC or XMC module Max 5V per PMC or XMC module Max 5V for both PMC/XMC sites combined Max +12V per PMC or XMC module Max -12V per PMC or XMC module 20W 4A 4A 6A / 8A * 0.5A 0.5A Maximum Current Requirements for PMC/XMC modules * 6A for 4-core 2.1 GHz processor and 8A for 2-core 2.5 GHz processors. The limit is based on the VITA 1.7 P1 and P2 +5V maximum current rating of 18A minus the board s worst case typical current requirement or total 40W maximum power dissipation for both sites. VX 91x/01x A-7

102 SPECIFICATIONS A.7 Connectors P3 P4 J16 J13 J15 J11 J23 J25 J21 J14 J12 J22 P2 P0 P1 Figure A-1 Connector Layout Component Side PMC 2 PMC 1 Console (P4) Ethernet (P3) Figure A-2 Connector Layout Front Panel A-8 VX 91x/01x

103 SPECIFICATIONS A.7.1 VME Interface P1 VME interface P1 is via a 160-pin connector with signals assigned as follows: Pin Row Z Row A Row B Row C Row D 1 NC D00 BBSY# D08 VCC 2 GND D01 BCLR# D09 GND 3 NC D02 ACFAIL# D10 NC 4 GND D03 BG0IN# D11 NC 5 NC D04 BG0OUT# D12 NC 6 GND D05 BG1IN# D13 NC 7 NC D06 BG1OUT D14 NC 8 GND D07 BG2IN# D15 NC 9 NC GND BG2OUT# GND GAP# 10 GND SYSCLK BG3IN# SYSFAIL# GA0# 11 NC GND BG3OUT# BERR# GA1# 12 GND DS1# BR0# SYSRESET# NC 13 NC DS0# BR1# LWORD# GA2# 14 GND WRITE# BR2# AM5 NC 15 NC GND BR3# A23 GA3# 16 GND DTACK# AM0 A22 NC 17 NC GND AM1 A21 GA4# 18 GND AS# AM2 A20 NC 19 NC GND AM3 A19 NC 20 GND IACK# GND A18 NC 21 NC IACKIN# NC A17 NC 22 GND IACKOUT# NC A16 NC 23 NC AM4 GND A15 NC 24 GND A07 IRQ7# A14 NC 25 NC A06 IRQ6# A13 NC 26 GND A05 IRQ5# A12 NC 27 NC A04 IRQ4# A11 NC 28 GND A03 IRQ3# A10 NC 29 NC A02 IRQ2# A09 NC 30 GND A01 IRQ1# A08 NC 31 NC -12V VCC_STANDBY +12V GND 32 GND +5V +5V +5V VCC Table A-6 VME Interface P1 - Pin-out VX 91x/01x A-9

104 SPECIFICATIONS A.7.2 Auxiliary Connection P2 Auxiliary connection P2 is via a 160-pin, or optionally 96-pin connector with signals assigned as follows: Pin Column Z Column A Column B Column C Column D 1 TXD2#_TX2# PMC_IO(2) VCC PMC_IO(1) RTM_3V3 2 GND PMC_IO(4) GND PMC_IO(3) SATA4_TX+ 3 RXD2#_RX2# PMC_IO(6) VME_RETRY# PMC_IO(5) SATA4_TX- 4 GND PMC_IO(8) VME_A(24) PMC_IO(7) GND 5 RTS2_TX2 PMC_IO(10) VME_A(25) PMC_IO(9) SATA4_RX- 6 GND PMC_IO(12) VME_A(26) PMC_IO(11) SATA4_RX+ 7 CTS2_RX2 PMC_IO(14) VME_A(27) PMC_IO(13) GND 8 GND PMC_IO(16) VME_A(28) PMC_IO(15) SATA5_TX+ 9 DTR2 PMC_IO(18) VME_A(29) PMC_IO(17) SATA5_TX- 10 GND PMC_IO(20) VME_A(30) PMC_IO(19) GND 11 DSR2 PMC_IO(22) VME_A(31) PMC_IO(21) SATA5_RX- 12 GND PMC_IO(24) GND PMC_IO(23) SATA5_RX+ 13 DCD2 PMC_IO(26) VCC PMC_IO(25) GND 14 GND PMC_IO(28) VME_D(16) PMC_IO(27) USBP9+ 15 RI2 PMC_IO(30) VME_D(17) PMC_IO(29) USBP9-16 GND PMC_IO(32) VME_D(18) PMC_IO(31) GND 17 TM_RST# PMC_IO(34) VME_D(19) PMC_IO(33) USBP8-18 GND PMC_IO(36) VME_D(20) PMC_IO(35) USBP8+ 19 DVI_DDCCK PMC_IO(38) VME_D(21) PMC_IO(37) SPKR 20 GND PMC_IO(40) VME_D(22) PMC_IO(39) VCC_USB9 21 DVI_DDCDT PMC_IO(42) VME_D(23) PMC_IO(41) VCC_USB8 22 GND PMC_IO(44) GND PMC_IO(43) GND 23 DVI_HPD PMC_IO(46) VME_D(24) PMC_IO(45) DVI_D0+ 24 GND PMC_IO(48) VME_D(25) PMC_IO(47) DVI_D0-25 GPIO0 PMC_IO(50) VME_D(26) PMC_IO(49) DVI_D1+ 26 GND PMC_IO(52) VME_D(27) PMC_IO(51) DVI_D1-27 GPIO1 PMC_IO(54) VME_D(28) PMC_IO(53) DVI_D2+ 28 GND PMC_IO(56) VME_D(29) PMC_IO(55) DVI_D2-29 GPIO2 PMC_IO(58) VME_D(30) PMC_IO(57) DVI_CLK+ 30 GND PMC_IO(60) VME_D(31) PMC_IO(59) DVI_CLK- 31 GPIO3 PMC_IO(62) GND PMC_IO(61) GND 32 GND PMC_IO(64) VCC PMC_IO(63) VCC Table A-7 Auxiliary Connector P2 - Pin-out NOTE: The serial I/O TX2 and RX2 pins act either as single-ended signals for RS232 or differential signals for RS485. CAUTION: RTM_3V3 is a 3.3V supply to the RTM from the VX 91x/01x board and must not connect to the backplane 3.3V power rail. NOTE: Columns Z and D connections are not supported with 96-pin connectors. A-10 VX 91x/01x

105 A.7.3 VXS Connector P0 SPECIFICATIONS VXS connection P0 is via a 105-way (7-row x 15-position) high speed differential connector. It carries backplane PCIe (VITA 41.4) as well as SerDes (VITA 41.6) interfaces on both Port A and Port B. Table A-8 shows the signal assignments conforming to the mapping defined in the VITA 41.4 and VITA 41.6 standards. Pin Row G Row F Row E Row D Row C Row B Row A 1 NC GND PA_TX0- PA_TX0+ GND PA_RX0- PA_RX0+ 2 GND PA_TX1- PA_TX1+ GND PA_RX1- PA_RX1+ GND 3 NC GND PA_TX2- PA_TX2+ GND PA_RX2- PA_RX2+ 4 GND PA_TX3- PA_TX3+ GND PA_RX3- PA_RX3+ GND 5 USB_ PWREN# GND SA_TX- SA_TX+ GND SA_RX- SA_RX+ 6 GND SATA0 SATA0 SATA0 SATA0 GND _TX- _TX+ _RX- _RX+ GND 7 ETH_ SATA1 SATA1 SATA1 SATA1 GND GND ACT# _TX- _TX+ _RX- _RX+ 8 GND USBP3- USBP3+ GND USBP2- USBP2+ GND 9 USB_OC# GND ETH0 ETH0 ETH0 ETH0 GND _DB- _DB+ _DA- _DA+ 10 GND ETH0 ETH0 ETH0 ETH0 GND _DD- _DD+ _DC- _DC+ GND 11 PEN# GND SB_TX- SB_TX+ GND SB_RX- SB_RX+ 12 GND PB_TX0- PB_TX0+ GND PB_RX0- PB_RX0+ GND 13 - GND PB_TX1- PB_TX1+ GND PB_RX1- PB_RX1+ 14 GND PB_TX2- PB_TX2+ GND PB_RX2- PB_RX2+ GND 15 - GND PB_TX3- PB_TX3+ GND PB_RX3- PB_RX3+ Table A-8 VXS Connector P0 - Pin-out NOTE: This connector is a build time option and is not available on all variants. - Refer to VITA 41.0 Pins 1-4 and in rows A-F are defined in VITA Pins 5 and 11 in rows A-F are defined in VITA VX 91x/01x A-11

106 SPECIFICATIONS A.7.4 Console Connector P4 Connector P4 provides access to the VGA video, COM1 serial port and USB0/1 port interfaces via a female 60-way Molex LFH Matrix 50 connector, with signals assigned as follows: Pin Signal Pin Signal Pin Signal Pin Signal 1 RED1 RTN 30 TMDS1 D0-31 TMDS1 CK+ 60 GREEN1 RTN 2 RED1 29 TMDS1 D0+ 32 TMDS1 CK- 59 GREEN1 3 BLUE1 28 TMDS1 D1-33 TMDS1 D0 RTN 58 OP EN- 4 BLUE1 RTN 27 TMDS1 D1+ 34 TMDS1 D1 RTN 57 TMDS1 CK RTN 5 VCC 1 26 TMDS1 D2-35 TMDS1 D2 RTN 56 HSYNC 1 6 SCL 1 25 TMDS1 D2+ 36 HPD 1 55 VSYNC 1 7 SDA 1 24 COM1 DCD 37 COM1 RTS 54 SYNC1 RTN 8 GND 23 COM1 DTR 38 COM1 CTS 53 COM1 DSR 9 SDA 2 22 COM1 RXD- 39 COM1 TXD- 52 USB0 RTN 10 SCL 2 21 TMDS2 D2-40 HPD 2 51 USB0 VCC 11 VCC 2 20 TMDS2 D2+ 41 TMDS2 D2 RTN 50 COM1 RI 12 USBD0+ 19 TMDS2 D1-42 TMDS2 D1 RTN 49 TMDS2 CK RTN 13 USBD0-18 TMDS2 D1+ 43 TMDS2 D0 RTN 48 NC 14 USBD1+ 17 TMDS2 D0-44 TMDS2 CK- 47 USB1 VCC 15 USBD1-16 TMDS2 D0+ 45 TMDS2 CK+ 46 USB1 RTN Table A-9 Console Connector P4 - Pin-out NOTE: Pin USB0 VCC and pin USB1 VCC have a short circuit current limit of 2.1A max Pin 16 Pin 15 Pin 1 Pin 30 Figure A-3 Pin 45 Pin 46 Pin 60 Pin 31 Console Connector P4 - Pin Map NOTE: Concurrent Technologies supply a splitter cable to access the various interfaces (part number CB 60D/125-00). For detailed cable and pin-out information for each interface see the cable datasheet, available from our website NOTE: Splitter cables designed for the VESA Multi-Display Interface Standard may be used in place of the CB 60D/ splitter cable, although they will not provide connections to the serial and USB ports. If a VESA Multi-Display Interface cable is fitted the VX 91x/01x will detect it and disable (tri-state) the serial and USB connections to prevent any damage to the VX 91x/01x or connected devices. Only cables that interface to digital video (TMDS) interface #1 or #2 or analog video (VGA) #1 should be used. A-12 VX 91x/01x

107 A.7.5 PMC Site Connectors SPECIFICATIONS Signal assignments on the PMC connectors are shown in Table A-10, Table A-11, Table A-12 and Table A-13. Pin Signal Pin Signal 1 NC 2-12V 3 GND 4 INTA# 5 INTB# 6 INTC# 7 BUSMODE#1 8 +5V 9 INTD# 10 NC 11 GND V 13 CLK 14 GND 15 GND 16 GNT# 17 REQ# 18 +5V 19 V (I/O) 20 AD(31) 21 AD(28) 22 AD(27) 23 AD(25) 24 GND 25 GND 26 C/BE(3)# 27 AD(22) 28 AD(21) 29 AD(19) 30 +5V 31 V (I/O) 32 AD(17) 33 FRAME# 34 GND 35 GND 36 IRDY# 37 DEVSEL# 38 +5V 39 PCIXCAP 40 LOCK# 41 SDONE# 42 SBO# 43 PAR 44 GND 45 V (I/O) 46 AD(15) 47 AD(12) 48 AD(11) 49 AD(09) 50 +5V 51 GND 52 C/BE(0)# 53 AD(06) 54 AD(05) 55 AD(04) 56 GND 57 V (I/O) 58 AD(03) 59 AD(02) 60 AD(01) 61 AD(00) 62 +5V 63 GND 64 REQ64# V(I/O) = 3.3V # denotes active low pulled high via 4.7kΩ resistor, pulled high via 10kΩ resistor. pulled low via 4.7kΩ resistor. Table A-10 PMC Connectors J11 and J21 - Pin-out VX 91x/01x A-13

108 SPECIFICATIONS Pin Signal Pin Signal 1 +12V 2 NC 3 NC 4 NC 5 NC 6 GND 7 GND 8 NC 9 NC 10 NC V V 13 RST# 14 GND V 16 GND 17 NC 18 GND 19 AD(30) 20 AD(29) 21 GND 22 AD(26) 23 AD(24) V 25 IDSEL 26 AD(23) V 28 AD(20) 29 AD(18) 30 GND 31 AD(16) 32 C/BE(2)# 33 GND 34 NC 35 TRDY# V 37 GND 38 STOP# 39 PERR# 40 GND V 42 SERR# 43 C/BE(1)# 44 GND 45 AD(14) 46 AD(13) 47 M66EN 48 AD(10) 49 AD(08) V 51 AD(07) 52 NC V 54 NC 55 PMC-RSVD 56 GND 57 PMC-RSVD 58 EREADY 59 GND 60 NC 61 ACK64# V 63 GND V # denotes active low. pulled high via 4.7kΩ resistor, pulled high via 10kΩ resistor. pulled low via 4.7kΩ resistor. Table A-11 PMC Connectors J12 and J22 - Pin-out NOTE: REQ B# and GNT B# are provided for use by dual-function PMC modules or Processor-PMC modules on J12 and J22. A-14 VX 91x/01x

109 SPECIFICATIONS Table A-12 Pin Signal Pin Signal 1 NC 2 GND 3 GND 4 C/BE(7)# 5 C/BE(6)# 6 C/BE(5)# 7 C/BE(4)# 8 GND 9 V(I/O) 10 PAR64 11 AD(63) 12 AD(62) 13 AD(61) 14 GND 15 GND 16 AD(60) 17 AD(59) 18 AD(58) 19 AD(57) 20 GND 21 V(I/O) 22 AD(56) 23 AD(55) 24 AD(54) 25 AD(53) 26 GND 27 GND 28 AD(52) 29 AD(51) 30 AD(50) 31 AD(49) 32 GND 33 GND 34 AD(48) 35 AD(47) 36 AD(46) 37 AD(45) 38 GND 39 V(I/O) 40 AD(44) 41 AD(43) 42 AD(42) 43 AD(41) 44 GND 45 GND 46 AD(40) 47 AD(39) 48 AD(38) 49 AD(37) 50 GND 51 GND 52 AD(36) 53 AD(35) 54 AD(34) 55 AD(33) 56 GND 57 V(I/O) 58 AD(32) 59 NC 60 NC 61 NC 62 GND 63 GND 64 NC V(I/O) = 3.3V or 5V PMC Connectors J13 and J23 - Pin-out VX 91x/01x A-15

110 SPECIFICATIONS Pin Signal Pin Signal 1 I/O 1 2 I/O 2 3 I/O 3 4 I/O 4 5 I/O 5 6 I/O 6 7 I/O 7 8 I/O 8 9 I/O 9 10 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 64 Table A-13 PMC Connector J14 - Pin-out NOTE: Signals I/O 1 and I/O 3, I/O 2 and I/O 4 etc are routed as differential pairs to P2 connector. The nominal differential impedance is 100Ω. A-16 VX 91x/01x

111 A.7.6 XMC Connectors J15 and J25 SPECIFICATIONS Pin Row A Row B Row C Row D Row E Row F 1 PET0p0 PET0n0 +3.3V PET0p1 PET0n1 +5V 2 GND GND PULL DOWN GND GND RESET# 3 PET0p2 PET0n2 +3.3V PET0p3 PET0n3 +5V 4 GND GND PULL DOWN GND GND PULL UP 5 PET0p4 PET0n4 +3.3V PET0p5 PET0n5 +5V 6 GND GND PULL UP GND GND +12V 7 PET0p6 PET0n V PET0p7 PET0n7 +5V 8 GND GND PULL UP GND GND -12V 9 NC NC NC NC NC NC 10 GND GND NC GND GND GA0 11 PER0p0 PER0n0 MBIST# PER0p1 PER0n1 +5V 12 GND GND GA1 GND GND PRSNT# 13 PER0p2 PER0n V PER0p3 PER0n3 +5V 14 GND GND GA2 GND GND MSDA 15 PER0p4 PER0n4 NC PER0p5 PER0n5 +5V 16 GND GND PULL UP GND GND MSCL 17 PER0p6 PER0n6 NC PER0p7 PER0n7 NC 18 GND GND NC GND GND NC 19 REFCLK+ REFCLK- NC WAKE# NC NC Table A-14 XMC Connector J15 and J25 - Pin-out NOTE: The terminology in the above table matches that used in the XMC specification, VITA The PET0xx signals are used to receive data from the XMC module (i.e. they are the XMC module s transmit signals). The PER0xx signals are used to send data to the XMC module (i.e. they are the XMC module s receive signals). VX 91x/01x A-17

112 SPECIFICATIONS A.7.7 XMC Interface J16 XMC site 1 supports the XMC I/O connector which is used as an alternative connection to P0 VITA 41.4 connections. Table A-15 shows the connections to the P0 signals; these are not connected directly but pass through AC coupling capacitors and active repeaters within the VXS interface multiplexer. Pin Row A Row B Row C Row D Row E Row F 1 PA_TX0+ PA_TX0- NC PA_TX1+ PA_TX1- NC 2 GND GND NC GND GND NC 3 PA_TX2+ PA_TX2- NC PA_TX3+ PA_TX3- NC 4 GND GND NC GND GND NC 5 PB_TX0+ PB_TX0- NC PB_TX1+ PB_TX1- NC 6 GND GND NC GND GND NC 7 PB_TX2+ PB_TX2- NC PB_TX3+ PB_TX3- NC 8 GND GND NC GND GND NC 9 NC NC NC NC NC NC 10 GND GND NC GND GND NC 11 PA_RX0+ PA_RX0- NC PA_RX1+ PA_RX1- NC 12 GND GND NC GND GND NC 13 PA_RX2+ PA_RX2- NC PA_RX3+ PA_RX3- NC 14 GND GND NC GND GND NC 15 PB_RX0+ PB_RX0- NC PB_RX1+ PB_RX1- NC 16 GND GND NC GND GND NC 17 PB_RX2+ PB_RX2- NC PB_RX3+ PB_RX3- NC 18 GND GND NC GND GND NC 19 NC NC NC NC NC NC Table A-15 XMC Interface J16 - Pin-out NOTE: This connector is a build time option and is not available on all variants. A-18 VX 91x/01x

113 SPECIFICATIONS A.7.8 Ethernet Interface P3 Ethernet interface P3 uses an 8-way RJ45 connector with signals assigned as follows: Table A-16 Pin No. Signal Name 1 ETH_DA 2 ETH_DA# 3 ETH_DB 4 ETH_DC 5 ETH_DC# 6 ETH_DB# 7 ETH_DD 8 ETH_DD# Ethernet Interface P3 - Pin-out Pin 1 Pin 8 Figure A-4 Ethernet Interface P3 - Pin Map VX 91x/01x A-19

114 SPECIFICATIONS This page is intentionally unused. A-20 VX 91x/01x

115 B.1 Introduction B REAR TRANSITION MODULES This section details Rear Transition Modules (RTMs) available for use with the VX 91x/01x. Each RTM provides a means of connecting interface cables to the rear I/O of the VX 91x/01x. All RTMs utilize a 5-row P2 for rear I/O connection. For a 3-row backplane only the PMC rear I/O interface is available. An overview of each RTM is given with references to the pin-out tables for each of the connectors identified. B.2 RTM List Currently only the AD VP2/027 RTM is available for use with the VX 91x/01x. This RTM can be supplied in a number of build variants, the key differences being whether a P0 connector is fitted and the type of optional 1.8-inch SATA disk drive kit fitted. Contact your sales representative for order details of the different variants. The presence of the RP0 connector affects the types of I/O interfaces that are supported and this will be clearly identified in the following sections. VX 91x/01x B-1

116 REAR TRANSITION MODULES B.3 AD VP2/027 The AD VP2/027 is a 160-way P2 plus optional RP0 RTM. This RTM requires one slot width and a minimum of 115 mm behind the backplane. B.3.1 Layout Figure B-1 shows the locations of the connectors, headers and switches and Figure B-2 shows the switch settings. P7 P2 P3 S2 S3 P4 P6 J4 RP0 J3 S1 LK1 Pin 1 J2 P8 LK1 P5 P1 Figure B-1 AD VP2/027 RTM - Connectors and Switches B-2 VX 91x/01x

117 B.3.2 Pin-out Tables REAR TRANSITION MODULES Connector Reference Interface Removed when no RP0 connector Pin-out Table P7 esata A and esata B (SATA 4 and SATA 5) No Table B-9 P2 DB9 Serial COM2 port No Table B-3 P3 USB C, connected to VX 91x/01x USB Port 2 Yes P4 USB B, connected to VX 91x/01x USB Port 9 No Table B-1 P6 USB A, connected to VX 91x/01x USB Port 8 No J4 Ethernet RJ45, connected to VX 91x/01x ETH 0 Yes Table B-2 J3 PMC I/O No Table B-5 P1 DVI-D No Table B-6 P5 GPIO and RESET No Table B-4 P8 USB Flash module, connected to VX 91x/01x USB Port 3 Yes Table B-10 S1 SATA 4 and SATA 5 No S3 SATA 0 and SATA 1 Yes Table B-8 S2 1.8-inch SATA drive (SATA 4) No - LK1 Legacy Speaker No Table B-7 VX 91x/01x B-3

118 REAR TRANSITION MODULES B.3.3 RTM Switch Settings Switches on SW2 configure the routing of the P2 SATA 4 and SATA 5 interfaces. Figure B-2 shows the settings for the various routing options. The GPIO switches shown in Figure B-2 provide the facility to pull the GPIO signals low and hence provide (up to) four user defined switches when the GPIO is defined as an input. SW2-1 and SW2-2 - SATA 4 Config OFF ON SATA 4 to esata A OFF ON OFF ON SW2-3 - SATA 5 Config OFF ON OFF ON SATA 4 to S1 lower SATA 4 to 1.8 inch drive SATA 5 to esata B SATA 5 to S1 upper OFF SW1 - GPIOs ON GPIO0 GPIO1 GPIO2 GPIO3 OFF - GPIO function ON - GPIO function forced low Figure B-2 AD VP2/027 RTM Switch Settings B-4 VX 91x/01x

119 B.3.4 USB NAND Flash Module REAR TRANSITION MODULES The AD VP2/027 has the option to have a USB NAND Flash module (Sales part no. AD 235/001) installed, according to the following procedure: 1. Locate USB NAND Flash module position and P8 connector as shown in Figure B-3 below. 5mm Spacer M3 Nut Module P8 P8 Connector Outline position of USB NAND Flash module M3 Screw Figure B-3 Location of USB NAND Flash Module and P8 connector 3. Insert the M3 screw into the M3 hole from the bottom side of the board and attach the 5mm spacer to the screw on the top-side of the board. 4. Align the connector on the underside of the USB NAND Flash module with connector P8 on the main board. 5. Press down the USB NAND Flash module until it is firmly seated. 6. Secure the USB NAND Flash module to the board using the single M3 nut provided. Avoid over tightening the nut. NOTE: If the board is likely to be subjected to mechanical vibration consider applying a suitable thread lock compound to the screw thread. VX 91x/01x B-5