P375 Data Sheet & Applications Notes. PG3A Pattern Generator P375 Variable Universal probe April Rev 1.0

Transcription

1 P375 Data Sheet & Applications Notes PG3A Pattern Generator P375 Variable Universal probe April Rev 1.0

2 PG3A Pattern Generator P375 Variable Universal probe 1.0 General: The P375 probe is a variable probe in the sense that the logic high (Voh) and the logic low (Vol) output voltages are independently adjustable on a channel-by-channel basis, providing the most flexibility possible. Both the Voh and Vol levels can be set to any voltage between volts and volts. The P375 supports all modern I/O standards including TTL, LVCMOS, LVDS, PECL, NECL, HSTL, SSTL, and CML including all common variations of these standards. It features a 50-ohm series output impedance. The probe supports clock rates up to 300 MHz and data rates as high as 600 Mbps/pin. In addition to the native delay adjust capability inherent in a PG3A, this probe allows the user to adjust the delay of each channel over a small range in 20 ps steps so that the probe can be perfectly timed into a user system. The probe supports both high speed drive and low speed systems via two leadset options: a high-speed Mictor-terminated coaxial lead set and a more traditional square pin leadset. Both types of leadsets are shipped with the unit as standard accessories. The probe also provides a slew rate selection to enhance signal integrity. The probe provides up to 16 single-ended data outputs, a clock, and a strobe. It also supports differential operation on a pin-pair by pin-pair basis. The PGApp software makes the linking of two output channels to form a differential pin pair nearly invisible to the user. The probe provides output inhibits on a byte basis under pattern control as well as byte inhibits directly to the probe for hardware output disable. The threshold at which the inhibits trip is adjustable. Almost all of the user-adjustments to the probe can be changed in real-time while the pattern is being output. This enhances the speed at which the PG and probe can be used for parametric testing especially when coupled with the PPI interface.

3 2.0 Requirements: The P375 probe works with all current PG3AMod and PG3ACab models. The instrument firmware must be V1.2 or higher. The PGApp software must be V or higher. Updated versions of the instrument firmware and the PGApp software can be freely downloaded from the PG3A website:

4 3.0 P375 Pinouts The P375 probe features outputs running at up to 300 MHz. To preserve the signal integrity associated with the fast edge rates (2V/nS) of the output drivers, we have chosen to make the connection from the probe to the user system via a AMP Mictor connector and a high-speed, multi-coax ribbon cable. We also support a traditional square pin connector in parallel. The pinout for the Mictor connector is as follows. We use the AMP numbering convention (as opposed to the Tektronix numbering convention found in some Tektronix documentation): Pin 1: Low Byte Inhibit input Pin 3: Low Byte Inhibit input Pin 5: Clock_p Pin 7: D1_p Pin 9: D1_n Pin 11: D3_p Pin 13: D3_n Pin 15: D5_p Pin 17: D5_n Pin 19: D7_p Pin 21: D7_n Pin 23: D9_p Pin 25: D9_n Pin 27: D11_p Pin 29: D11_n Pin 31: D13_p Pin 33: D13_n Pin 35: D15_p Pin 37: D15_n Pin 2: Strobe_p Pin 4: Strobe_n Pin 6: Clock_n Pin 8: D0_p Pin 10: D0_n Pin 12: D2_p Pin 14: D2_n Pin 16: D4_p Pin 18: D4_n Pin 20: D6_p Pin 22: D6_n Pin 24: D8_p Pin 26: D8_n Pin 28: D10_p Pin 30: D10_n Pin 32: D12_p Pin 34: D12_n Pin 36: D14_p Pin 38: D14_n The square pin connections to the probe are shown on a label on the probe.

5 Data0 through Data15 are the pattern data outputs. Strobe is the strobe output. Clock is the clock output. Inhibit0 is the input that disables (tristates) the data outputs 7 through 0 when high. Inhibit1 is the input that disables (tristates) the data outputs 15 through 8 when high. Note that the connector on the front of the unit has two rows. The signals mentioned above are carried on the upper row of contacts. Every pin of the lower row of contacts carries ground EXCEPT the one under the Clock and Strobe pins 1. There is no necessity to connect each ground wire to the system-under-test (SUT). However, to maximize signal integrity a user may wish to make all the connections. Also, if the load draws significant current, additional grounds again will help preserve signal integrity. The two inhibit inputs are a user-settable level. There is an independent inhibit for each data byte. The probe data byte outputs are enabled when these are no-connect or pulled low. The probe does not drive the data byte outputs when the inhibit pin is driven high. The probe expects the user system to be differentially terminated in a purely resistive 100 ohms. All specifications assume this resistive termination. 1 This is to support differential output. During differential output on the data pins, those pins are paired even and odd. Note that the lack of grounds under the clock and strobe outputs is different than the P370 series of probe.

6 4.0 Disassembly/Reassembly instructions: These disassembly instructions are provided so that the user can attach or detach the Mictor output cable. The unit should not be disassembled for any other reason. To disassemble the unit, start by removing the power plug from the power jack. Remove the 4 Phillips Head screws from the sides of the case (2 each side) and gently spread the top part of the case away from one side while forcing it up past the base. The top of the case should come free. The Mictor cable can be installed with either connector on either end. The user should install the Mictor cable in the direction that allows the cable to exit the cabinet without being bent. Be careful the connector can be damaged by trying to force the connector into the socket in the wrong direction. Once the connector starts to slide into the socket, make sure it is fully engaged by visual inspection. Once the unit is open, be very careful to not let any object (including fingers) touch any of the internal component leads. This unit is particularly susceptible to static damage due to the extensive use of small-geometry, extremely high-speed semiconductor devices. Reassembly is the reverse of the disassembly process. It is very important to get the circuit board correctly aligned with the side case slot and getting the case tangs seated into the case slots before installing the screws.

7 5.0 Electrical specification for the P375 probe All specifications assume no output load unless otherwise noted. All specifications are at 25 degrees Celsius ambient temperature, 30 minutes for stabilization of both the PG and the probe. The user can adjust the time skews shown down to zero +/- 20pS. Characteristic Specification Notes Output Risetime Selections unloaded ~1V/nS, ~2V/nS 50 ohm load ~0.5V/nS, ~1V/nS Output Enable time 5 ns typ Output Disable time 5 ns typ to +/- 10 ua Skew, nybble +/- 300pS Uncalibrated, 4 consecutive bits starting with D0. Can be user-calibrated to +/- 20pS Skew, worst case, probeprobe +/- 600pS Uncalibrated, Any bit in any probe to any other bit in any other probe. Can be user-calibrated to +/- 20pS Clock before data 50ps 400pS typical Within one probe, all bits Output impedance 48.5 ohms +/- 10% Output Characteristic Min Max Output voltage high V V +/- 25mV of set point Output voltage low V V +/- 25 mv of set point Noise 10mVp-p Output voltage V 40mVp-p Output voltage V Weight 710 grams Approximate, without external power supply Overall Dimensions Length: 145mm, Width approximate 125mm, Height: 75mm External power supply 24 volts, 2 Amps, typical provided

8 Application information I/O standards: The P375 supports all common I/O standards. It also features a 48.5 ohm series output impedance that cannot be bypassed. In order to properly support all common I/O standards, in some cases, the output voltage setting for the probe must be adjusted in order to accommodate this inherent output impedance and generate the desired output voltage at the user system input pin. The following table presents each common I/O standard in various configurations (DCcoupled only), the desired voltage swing and the settings required to obtain the desired voltage swing at the user input to the system. Before implementing any particular I/O standard, please read the Issues section associated with it. Before using any data in this table, the user should verify that the data is correct for the user s situation. Standard Desired Voh Desired Vol Set Voh to: Set Vol to Load TTL 5 V 0 V V V none CMOS 3.3 V 0 V V V none NECL 10k -0.9 V -1.8 V V V 50 ohms to -2.0 volts NECL 100k V V V V 50 ohms to -2.0 volts PECL (+5.0 Vcc) LVPECL (+3.3Vcc) V V V V 50 ohms to 3.0 volts V V V V 50 ohms to 1.3 volts LVDS (vcm = 1.25V) HSTL class I 1.8 V HSTL class II 1.8 V HSTL class I 1.5V HSTL class II 1.5V HSTL class I 1.2V HSTL class II 1.2V V V V V 100 ohm differential 1.8 V 0 V V V 50 ohms to 0.90V* 1.8 V 0 V V V 2 x 50 ohms to 0.90V* 1.5 V 0 V V V 50 ohms to 0.75V* 1.5 V 0 V V V 2 x 50 ohms to 0.75V* 1.2 V 0 V V V 50 ohms to 0.60V* 1.2 V 0 V V V 2 x 50 ohms to 0.60 V* * Note that the user system must be terminated as indicated else the probe might damage the user system.

9 Standard Desired Voh Desired Vol Set Voh to: Set Vol to Load SSTL2 class I 2.5V SSTL2 class II 2.5V SSTL18 class I 1.8V SSTL18 class II 1.8V 2.09 V V V V 50 ohms to 1.25V V V V V 2 x 50 ohms to 1.25V 1.5 V 0.3 V V V 50 ohms to 0.9 V 1.35 V 0.45 V V V 2 x 50 ohms to 0.9V CML, 2.5V 2.5V 2.1V 2.5V 1.7V 50 ohms to 2.5V

10 Output Voltage Model: The configuration that the table is based on is an ideal voltage source with a series resistance driving a user load, often resistively terminated to an ideal termination voltage. Based on this description, the equation for the driver voltage necessary to achieve the desired terminal voltage in the user system is: VoNecessary = VoDesired + (Rs/Rt)*(VoDesired Vtt) where: VoDesired is the voltage desired at the input pin of the device being driven. VoNecessary is the voltage the P375 must be programmed to get to the Vo desired in the given configuration. Rs is the driver source resistance. By spec, the P375 has 48.5 ohms series resistance. Rt is the termination resistance in the given user configuration. Vtt is the termination voltage in the given user configuration. TTL/CMOS: Be sure to adjust the voltage settings if there is a significant DC load. For example, if the output is loaded with 4.7kohms to ground, this would cause about 1 ma to flow through the output source resistor (48.5 ohms) and cause about a 50mV drop. If the user must have exactly volts on this output, the Voh should be set to volts. Negative ECL 10k & 100k series (NECL) If unterminated, the input voltage presented to the user system will be slightly higher than the supply voltage. The user should make sure that either the termination is applied or that the system will not be damaged in this condition. HSTL, SSTL If unterminated, the logic high input voltage presented to the user system will be slightly higher than the supply voltage and the logic low voltage will be slightly below ground. The user should make sure that either the termination is applied or that the system will not be damaged in this condition.

11 An Output Example: SSTL Class I The ideal SSTL system is shown in the first figure below. The second figure represents the P375 driving an SSTL load. In an SSTL system, the idea is that the ideal driver contributes some nominal output impedance of roughly 25 ohms. This in combination with the additional resistive 25 ohms well matches the transmission line and that the voltage swing at the load is somewhat less that the driver output voltage swing. So, in principle, the P375 drives the SSTL system perfectly. However, some systems may be designed such that the ideal driver is ideal and that the total series resistance is 25 ohms. In this case, the output voltage of the P375 must be increased to compensate for the additional 25 ohms of series impedance it presents to the user system. The case presented in the table is this second case as no adjustment need be made in the first case.