PCI 6140 (HB1) PCI-to-PCI Bridge Data Book

Transcription

1 PCI 6140 (HB1) PCI-to-PCI Bridge Data Book

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3 PCI 6140 (HB1) PCI-to-PCI Bridge Data Book Version 2.0 May 2003 Website: Technical Support: Phone: Fax:

4 2003 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products. PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other brands and names are property of their respective owners. This device is not designed, intended, authorized, or warranted to be suitable for use in medical, life-support applications, devices or systems or other critical applications. PLX Part Number: PCI 6140-AA33PC; Former HiNT Part Number: HB1 Order Number: 6140-SIL-DB-P1-2.0 Printed in the USA, May 2003

5 32-Bit, 33 MHz PCI-to-PCI Bridge The world s first, Patent Pending PCI 6140 provides very low cost, PCI-to-PCI bridging functions. It is optimized to provide PCI masters to achieve optional Zero Clock latency in bursting data through the PCI 6140 PCI-to-PCI bridge. It supports up to 4 Secondary PCI master devices. Optimized for the following applications: PCI Latency Sensitive Systems PCI-Retry Penalty Sensitive Systems PCI Slave Access Intensive bridging functions High Performance and Low cost PCI-to-PCI bridging functions Low Power and PCI ClockRun support Compact PCI with Hot Swap 3.3V, 33 MHz, PCI 2.1 and Compact PCI Hot Swap friendly features PC99 Power Management D3 Cold Wakeup Capable* Very efficient, low power, low cost and easy to use PCI ClockRun support. Optional Zero clock latency when bursting data across PCI 6140 to preserve maximum data rate PCI compatible cycle completion without PCI Retry penalty of a traditional PCI bridge Legacy VGA and Audio IO address support Provides arbitration support for 4 bus masters on secondary interface Supports PCI Type 1 to Type 0 and Type 1 configuration command conversion Supports 1-Clock Latency Mode Synchronous Primary and Secondary Ports 128-pin PQFP package Secondary PCI Primary PCI BUS ENUM# L_STAT PCI 6140 Secondary PCI Secondary PCI Secondary PCI * Supported only in latest revision of PCI 6140, PCI register 82h bits is set to 11110b, indicating PME# assertion possible during D1 state PLX Technology, Inc. All rights reserved. 5

6 History Rev Date Description Eng Chk Mkt Chk Rev 2.0 5/23/03 This release reflects PLX part numbering. Changed S_IDEN signal to reserved Added operating ambient temperature information 2003 PLX Technology, Inc. All rights reserved. 6

7 Contents HISTORY PIN DIAGRAM AND PACKAGE OUTLINE PIN DESCRIPTION PCI 6140 CONFIGURATION REGISTERS Configuration Space Address Map Configuration Register Description Vendor ID Register (RO) (offset 00h) Device ID Register (RO) (offset 02h) Command Register (offset 04h) Primary Status Register (offset 06h) Revision ID Register (RO) (offset 08h) Class Code Register (RO) (offset 09h) Cache Line Size Register (R/W) (offset 0Ch) Latency Timer (R/W) (offset 0Dh) Header Type Register (RO) (offset 0Eh) Secondary Bus Number Register (R/W) (offset 19h) Subordinate Bus Number Register (R/W) (offset 1Ah) Secondary Latency Timer Register (R/W) (offset 1Bh) I/O Base Register (R/W) (offset 1Ch) I/O Limit Register (R/W) (offset 1Dh) Secondary Status Register (offset 1Eh) Memory Base Register (R/W) (offset 20h) Memory Limit Register (R/W) (offset 22h) Prefetchable Memory Base Register (R/W) (offset 24h) Prefetchable Memory Limit Register (R/W) (offset 26h) Capability Pointer(R) (offset 34h) Expansion ROM Base Address(R) (offset 38h) Interrupt Line Register(R/W) (offset 3Ch) Interrupt Pin(R) (offset 3Dh) Bridge Control (offset 3Eh) Subsystem Vendor ID(R/W) (offset 40h) Subsystem ID (R/W) (offset 42h) Secondary Clock Disable Register (R/W) (offset 6Ch) Clock run control Register (R/W) (offset 6Fh) Capability Identifier (R) (offset 80h) Next Item Pointer (R) (offset 81h) Power Management Capabilities(R) (offset 82h) Power Management Control/ Status(R/W) (offset 84h) PMCSR Bridge Support(R) (offset 86h) Capability Identifier (R) (offset 90h) PLX Technology, Inc. All rights reserved. 7

8 Next Item Pointer (R) (offset 91h) Hot Swap Register(R/W) (offset 92h) PCI 6140 mode register (offset C0h) PCI BUS OPERATION (TRANSPARENT MODE) Types of Transactions Address Phase Device Select (LDEV#) Generation Data Phase Write Transactions Read Transactions Configuration Transactions Type 0 Access to PCI Type 1 to Type 0 Translation Type 1 to Type 1 Forwarding Special Cycles Transaction Termination Master Termination Initiated by PCI Master Abort Received by PCI Target Termination Received by PCI Target Termination Initiated by PCI ADDRESS DECODING Address Ranges I/O Address Decoding I/O Base and Limit Address Registers ISA Mode Memory Address Decoding Memory-Mapped I/O Base and Limit Address Registers PCI BUS ARBITRATION Primary PCI Bus Arbitration Secondary PCI Bus Arbitration PLX Technology, Inc. All rights reserved. 8

9 7 ONE CLOCK LATENCY MODE ERROR HANDLING Address Parity Errors Data Parity Errors Configuration Write Transactions to Configuration Space Read Transactions Data Parity Error Reporting Summary System Error (SERR#) Reporting RESET Primary Interface Reset Secondary Interface Reset BRIDGE BEHAVIOR Abnormal Termination (Initiated by Bridge Master) Master Abort PCI Master on Primary Bus Configuration type #1 to type #0 conversion Configuration type #1 to type #1 by-passing Type-0 Configuration cycle filter mode Decoding Secondary master PCI clock run feature TIMING DIAGRAMS Zero-clock Latency Mode Write Transaction in Zero-clock Latency Mode Read Transaction in Zero-clock Latency mode One-Clock Latency Mode Primary to Secondary Write Transaction Primary to Secondary Read Transaction Memory Read Line / Memory Read Multiple Transaction (Block Read Mode) PLX Technology, Inc. All rights reserved. 9

10 12. ELECTRICAL SPECIFICATIONS Maximum Ratings DC Electrical Characteristics AC Specifications V Signal Tolerant Maximum Power CLOCK AND TIMING SPECIFICATION PCI Clock Timing PCI Timing Parameters APPENDIX A. INTERRUPT DEVICE NUMBER BINDING APPENDIX B. SAMPLE APPLICATION SCHEMATICS PLX Technology, Inc. All rights reserved. 10

11 1 Pin Diagram and Package Outline Primary PCI BUS P_CLK P_RST# P_REQ# P_GNT# P_FRAME# P_IRDY# P_TRDY# P_LDEV# P_STOP# P_AD[31:0] P_CBE#[3:0] P_PAR P_SERR# P_PERR# P_IDSEL P_CLKRUN# PCI 6140 S_CLK[3:0] S_FRAME# S_IRDY# S_TRDY# S_LDEV# S_STOP# S_AD[31:0] S_CBE#[3:0] S_PAR S_REQ#[3:0] S_GNT#[3:0] S_RST# S_SERR# S_PERR# S_CLKRUN# S_IDEN Secondary PCI BUS HOT PLUG ENUM# L_STAT S_GNT2# S_GNT3# S_RST# S_IDEN S_CLK3 S_CLK2 S_CLK1 S_CLK0 VSS S_CLKRUN# ENUM# L_STAT P_CLKRUN# P_RST# P_CLK P_GNT# P_REQ# VDD P_AD[31] P_AD[30] P_AD[29] P_AD[28] P_AD[27] P_AD[26] P_AD[25] VSS VDD S_GNT1# S_GNT0# S_REQ3# S_REQ2# S_REQ1# S_REQ0# S_AD[31] S_AD[30] VSS S_AD[29] S_AD[28] S_AD[27] S_AD[26] S_AD[25] S_AD[24] S_CBE3# S_AD[23] VDD S_AD[22] S_AD[21] S_AD[20] S_AD[19] S_AD[18] S_AD[17] S_AD[16] S_CBE[2]# VSS S_FRAME# S_IRDY# S_TRDY# S_LDEV# S_STOP# S_PERR# S_SERR# S_PAR S_CBE[1]# NC 1 PCI VDD 3 P_AD[24] 4 P_CBE[3]# 5 P_IDSEL 6 P_AD[23] 7 P_AD[22] 8 P_AD[21] 9 P_AD[20] 10 P_AD[19] 11 P_AD[18] 12 VSS 13 P_AD[17] 14 P_AD[16] 15 P_CBE[2]# 16 P_FRAME# 17 P_IRDY# 18 P_TRDY# 19 P_LDEV# 20 P_STOP# 21 VDD 22 P_PERR# 23 P_SERR# 24 P_PAR 25 P_CBE[1]# 26 P_AD[15] 27 P_AD[14] 28 P_AD[13] 29 P_AD[12] 30 VSS 31 P_AD[11] 32 P_AD[10] 33 P_AD[9] 34 P_AD[8] 35 P_CBE[0]# 36 P_AD[7] 37 P_AD[6] 38 P_AD[5] VSS VSS S_AD[15] S_AD[14] S_AD[13] S_AD[12] S_AD[11] VDD S_AD[10] S_AD[9] S_AD[8] S_CBE[0]# S_AD[7] S_AD[6] S_AD[5] S_AD[4] VSS S_AD[3] S_AD[2] S_AD[1] S_AD[0] P_AD[0] P_AD[1] P_AD[2] P_AD[3] P_AD[4] VDD PLX Technology, Inc. All rights reserved. 11

12 Notes: 1. Controlling dimensions are in millimeters (mm) 2. Dimension D1/E1 do not include mold protrusion Symbol Min Max A A A B B B B C D D D REF. - E E E REF. - e 0.50 BSC - L L REF - L Zd 0.75 REF - Ze 0.75 REF PLX Technology, Inc. All rights reserved. 12

13 2 Pin Description SIGNAL PIN I/O DESCRIPTION P_CLK 117 I PCI system clock P_RST# 116 I PCI system reset P_REQ# 119 O PCI bus request P_GNT# 118 I PCI bus grant P_FRAME# 15 I/O PCI FRAME, input during slave, output during master. P_IRDY# 16 I/O PCI IRDY, input during slave, output during master. P_TRDY# 17 I/O PCI TRDY, output during slave, input during master. P_LDEV# 18 I/O PCI LDEV, output during slave, input during master. P_STOP# 19 I/O PCI STOP, output during slave, input during master. P_IDSEL 4 I PCI IDSEL signal P_AD[31:0] 121,122, 123,124, 125,126, 127,2,5, 6,7,8,9, 10,12,13, 25,26,27, 28,30,31, 32,33,35, 36,37,40, 41,42,43, 44 I/O PCI address/data. Slave mode: output only during data read phase. Master mode: output during address phase and data write phase. P_CBE#[3:0] 3,14,24, 34 I/O PCI command/byte-enable, input during slave, output during master. P_PAR 23 O PCI parity P_PERR# 21 I/O PCI parity error P_SERR# 22 O PCI system error P_CLKRUN# 115 I/O Primary PCI bus clock run. Used by the central resource to stop the PCI clock or to slow it down S_CLK[3:0] 110,109, O Secondary PCI clock 108,107 S_IDEN 106 O Reserved. Must be pulled high. S_RST# 105 O Secondary PCI reset S_FRAME# 74 I/O Secondary PCI FRAME S_IRDY# 73 I/O Secondary PCI IRDY S_TRDY# 72 I/O Secondary PCI TRDY S_LDEV# 71 I/O Secondary PCI LDEV S_STOP# 70 I/O Secondary PCI STOP 2003 PLX Technology, Inc. All rights reserved. 13

14 S_AD[31:0] 95,94,92, I/O Secondary PCI address/data 91,90,89, 88,87,85, 83,82,81, 80,79,78, 77,63,62, 61,60,59, 57,56,55, 53,52,51, 50,48,47, 46,45 S_CBE#[3:0] 86,76,66, I/O Secondary PCI command/byte-enable 54 S_PAR 67 O Secondary PCI parity S_SERR# 68 I Secondary PCI system error S_PERR# 69 I/O Secondary PCI parity error S_REQ[3:0]# 99,98,97, I Secondary PCI bus request 96 S_GNT[3:0]# 104,103, O Secondary PCI bus grant 101,100 S_CLKRUN# 112 I/O Secondary PCI bus clock run. Drive high to stop or slow down secondary PCI clock, driven by secondary PCI device to keep clock running ENUM# 113 O Hot Swap Interrupt L_STAT 114 I/O Hot Swap LED NC 65 No connect pin VSS 11,29,38, GND Ground Pins 49,64,75, 93,111, 128 VDD 1,20,39, 58, 84, 102,120 PWR Power Pins 2003 PLX Technology, Inc. All rights reserved. 14

15 3 PCI 6140 Configuration Registers The following PCI registers are supported by PCI All registers, except for register C0h follow the standard PCI register definition. 3.1 Configuration Space Address Map Address Device ID Vendor ID 00h Status Command 04h Class Code Revision ID 08h Reserved Header Type Latency Timer Cache Line Size Secondary Latency Timer Subordinate Bus Number Reserved Reserved Secondary Bus Number Reserved 0Ch 10h 14h 18h Secondary Status I/O Limit I/O Base 1Ch Memory Limit Memory Base 20h Prefetchable Memory Limit Prefetchable Memory Base 24h Reserved Reserved Expansion ROM Base Address Bridge Control Interrupt Pin = 00 Capability Pointer = 80 Interrupt Line = 00 28h-33h 34h 38h 3ch Subsystem ID = 0000 Subsystem Vendor ID = h CLKRUN control Data = 00 Reserved Reserved Reserved PMC = F601 Next Item Ptr = 90 PMCSR Bridge Support PMCSR = 0000 Capability ID = 01 44h-6Bh 6Ch 70h-7Fh 80h 84h 2003 PLX Technology, Inc. All rights reserved. 15

16 Reserved Reserved HSCSR = 00 Next Item Ptr = 00 Reserved Capability ID = 06 Reserved PCI 6140 control Reserved 88h-8Fh 90h 94h-BFh C0h C4h-FFh 3.2 Configuration Register Description The following subsection describes the configuration registers of PCI Table 3-1 Register Access Abbreviation Definition RO Read only. Writes have no effect R/W Read/Write R/WC Read. Write 1 to clear Vendor ID Register (RO) (offset 00h) Hardwired to 3388(h) Device ID Register (RO) (offset 02h) Hardwired to 0021(h) 2003 PLX Technology, Inc. All rights reserved. 16

17 3.2.3 Command Register (offset 04h) Bit Function Type Description 0 I/O Space Enable 1 Memory Space Enable 2 Bus Master Enable 3 Special Cycle Enable 4 Memory Write and Invalidate Enable R/W R/W R/W Controls the bridge s response to I/O accesses on the primary interface. 0=ignore I/O transaction 1=enable response to I/O transaction Reset to 0. Controls the bridge s response to memory accesses on the primary interface. 0=ignore all memory transaction 1=enable response to memory transaction Reset to 0. Controls the bridge s ability to operate as a master on the primary interface. 0=do not initiate transaction on the primary interface and disable response to memory or I/O transactions on secondary interface 1=enable the bridge to operate as a master on the primary interface Reset to 0. R/O No special cycle implementation (set to 0 ). R/O Memory write and invalidate not supported (set to 0 ). 5 Reserved R/O Reserved. Reset to 0 6 Parity Error Enable 7 Wait Cycle Control R/W Controls the bridge s response to parity errors. 0=ignore any parity errors 1=normal parity checking performed Reset to 0. R/O No data stepping supported (set to 0 ) PLX Technology, Inc. All rights reserved. 17

18 8 Primary SERR# Enable R/W 9-15 reserved R/O Reserved. Reset to 0. SERR# enable 0 = Disable SERR# driver on primary interface 1 = Enable the SERR# driver Primary Status Register (offset 06h) Bit Function Type Description 0-3 reserved R/O Reserved (set to 0 s). 4 Capabilities List R/O Set to 1 indicating the presence of additional PCI Capabilities such as the power management and hot swap functions 5 33 MHz R/O 33 MHz maximum frequency (set to 0 ). 6 UDF R/O No User-Definable Features (set to 0 ). 7 Fast Back to Back Capable 8 Data Parity Error Detected R/O Fast back-to-back write capable on primary side (set to 1 ). NOTE: Fast back-to-back mode is always enabled, even though this bit actually returns 0 on reads. R/WC Reset to LDEV timing R/O LDEV timing (default to 10 ). 11 Signaled Target Abort 12 Received Target Abort 13 Received Master Abort 14 Signaled System Error 15 Detected Parity Error R/WC R/WC R/WC Should be set (by a target device) whenever a Target Abort cycle occurs. Reset to 0. Set to 1 (by a master device) when transactions are terminated with Target Abort. Reset to 0. Set to 1 (by a master) when transactions are terminated with Master Abort. Reset to 0. R/WC Set high to indicate SERR_L assertion. Reset to 0. R/WC Set high to indicate data parity error. Reset to PLX Technology, Inc. All rights reserved. 18

19 3.2.5 Revision ID Register (RO) (offset 08h) Hardwired to 10h Class Code Register (RO) (offset 09h) Hardwired to h Cache Line Size Register (R/W) (offset 0Ch) Bit 5-1: Used to set the memory read line or memory read multiple size in dword unit. Must be a multiple of Latency Timer (R/W) (offset 0Dh) Bit 7-3: Used to satisfy PCI specifications Header Type Register (RO) (offset 0Eh) Hardwired to 01h Secondary Bus Number Register (R/W) (offset 19h) Programmed with the number of the PCI bus to which the secondary bridge interface is connected. This value is set with configuration software. Reset to Subordinate Bus Number Register (R/W) (offset 1Ah) Programmed with the number of the PCI bus with the highest number that is subordinate to the bridge. This value is set with configuration software. Reset to Secondary Latency Timer Register (R/W) (offset 1Bh) Bit 7-3: Used to satisfy PCI specifications I/O Base Register (R/W) (offset 1Ch) This register defines the bottom address of the I/O address range for the bridge. The upper four bits define the bottom address range used by the chip to determine when to forward I/O transactions from one interface to the other. These 4 bits correspond to address bits <15:12> and are writeable. The upper 16 bits corresponding to address bits <31:16> are defined in the I/O base address upper 16 bits register. The address bits <11:0> are assumed to be 000h. The lower four bits (3:0) of this register set to 0001 (read-only) to indicate 32-bit I/O addressing. Reset to PLX Technology, Inc. All rights reserved. 19

20 I/O Limit Register (R/W) (offset 1Dh) This register defines the top address of the I/O address range for the bridge. The upper four bits define the top address range used by the chip to determine when to forward I/O transactions from one interface to the other. These 4 bits correspond to address bits <15:12> and are writeable. The upper 16 bits corresponding to address bits <31:16> are defined in the I/O limit address upper 16 bits register. The address bits <11:0> are assumed to be FFFh. The lower four bits (3:0) of this register set to 0001 (read-only) to indicate 32-bit I/O addressing. Reset to Secondary Status Register (offset 1Eh) Bit Function Type Description 0-4 reserved R/O Reserved (set to 0 s) MHz R/O 33 MHz maximum frequency (set to 0 ). 6 UDF R/O No User-Definable Features (set to 0 ). 7 Fast Back to Back Capable 8 Data Parity Error Detected R/O Fast back-to-back write capable on secondary port (set to 1 ). NOTE: Fast back-to-back mode is always enabled, even though this bit actually returns 0 on reads. R/WC Reset to LDEV timing R/O Medium LDEV timing (set to 01 ) 11 Signaled Target Abort 12 Received Target Abort 13 Received Master Abort 14 Received System Error 15 Detected Parity Error R/WC R/WC R/WC Should be set (by a target device) whenever a Target Abort cycle occurs. Should be 0 after reset. Reset to 0. Set to 1 (by a master device) when transactions are terminated with Target Abort. Reset to 0. Set to 1 (by a master) when transactions are terminated with Master Abort. Reset to 0. R/WC Set high to indicate SERR_L assertion. Reset to 0. R/WC Set high to indicate data parity error. Reset to PLX Technology, Inc. All rights reserved. 20

21 Memory Base Register (R/W) (offset 20h) This register defines the base address of the memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits <31:20> are writeable. The lower 20 address bits (19:0) are assumed to be 00000h. The 12 bits are reset to 0. The lower 4 bits are read only and set to Memory Limit Register (R/W) (offset 22h) This register defines the upper limit address of the memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits <31:20> are writeable. The 12 bits are reset to 0. The lower 4 bits are read only and is set to 0. The lower 20 address bits (19:0) are assumed to be FFFFFh. Reset to Prefetchable Memory Base Register (R/W) (offset 24h) This register defines the base address of the prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits <31:20> are writeable. The 12 bits are reset to 0. The lower 4 bits are read only and is set to 0. The lower 20 address bits (19:0) are assumed to be 00000h. Reset to Prefetchable Memory Limit Register (R/W) (offset 26h) This register defines the upper limit address of the memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits correspond to address bits <31:20> are writeable. The 12 bits are reset to 0. The lower 4 bits are read only and is set to 0. The lower 20 address bits (19:0) are assumed to be FFFFFh. Reset to Capability Pointer(R) (offset 34h) This pointer points to the PCI power management registers Expansion ROM Base Address(R) (offset 38h) PCI 6140 does not implement the expansion ROM remapping feature. Register returns all 0s when read Interrupt Line Register(R/W) (offset 3Ch) PCI 6140 does not implement an interrupt signal pin, thus register defaults to FFh Interrupt Pin(R) (offset 3Dh) PCI 6140 does not implement any interrupt pins, so this register returns 0s PLX Technology, Inc. All rights reserved. 21

22 Bridge Control (offset 3Eh) Bit Function Type Description 0 Parity Error Response Enable 1 SERR Enable R/W R/W Specify bridge s response to parity errors on the secondary interface. 0 = ignore address and parity errors 1 = enable parity error reporting Specify forwarding of secondary interface SERR assertions to the primary interface. 0 = SERR disabled 1 = SERR enabled 2 ISA Enable R/W Controls forwarding of ISA IO transactions from the primary to the secondary. 0 = forward all IO addresses in the address range defined by IO base and IO limit registers. 1 = Block forwarding of ISA IO addresses 3 VGA Enable R/W Controls positive decoding and forwarding of VGA-compatible memory addresses. 0 = do not forward VGA-compatible memory and IO addresses from the primary to the secondary interface. 1 = forward VGA addresses 4 Reserved R Reserved 5 Master Abort Mode 6 Secondary Bus Reset 7 Fast Back to Back R/W R/W 8-15 Reserved R Reserved R Specifies how the bridge responds to a master abort that occurs on either interface when the bridge is the master 0 = do not report master aborts 1 = report master aborts by signaling target abort if possible or SERR if enabled in bit 1 of this register Controls assertion of S_RST# 0 = do not force the assertion of S_RST# 1 = force the assertion of S_RST# The bridge always generates fast back to back transactions to secondary devices PLX Technology, Inc. All rights reserved. 22

23 Subsystem Vendor ID(R/W) (offset 40h) An add-in card manufacturer may write to this register via a device driver for identification purposes Subsystem ID (R/W) (offset 42h) An add-in card manufacturer may write to this register via a device driver for identification purposes Secondary Clock Disable Register (R/W) (offset 6Ch) Bit Function Type Description 0 Disable S_CLK0 1 Disable S_CLK0 2 Disable S_CLK0 3 Disable S_CLK0 R/W Disable secondary clock 0 0 = enable clock 1 = disable clock R/W Disable secondary clock 1 0 = enable clock 1 = disable clock R/W Disable secondary clock 2 0 = enable clock 1 = disable clock R/W Disable secondary clock 3 0 = enable clock 1 = disable clock 4-7 Reserved R Reserved 2003 PLX Technology, Inc. All rights reserved. 23

24 Clock run control Register (R/W) (offset 6Fh) Bit Function Type Description 0 Secondary clock status 1 Secondary CLKRUN# enable 2 Primary keep clock running 3 Primary CLKRUN# enable 4 CLKRUN# mode R R/W R/W R/W R/W 5-7 Reserved R Reserved Secondary clock status 0 = secondary clock is running 1 = secondary clock is stopped Secondary clock run enable 0 = disable secondary CLKRUN# 1 = enable secondary CLKRUN# (default) Primary keep clock run 0 = Allow primary clock to stop when secondary clock is stopped 1 = Keep primary clock running regardless of secondary clock Primary clock run enable 0 = disable primary CLKRUN# 1 = enable primary CLKRUN# (default) Secondary clock run mode 0 = Stop secondary clock when requested by primary clock source 1 = Stop secondary clock when secondary bus is idle and no cycle from primary 2003 PLX Technology, Inc. All rights reserved. 24

25 Capability Identifier (R) (offset 80h) This register is set to 01h to indicate power management interface registers Next Item Pointer (R) (offset 81h) Set to 90h. This field provides an offset into the function's PCI Configuration Space pointing to the location of next item in the function's capability list. In PCI 6140, this points to the hot swap registers Power Management Capabilities(R) (offset 82h) Bit Function Type Description 0-2 Version R This register is set to 001b, indicating that this function complies with Rev 1.0 of the PCI Power Management Interface Specification 3 PME Clock R This bit is a '0', indicating that the PCI 6140 does not support PME# signaling. 4 Auxiliary Power Source R This bit is set to 0 since PCI 6140 does not support PME# signaling 5 DSI R Device Specific Initialization. Returns 0 indicating that PCI 6140 does not need special initialization 6-8 Reserved R Reserved 9 D1 Support R Returns 1 indicating that PCI 6140 supports the D1 device power state 10 D2 Support R Returns 1 indicating that PCI 6140 supports the D2 device power state PME Support R Set to 11110b indicating that PME# can be asserted from D1,D2,D3hot and D3cold states. This is true for the latest revision 10. Earlier revisions have this set to b PLX Technology, Inc. All rights reserved. 25

26 Power Management Control/ Status(R/W) (offset 84h) Bit Function Type Description 0-1 Power State R/W This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot 2-7 Reserved R Reserved 8 PME Enable R This bit is set to 0 since PCI 6140 does not support PME# signaling 9-12 Data Select R This field returns 0000b indicating PCI 6140 does not return any dynamic data Data Scale R Returns 00b when read. PCI 6140 does not return any dynamic data. 15 PME Status R This bit is set to 0 since PCI 6140 does not support PME# signaling PMCSR Bridge Support(R) (offset 86h) Bit Function Type Description 0-5 Reserved R Reserved 6 B2/B3 Support for D3hot 7 Bus Power Control Enable R R This bit returns a 1 when read indicating that when the PCI 6140 is programmed to D3hot state the secondary bus s clock is stopped. Returns 1 indicating that the power management state of the secondary bus follows that of the PCI 6140 with one exception, D3hot state PLX Technology, Inc. All rights reserved. 26

27 Capability Identifier (R) (offset 90h) This register is set to 06h to indicate power management interface registers Next Item Pointer (R) (offset 91h) Set to 00h. Indicates the end of the capabilities list Hot Swap Register(R/W) (offset 92h) Bit Function Type Description 0 Reserved R Reserved 1 ENUM# Mask Status R/W 2 Reserved R Reserved Enables or disables ENUM# assertion 0 = enable ENUM# signal 1 = mask off ENUM# signal 3 LED status R Indicates if LED is on or off 0 = LED is off 1 = LED is on 4-5 Reserved R Reserved 6 Extraction State 7 Insertion State R R Indicates assertion of ENUM# due to the device being extracted 0 = ENUM# asserted 1 = ENUM# not asserted Indicates assertion of ENUM# due to the device being inserted 0 = ENUM# asserted 1 = ENUM# not asserted 2003 PLX Technology, Inc. All rights reserved. 27

28 PCI 6140 mode register (offset C0h) Bit Function Type Description 0 Primary to Secondary transaction delay 1 P_CBE[3:0] active 2 Transparent P_GNT R/W R/W R/W 3-4 Reserved R/W Reserved Specify delay for transactions going from primary to secondary PCI interface 0 = delay Primary bus to Secondary bus transfer by 1 P_CLK 1 = no delay Specify decoding timing 0 = use the correct P_CBE[3:0] 1 = force P_CBE[3:0] active only all remaining burst read cycle. 0 = transparent P_GNT 1 = use 1-clock delayed P_GNT 5 IRDY Mode R/W 0 = assert IRDY only after IRDY has been active on the master side 1 = assert IRDY immediately during memory-read-line, or memory-read-multiple after IRDY has been active 6 Memory Read Termination 7 Fast Read Enable 8 Legacy Audio IO Address Enable R/W R/W R/W Always terminate memory read line or memory read multiple on the line boundary Allowing fast read during burst-read. 0 = disable, 1 = enable When enabled, IO address (Game), B (FM), (Audio), (MIDI) will be claimed by PCI 6140 and such cycles will be passed onto the secondary PCI bus PLX Technology, Inc. All rights reserved. 28

29 4 PCI Bus Operation (Transparent Mode) This chapter presents detailed information about PCI transactions, transaction forwarding across PCI 6140, and transaction termination. PCI 6140 provides a simple, but complete PCI-to-PCI bridge capability, allowing PCI master and slave on its either side. It passes control and data between primary and secondary bus to guarantee complete visibility from either side. PCI 6140 is designed to behave like an intelligent buffer. PCI 6140 achieves its zero wait state bridging function by controlling the direction of control and data. It divides control and data into 3 signal groups; the FRAME#/IRDY#/CBE#, LDEV#/TRDY#/STOP#, and AD signal groups. Direction of FRAME#/IRDY#/CBE# is determined by P_GNT#. If P_GNT# is asserted at the time FRAME# is active, direction of LDEV#/TRDY#/STOP# is determined by address decode, as described in the address decode section. Direction of AD[31:0] is determined by the combination of address decode and location of slave PLX Technology, Inc. All rights reserved. 29

30 4.1 Types of Transactions This section provides a summary of PCI transactions performed by PCI Table 4 1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PCI 6140 initiates transactions as a master, on the primary bus and on the secondary bus, and when PCI 6140 responds to transactions as a target, on the primary bus and on the secondary bus. Table 4 1 PCI Transactions Type of transaction Initiates as Master Responds as Target Primary Secondary Primary Secondary 0000 Interrupt N N N N acknowledge 0001 Special cycle Y Y N N 0010 I/O read Y Y Y Y 0011 I/O write Y Y Y Y 0100 Reserved N N N N 0101 Reserved N N N N 0110 Memory read Y Y Y Y 0111 Memory write Y Y Y Y 1000 Reserved N N N N 1001 Reserved N N N N 1010 Configuration N Y Y N read 1011 Configuration Type 1 Y Y Type 1 write 1100 Memory read Y Y Y Y multiple 1101 Dual address N N N N cycle 1110 Memory read Y Y Y Y line 1111 Memory write and invalidate Y Y Y Y As indicated in Table 4 1, the following PCI commands are not supported by PCI 6140 : PCI 6140 never initiates a PCI transaction with a reserved command code and, as a target, PCI 6140 ignores reserved command codes. PCI 6140 never initiates an interrupt acknowledge transaction and, as a target, PCI 6140 ignores interrupt acknowledge transactions. Interrupt acknowledge transactions are expected to reside entirely on the primary PCI bus closest to the host bridge. PCI 6140 does not respond to special cycle transactions. To generate special cycle transactions on other PCI buses, either upstream or downstream, a Type 1 configuration command must be used PLX Technology, Inc. All rights reserved. 30

31 PCI 6140 does not generate Type 0 configuration transactions on the primary interface, nor does it respond to Type 0 configuration transactions on the secondary PCI interface. The PCI-to-PCI Bridge Architecture Specification does not support configuration from the secondary bus. PCI 6140 does not respond to nor initiate DAC cycle transactions. 4.2 Address Phase A 32-bit address uses a single address phase. This address is driven on AD<31:0>, and the bus command is driven on P_CBE[3:0] 4.3 Device Select (LDEV#) Generation PCI 6140 always performs positive address decoding when accepting transactions on either the primary or secondary buses. PCI 6140 never subtractively decodes. Medium LDEV# timing is used on both interfaces. 4.4 Data Phase The address phase or phases of a PCI transaction are followed by one or more data phases. A data phase is completed when IRDY# and either TRDY# or STOP# are asserted. A transfer of data occurs only when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are asserted. 4.5 Write Transactions Acting as PCI bus extender, PCI 6140 responds differently according to the address and initiator. Case 1: Primary master access device on primary bus PCI 6140 will forward all PCI signals from primary to secondary so that any device there can track the PCI bus. Case 2: Primary master access device on secondary bus PCI 6140 will forward address, command, data, byte enable, P_IRDY# to secondary while forwarding S_LDEV#, S_TRDY# and S_STOP# to primary bus. Case 3: Secondary master access device on secondary bus PCI 6140 will forward all PCI signals from secondary to primary so that any device there can track the PCI bus. Case 4: Secondary master access device on primary bus PCI 6140 will forward address, command, data, byte enable, S_IRDY# to primary while forwarding P_LDEV#, P_TRDY# and P_STOP# to secondary. There is no buffer inside PCI 6140 for write PLX Technology, Inc. All rights reserved. 31

32 4.6 Read Transactions PCI 6140 responds according to the address and initiator of the read command. Case 1: Primary master access device on primary bus PCI 6140 will forward all PCI signals from primary to secondary so that any device there can track the PCI bus. Case 2: Primary master access device on secondary bus PCI 6140 will forward address, command, byte enable, P_IRDY# to secondary while forwarding data, S_LDEV#, S_TRDY# and S_STOP# to primary bus. Case 3: Secondary master access device on secondary bus PCI 6140 will forward all PCI signals from secondary to primary so that any device there can track the PCI bus. Case 4: Secondary master access device on primary bus PCI 6140 will forward address, command, byte enable, S_IRDY# to primary while forwarding data, P_LDEV#, P_TRDY# and P_STOP# to secondary. There is no buffer inside PCI 6140 for read PLX Technology, Inc. All rights reserved. 32

33 4.7 Configuration Transactions Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, PCI 6140 also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the Lowest 2 bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the Lowest 2 address bits set to 01b. The register number is found in both Type 0 and Type 1 formats and gives the Dword address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. Type 1 configuration transaction addresses also include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted PLX Technology, Inc. All rights reserved. 33

34 4.7.1 Type 0 Access to PCI 6140 The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. PCI 6140 responds to a Type 0 configuration transaction by asserting P_LDEV# when the following conditions are met during the address phase: The bus command is a configuration read or configuration write transaction. low 2 address bits P_AD<1:0> must be 00b. Signal P_IDSEL must be asserted. The function code is 0. PCI 6140 limits all configuration accesses to a single Dword data transfer and returns a target disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested Dword are returned, regardless of the value of the byte enable bits. Type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately. PCI 6140 ignores all Type 0 transactions initiated on the secondary interface PLX Technology, Inc. All rights reserved. 34

35 4.7.2 Type 1 to Type 0 Translation Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. PCI 6140 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PCI 6140 must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is, PCI 6140 generates a Type 0 transaction only on the secondary bus, and never on the primary bus. PCI 6140 responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase: The low 2 address bits on P_AD<1:0> are 01b. The bus number in address field P_AD<23:16> is equal to the value in the secondary bus number register in configuration space. The bus command on P_CBE<3:0> is a configuration read or configuration write transaction. When PCI 6140 translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address: Sets the low 2 address bits on S_AD<1:0> to 00b. Decodes the device number and drives the bit pattern specified in Table 4 6 on S_AD<31:16> for the purpose of asserting the device s IDSEL signal. Sets S_AD<15:11> to 0. Leaves unchanged the function number and register number fields PLX Technology, Inc. All rights reserved. 35

36 PCI 6140 asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits P_AD<15:11>. Table 4 6 presents the mapping that PCI 6140 uses. Table 4 6 Device Number to IDSEL S_AD Pin Mapping Device P_AD<15:11 Secondary IDSEL S_AD<31:16> S_AD Bit Number > 0h h h h h h h h h h Ah Bh Ch Dh Eh Fh Fh Generate special cycle (P_AD<7:2> = 00h) (P_AD<7:2>!= 00h) - PCI 6140 can assert up to 16 unique address lines to be used as IDSEL signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted. The configuration transaction is still translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends in a master abort. PCI 6140 forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer PLX Technology, Inc. All rights reserved. 36

37 4.7.3 Type 1 to Type 1 Forwarding Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. When PCI 6140 detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, PCI 6140 forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during the address phase: The low 2 address bits are equal to 01b. The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The bus command is a configuration read or write transaction. PCI 6140 also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. A Type 1 configuration command is forwarded upstream when the following conditions are met: The low 2 address bits are equal to 01b. The bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The device number in address bits AD<15:11> is equal to 11111b. The function number in address bits AD<10:8> is equal to 111b. The bus command is a configuration write transaction. PCI 6140 forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer PLX Technology, Inc. All rights reserved. 37