Evaluation Board for CS5394 and CS5396/7

Transcription

1 Features CDB59 CDB59/7 Evaluation Board for CS59 and CS59/7 ldemonstrates recommended layout and grounding arrangements lcs80a generates AES/EBU and/or IEC 958 compatible digital audio lbuffered serial output interface ldigital and analog patch areas lon-board or externally supplied system timing General Description The CDB59, CDB59 and CDB597 evaluation boards are an excellent means for quickly evaluating the CS59, CS59 and CS597 -bit, stereo A/D converters. Evaluation requires a digital signal processor, a low distortion analog signal source and a power supply. Analog inputs are provided via XLR connectors for both channels. Also included is a CS80A digital audio interface transmitter which generates AES/EBU, S/PDIF, and EIAJ-0 compatible audio data. The digital audio data is available via RCA phono and optical connectors. The evaluation board may also be configured to accept external timing signals for operation in a user application during system development. ORDERING INFORMATION: CDB59, CDB59, CDB597 Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 787, Austin, Texas 7870 (5) 5 7 FAX: (5) Copyright Cirrus Logic, Inc. 998 (All Rights Reserved) MAR 98 DS58DB

2 OVERVIEW CDB59/9/97 System The CDB59/9/97 evaluation boards are an excellent means of quickly evaluating the CS59, CS59 or CS597. The CS80A digital audio interface transmitter provides an easy interface to digital audio signal processors, including the majority of digital audio test equipment. The evaluation board has been designed to accept an analog input and provide optical and coaxial digital outputs. The evaluation board also allows the user to access clocks and data through a 0-pin header for system development. The CDB59/9/97 schematic has been partitioned into 7 schematics shown in Figures through 8. Each partitioned schematic is represented in the system diagram shown in Figure. Notice that the system diagram also includes the connections between the partitioned schematics. Power Supply Circuitry and Grounding Power is supplied to the evaluation board by six binding posts as shown in Figure 8. +5VA provides 5 Volt power to the converter, VCOM buffer and the crystal oscillator. The +/-V binding posts provide power to the analog input buffer. supplies 5 Volt power to the digital section of the board. Z-Z are transient suppression diodes which also provide protection from incorrectly connected power supply leads. Configuration for Stand-Alone or Control Port Mode Refer to Tables - for the jumper settings required to configure the evaluation board. Power-Down and Calibration - Stand alone Mode The CS59 and CS59/97 in Stand-Alone mode are placed into the power-down mode simply by depressing the PDN switch (S). Power-down is released when the PDN switch is released. A calibration sequence should be manually initiated by depressing the CAL switch (S) following powerdown. Power-Down and Calibration - Control Port Mode for CDB59/97 Only Power-down and calibration are available only through the control port. The calibration and power-down buttons on the evaluation board are ignored when configured in the Control Port mode. Supplied Control Port Commands for CDB59/97 The evaluation board includes a set of DOS files which allow communication through a PC parallel port to the evaluation board. The supplied commands include: calx.bat - Performs a calibration and initialization sequence and sets the CS59/97 into the X oversampling mode. cal8x.bat - Performs a calibration and initialization sequence and sets the CS59/97 into the 8X oversampling mode. rdic.exe <Map>- This routine returns the value located in the register pointed to by <map>. The <map> value is in hex and the value returned is in hex. wric.exe <map> <data> - This routine writes the value of <data> into the register pointed to by <map>. Both values are in hex. rst.exe - Sends a reset command to the device. mode8x.bat - Sets the device into the 8X oversampling mode. The cal8x.bat command includes this sequence. modex.bat - Sets the device into the X oversampling mode. The calx.bat command includes this sequence. DS58DB

3 gnd.bat - Disconnects the analog modulators from the input pins and attaches the modulator inputs to the internal common mode voltage. ungnd.bat - Disconnects the analog modulators from the internal common mode voltage and attaches the modulator inputs to the input pins. General Comments on the Parallel Port The evaluation board will be partially powered through the PC cable when the supplies to the evaluation board are off. This will affect the RC timing circuit which places the CS59/97 into the Control Port mode. It is required that the evaluation board go through the power-up sequence without the cable to the PC connected. Input Buffer The differential input circuit shown in Figure is well-suited for the CS59/9/7 in professional applications. The circuit will accept a differential or single-ended signal of either polarity and provide a differential signal with the proper DC offset to the CS59 or CS59/97. The circuit also incorporates db of attenuation to scale down professional input levels to the input voltage range of the CS59/9/97. A nominal input level of Volts rms to the evaluation board will achieve a full scale digital output from the CS59/9/97. The common mode rejection of the system is limited by the passive component matching of the input buffer circuit. The analog input connector is a standard female XLR with Pin positive, Pin return, and Pin shield. R, R5, R and C5 form an RC network which provides anti-alias filtering and the optimum source impedance for the CS59/9/97 right channel inputs. R, R, R5 and C duplicate this function for the left channel. Notice that this circuit also provides approximately.5 db attenuation to lower the noise contributed from the analog input buffer. The CS59/9/97 are able to withstand input currents of 00 ma maximum, as stated in the CS59 and CS59/7 data sheets. The OPA7 op-amp is not able to deliver 00 ma, so input protection diodes are not required. However, protection diodes are recommended if there is a possibility that overrange signals could be applied at the ADC inputs which exceed 00 ma. Refer to the Crystal application note, AN0: A/D Converter Input Protection Techniques. CS59 and CS59/7 A/D Converters The CS59/9/97 A/D converters are shown in Figure. A description of these devices is included in the CS59 and CS59/7 datasheets. CS80A Digital Audio Interface Figure shows the circuitry for the CS80A digital audio interface transmitter. The CS80A can implement AES/EBU, S/PDIF, and EIAJ-0 interface standards. The Digital Interface Format for the transmitter must be set to match the format chosen for the CS59 or CS59/7 as defined in Tables -. SW provides 8 DIP switches to select various modes and bits for the CS80A; switch definitions and the default settings for SW are listed in Tables 5-. Digital outputs are provided on an RCA connector via an isolation transformer and on an optical transmitter. For more detailed information on the CS80A and the digital audio standards, see the CS80A/CS80A data sheet. I/O Port for Clocks and Data A serial output interface is provided on I/O Port_, as shown in Figure. When I/O Port is set to the MASTER position, MCLK, SCLK, LRCK and SDATA are outputs from I/O Port. When I/O Port is in the SLAVE position, MCLK and SDATA are outputs, while SCLK and LRCK become inputs. Hence, in SLAVE mode, the SCLK and LRCK signals must be externally derived from MCLK to run the ADC. All signals are buffered in order to isolate the converter from external circuitry. Note that the DS58DB

4 CS59/9/97 must also be properly configured for Slave or Master mode. CS80A Format Configuration The CS59/9/97 supports two Digital Interface Formats for both master and slave configurations. Format 0 has valid data on the rising edge of SCLK and the CS80A has no corresponding mode. However, inverting SCLK so that data is valid on the falling edge of SCLK will make Format 0 of the CS59/9/97 match Format of the CS80A. Jumpers are available to configure the CS80A to Format and perform inversion of SCLK. See Tables -. Digital Interface Format is the IS compatible mode and matches Format of the transmitter. Refer to Tables - for jumper positions. CS80A MCLK Generation The crystal oscillator (U5) is either 5x for the x oversampling mode or 5x for the 8x oversampling mode. However, the CS80A requires a master clock frequency of 8x Fs. Therefore, the MCLK must be divided by either or depending on the mode of operation. Refer to Tables - for the proper jumper selection. Grounding and Power Supply Decoupling The CS59/9/97 require careful attention to power supply and grounding arrangements to optimize performance. The CS59/9/97 is positioned over the analog ground plane. This layout technique is used to minimize digital noise and to insure proper power supply matching/sequencing. The decoupling capacitors are located as close to the ADC as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yields large reductions in radiated noise effects. The evaluation board uses separate analog and digital ground planes which are joined at the converter. This arrangement isolates the analog circuitry from the digital logic. DS58DB

5 CONNECTOR INPUT/OUTPUT SIGNAL PRESENT +5VA input +5 Volts for analog section input +5 Volts for digital section ±V input ± Volts for analog input input Analog ground connection from power source D input Digital ground connection from power source AINL input Left channel differential/single ended analog input AINR input Right channel differential/single ended analog input LRCK, SCLK input/output I/O for serial and left/right clocks MCLK output Master clock output SDATA output Serial data output coaxial output output CS80A digital output via transformer optical output output CS80A digital output via optical transmitter Table. System Connections Jumper Purpose Position Function Selected HDR Sets the proper pull-up for the parallel port Selects a k pull-up for IC compliance Invalid selection for uc mode HDR7 Sets the proper pull-up for the parallel port Selects a k pull-up for IC compliance Invalid selection for uc mode HDR8 Sets the proper pull-up for the parallel port Selects a k pull-up for IC compliance Invalid selection for Control Port mode HDR0 Selects Stand-Alone or Control Port mode Selects Control Port Mode Invalid selection for Control Port Mode HDR Selects IC or SPI mode for CS59/97 control port Selects IC mode Selects SPI Mode SDATA Selection of data source for output from the SPDIF and I/O port Selects SDATA Selects SDATA I/O Port I/O port Slave or Master selection Slave Master LRCK and SDATA are inputs to the port. LRCK and SDATA are outputs from the port 80A Mode Sets CS80A data format selection for CS59/97 compatibility. IS LJ IS data format selected Left Justified data format selected Mode Mode All jumpers must be set to either IS or LJ and be compatible with the CS59/97 data format. CS80A MCLK divide for CS80 and CS59/97 compatibility 8 x x Divide MCLK by for 8x oversampling mode Divide MCLK by for x oversampling mode CS59/97 Supports a future function of the CS59/97 Bold indicates default settings Invalid selection Should be set LOW Table. CDB59 and CDB597 Control Port Mode jumper Setting DS58DB 5

6 Jumper Purpose Position Function Selected HDR Secondary effect on power-down implementation Invalid selection for Stand-alone Mode Must be set low for operation HDR7 CS59/97 digital data format selection Selects IS data format Selects Left justified data format HDR8 CS59/97 Master or Slave mode selection Selects Slave Mode Selects Master Mode HDR0 Selects Stand-alone or Control Port mode Selects Control Port Mode Selects Stand-alone Mode HDR Selects polarity of power-down Must be set Invalid selection, CDB will not function SDATA Selection of Data source for output from the SPDIF and I/O port Selects SDATA Selects SDATA I/O Port I/O port Slave or Master selection Slave Master LRCK and SDATA are inputs to the port LRCK and SDATA are outputs from the port 80A Mode Sets CS80A data format selection for CS59/97 compatibility. All IS LJ IS data format selected Left Justified data format selected Mode Mode jumpers must be set to either IS or LJ and be compatible with the CS59/97 data format (HDR7) CS80A MCLK divide for CS80 and 8 x Divide MCLK by for 8x oversampling mode CS59/97 CS59/97 compatibility Supports a future function of the CS59/97 x Table. CDB59 and CDB597 Stand-Alone Mode Jumper Settings Bold indicates default settings Table. CDB59 Jumper Settings Divide MCLK by for x oversampling mode Invalid selection Should be set LOW Jumper Purpose Position Function Selected HDR Secondary effect on power-down implementation Invalid selection for Stand-alone Mode Must be set low for operation HDR7 CS59 digital data format selection Selects IS data format Selects Left justified data format HDR8 CS59 Master or Slave mode selection Selects Slave Mode Selects Master Mode HDR0 Selects Stand-alone or Control Port mode Invalid selection for CS59 Selects Stand-alone Mode HDR Selects polarity of power-down Must be set Invalid selection, CDB will not function SDATA Selection of Data source for output from the SPDIF and I/O port Selects SDATA Invalid selection for CS59 I/O Port I/O port Slave or Master selection Slave Master LRCK and SDATA are inputs to the port LRCK and SDATA are outputs from the port 80A Mode Sets CS80A data format selection for CS59 compatibility. All IS LJ IS data format selected Left Justified data format selected Mode Mode jumpers must be set to either IS or LJ and be compatible with the CS59 data format (HDR7) CS80A MCLK divide for CS80 and 8 x Invalid selection for CS59 CS59/97 CS59 compatibility Supports a future function of the CS59/97 x Divide MCLK by for x oversampling mode Invalid selection Should be set LOW DS58DB

7 Switch# 0=Closed, =Open Comment PRO=0 Consumer Mode (C0=0) FC, FC0 C,C5,C,C7 - Sample Frequency 8, * khz khz 00 - khz khz, CD Mode 7 C C,C,C5 - Emphasis ( of bits) * None 00-50/5 µs C C - Copy/Copyright * Copy Inhibited/Copyright Asserted - Copy Permitted/Copyright Not Asserted C5 C5 - Generation Status * Definition is based on category code - See CS80A Data Sheet, App. A C8, C9 C8-C - Category Code ( of 7 bits), 0 0 * General PCM encoder/decoder Compact Disk - CD Digital Audio Tape - DAT Table 5. CS80A Switch Definitions - Consumer Mode Switch# 0=Closed, =Open Comment PRO= Professional Mode (C0=) 8 CRE Local Sample Address Counter & Reliability Flags 0 Disabled Internally Generated 7, C, C7 C,C7 - Sample Frequency Not Indicated - Default to 8 khz 0-8 khz 0 -. khz - khz 5 C C - Audio Normal Audio - Non-Audio C9 C8,C9,C0,C - Channel Mode ( of bits) Not indicated - Default to -channel Stereophonic, EM, EM0 C,C,C - Emphasis ( of bits) Not Indicated - Default to none 00 - No Emphasis 0-50/5 µs - CCITT J.7 Table. CS80A Switch Definitions - Professional Mode DS58DB 7

8 Fig. 5 Fig. Fig. Fig. 7 Fig. Fig. Figure. System Block Diagram and Signal Flow 8 DS58DB

9 DS58DB 9 AINL+ AINL- CAL HDR SDATA +5VA.7 R7 +5VA VBIAS VBIAS + - V+ + - V U5 OPAU K R8 C7.0UF C.0UF +VD HDR0 7K R 00K R C8.UF +5VA K R C.UF.UF C C9.UF.UF C8.UF C7 BAT85 D +VD FERRITE_BEAD L FERRITE_BEAD L SDATA 5 U SN7HC5N SDATA SDATA R 7K R 7K LO HI 5V C7 00UF HI LO 00UF C 0UF C8 SCLK LRCK VREF VCOM AINL+ AINL- ADCTL MCLKA TST0 DACTL CAL VD+ D LRCK SCLK SDATA AINR+ AINR- VA+ VL+ L TST0 MCLKD PDN DFS S/\M SDATA U? CS59 AINR+ AINR- MCLK CS/PDN CDIN/DFS CCLK/SMB Figure. CS59 and CS59/7 Connections

10 0 DS58DB *.UF C50 7 R50.UF C7 VCC 7 SN7HC0N U R0 8.K LRCK SDATA 80_MODE_ MCLK HDR TP TP NC CON_RCA_RA J 90.9 R5 TOTX7 5 OPT TP5 TP TP 0UF C7 C.UF OPEN SW_DIP_8 SW 7K RN TP TP 5 TR XFR_PE_7900 D S C R HC7A U HI HI LO LO M 8X X.0UF C D S C R 5 7HC7A U SCLK 80_MODE_ LEFT JUSTIFIED M0 80_MODE_ U IS CS80A_CS CRE/FC C7/C PRO C/FC0 C/C C9/C5 EM0/C9 EM/C8 TXP SCK SDATA FSYNC VD+ CBL V C U TXN MCK M0 M M /RST Figure. CS80A Digital Audio Transmitter and Connections

11 DS58DB V 70UF C70 87 R 5V C5 00UF 0.% 0.% 0.% 0.% 0.% 0.% 0.% 0.% +V R8 M R7 M +V -V M R5 R M AINL- VBIAS VBIAS.UF C8 - + V+ V- 5 7 OPA7AP U7 - + V+ V- 7 5 OPA7AP U -V C.UF +V +V C5.UF NPO 00PF C C5 00PF NPO C58.UF XR7.UF C59 XR7 C5.UF XR7.UF C5 XR7.UF C8 -V -V -V +V NPO 0PF C R 7.77K NPO 00PF C NPO 00PF C NPO 00PF C M R7 R8 7.77K R9 7.77K R 7.77K R 7.77K NPO 00PF C XLR J R0 7.77K NPO 00PF C R K NPO 0PF C +V - + V+ V- 7 5 U OPA7AP.UF C V+ V- 5 7 U OPA7AP - + V+ V- 7 5 OPA7AP U - + V+ V- 7 5 OPA7AP U8 AINL+ AINR+ NPO 00PF C M R C5.UF C.UF -V +V C9.UF.UF C0 +V.UF C5 -V AINR- -V R7 7.77K R5 00 R 00 0.% R5 0K 0.% 0K R 0.% R57 0K 0.% R58 0K XLR J 5V C 00UF 5V C 00UF 5V C9 00UF R5 87 R 87 R 87 COG C5 00PF COG C 00PF V 70UF C0 V 70UF C9 -V +V V 70UF C5 Figure. Analog Input Buffer

12 Figure 5. P.C. Parallel Interface DS58DB

13 Figure. I/O Interface for Clocks & Data Figure 7. CAL Circuitry DS58DB

14 L FERRITE_BEAD DIGITAL DIGITAL D J J9 C0.UF C57 7UF L FERRITE_BEAD Z PKEV8P C 70UF V C0.UF C 70UF V +VD C0.UF TO +V -V +5VA J7 J8 J5 J Z PKEV8P Z PKE Z PKE C? 70UF V C? 70UF V C? 70UF V C.UF C.UF C.UF +V -V L5 FERRITE_BEAD +5VA +5VA L FERRITE_BEAD +5VA Figure 8. Power Supply & Reset Circuitry DS58DB

15 Figure 9. CDB59 and CDB59/7 Component Silkscreen Side (top) DS58DB 5

16 Figure 0. CDB59 and CDB59/7 Component Silkscreen Side (bottom) DS58DB

17 Figure. CDB59 and CDB59/7 Component Copper Side (top) DS58DB 7

18 Figure. CDB59 and CDB59/7 Component Copper Side (bottom) 8 DS58DB

19 Notes

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