User s Guide. DAV Digital Audio/Imaging Japan (DAIJ) SLAU068

Transcription

1 User s Guide May 00 DAV Digital Audio/Imaging Japan (DAIJ) SLAU08

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3 Running Title Attribute Reference DEM-DAI0/0 Module Description Ordering Information Block Diagram DEM-DAI0/ Configuration Controls Digital Audio Receiver Digital Filter (DF0/DF0) PCM Jumpers JP CN JP0 0 (Six Pieces) Demonstration Software (Version 0.0X) Installation Operation Schematics and Board Layout Schematics Board Layout DEM-DAI0/0 Board Internal Block Diagram Jumper JP DFI0/0 Top Menu DFI0/0 Window Submenus Digital Section (Digital Audio Interface/Digital Filter) Connector and Regulator Analog Section (DAC, I/V, and LPF Amplifier) Board Layout Top View Board Layout Bottom View Board Layout Silkscreen Contents iii

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5 Chapter The DEM-DAI0/0 is an evaluation module for the PCM0 and DF0/DF0 digital-to-analog converters (DACs). This module can achieve -bit/9-khz sampling format. This DEM-DAI0/0 uses two PCM0 DACs (stereo), two OPA for current/voltage amplification, an OPA in a second-order low-pass filter (LPF) in the analog section, and a digital audio receiver and a DF0/DF0 DAC in the digital section. Digital data can be connected to either input of the DF0/DF0 or directly input into the PCM0. An SPDIF signal is also accepted by the digital audio interface device (coax and optic). The DEM-DAI0/0 requires three power supplies: V for digital, ± V for the DACs (PCM0), and ± V for the analog output circuit. Topic Page. Ordering Information Block Diagram DEM-DAI0/ Configuration Controls Jumpers Demonstration Software (Version 0.0X) DEM-DAI0/0 Module Description -

6 Ordering Information Figure. DEM-DAI0/0 Board The following table provides ordering information for the DEM-DAI0/0 evaluation module.. Ordering Information Model DEM-DAI0 DEM-DAI0 Construction DF0+PCM0 DF0+PCM0 -

7 Block Diagram. Block Diagram Figure. Internal Block Diagram Figure shows the internal block diagram of the DEM DAI0/0 board. ML MC MD RST GND +V V GND +V V GND +V +.V REG. VDDsel. COAX SPDIF INPUT OPT Operation mode SW00 SW00 Format selection CS8 & Logic DAI (BUS) select 0 Digital Filter DF0 or DF0 LRCK BCK DATA XTI CLKO GND BCK/ WDCK/ DOL/ DOR Jumper BCK/ WDCK/ DOL BCK/ WDCK/ DOR DAC PCM0 DAC PCM0 PCM0 x SW0 PCM0 Format select I/V AMP OPA I/V AMP OPA nd-order LPF OPA Lch Output Rch Output External I/F (CN00) Digital Analog. DEM-DAI0/0 Connect the -V, ±-V, and ±-V power supplies to V DD, V CC, V CC, AV CC, AV CC, and GND through connectors CN0 08. Connect SPDIF signal to CN00(COAX) or U00(OPT). Set all positions of SW00 to high and all positions of SW00 to low for software control. Set input data format and demonstration software with SW The system clock and other digital signals are supplied from the digital audio receiver through the jumper block to DF0 or DF0.. Configuration Controls.. Digital Audio Receiver... Output Data Format SW00 (M0) SW00 (M) SW00 (M) OUTPUT DATA FORMAT L L L -bit left-justified, MSB-first L H L I S H L H -bit standard, right-justified L H H 8-bit standard, right-justified DEM-DAI0/0 Module Description -

8 Configuration Controls.. Digital Filter (DF0/DF0)... Serial I/F SW00: Manual reset for CS8 SW00: Digital audio interface selection: Internal CS8 External (CN00) JP00: BCK Selection: Remove the jumper from BCK to BCK(L/J) when using left-justified MSB-first data format. SW00 H L MUTE Mute off Mute on MODE Software mode Hardware mode RSTB Normal operation Reset operation MDI(CKO) x input Same as input MC(LRIP) H: L ch, L: R ch H: R ch, L: L ch ML(RESV) Reserved ML, MC, MD: These pins are serial-control data input in software mode. RESV, LRPI, CKO: Hardware can control functions by setting H or L. LRIP : Polarity control for LRCK clock CKO : Output clock frequency control over system clock... Filter Selection SW00 H L DEM De-emphasis on De-emphasis off OSS x Oversampling x8 oversampling SRO Slow rolloff Sharp rolloff... Input Data Format IIS IW IW0 Input Data Format L L L -bit standard, right-justified L L H 0-bit standard, right-justified L H L -bit standard, right-justified L H H --bit left-justified, MSB-first H L L -bit I S H L H -bit I S... Output Data Format OW OW Input Data Format L L -bit MSB-first -

9 Jumpers L H 8-bit MSB-first H L 0-bit MSB-first H H -bit MSB-first... Sampling Rate for De-Emphasis Control SF SF0 Input Data Format L L. khz L H Reserved H L 8 khz H H khz.. PCM0 SW0 H L 0-bit -bit data interface 0-bit data interface INVL Normal phase for L-ch Invert phase for L-ch INVR Normal phase for R-ch Invert phase for R-ch Input data phase can be inverted by INVL, INVR control.. Jumpers.. JP00 There are 9 jumpers on board: JP00: For digital signal to DF0 or DF0 CN09: For power supply selection (. V or V) CN0: For digital signal to PCM0 JP0 0: For fc of second-order postfilter The digital signal generated by the digital audio receiver is input to this jumper. If each pin is shorted, the digital signal goes to the DF0 or DF0. Figure. Jumper JP00 JP00 SCKI BCK(left-justified) BCK LRCK DATA CLKO GND DEM-DAI0/0 Module Description -

10 Demonstration Software (Version 0.0X).. CN09 The board has a.-v voltage regulator used as the digital power supply for the DF0. The CN09 jumper determines the supply voltage for the digital filter.. V: DF0 V: DF0.. JP0 0 (Six Pieces) These jumpers determine the fc of the second-order postfilter. Short JP0 0 Open JP0 0. Demonstration Software (Version 0.0X) fc = khz fc = 08 khz Demonstration software is provided to control the DF0/DF0 s internal register using a PC under Microsoft Windows./9/98. This software uses a printer cable to connect between the PC and the DEM-DAI0/0 s connector CN00... Installation Demonstration software includes a total five files in the DEM0&0 directory (folder) on floppy disk. These files are: Dem0&0.exe Dem0&0.ini Vbrjp00.dll inpout.dll Ver.dll Copy these files to a convenient directory (folder) such as C:\DEM0&0. Then change printer-port address in Dem0&0.ini to: &H8, &H8 or &HBC0. (Most PCs use &H8 as the default-printer port address) -

11 Demonstration Software (Version 0.0X).. Operation After executing Dem0&0.exe, the window shown in Figure appears on the screen. This window shows the contents of the internal register. There are two menus on top of the panel: Execute (E): This menu has the following options: Initialize (I): Initialize all internal register Reset (R) : Reset all selected data to DF0/0 Exit (X) : Exit this program Window (W): This menu has Attenuation, Interface Format, and Function options, as shown in Figure. Attenuation (A): This panel controls the attenuation function of the DF0/0. Interface format control (I): This panel controls input and output I/F format. Function control (F): This panel controls other functions. Figure. DFI0/0 Top Menu DEM-DAI0/0 Module Description -

12 Demonstration Software (Version 0.0X) Figure. DFI0/0 Window Submenus Attenuation Window Interface Format Window Function Window -8

13 Chapter This chapter presents the schematics and printed circuit board layout. Topic Page. Schematics Board Layout Schematics and Board Layout -

14 Schematics. Schematics This section presents the DEM DAI0/0 schematic diagrams. -

15 Schematics Figure. Digital Section (Digital Audio Interface/Digital Filter) V DD+ U00 C VERF 8 (L00) Cd/F Ce/F µ H Cc/F0 SDATA C00 0 µ F U00 /V TORX C µ F C00 C00 0. µ F 0 µ F /V CN00 RCA pj C µ F R00 C00 Cb/E ERF C00 0. µ F Ca/E M C008 0 µ F CS8 C0/E0 M0 0. µ F /V 0 SW00 FTD M U VD+ DGND RXP RXN FSYNC SCK CS/FCK U C0 VA+ AGND FILT MCK M M SEL CBL µ F U00 HC C00 0. µ F R00 U00 HC 0 C µ F [BCK] C0 0. µ F Vcc GND V CC GND R00 k O O BCK WCK DOL DOR C08 0 µ F/ V VHC [e SCLK] EXT [SCLK] V CC [SCLK] [e BCK] D00 SS R00 0 SW00 DSS0 RA00 SW00 k x C0 FPF M 0 µ F/ V [e LRCK] [e DATA] C0 GND C0 0. µ F [IIS] [IW0] [IW] DIN LRCIN BCKIN SRO IIS BCKO IW0 WCKO IW DOL XTI DF0 DOR XTO V V CC OSS DD CLKO OW MODE OW0 MD/CKO SF MC/LRIP SF0 ML/RESV DEM RST MUTE (FIL00) IN OUT GND U00 (X00) (C09) (C00) (C0) 0. µ F U VHC Vcc [RST ] GND SW00 FTD M [LRCK] (C0) JP00 0 µ F/ V FFC BMEP (CN00) FFC 8BMEP 8 [RST ] [MD] [MD] SW00 FTD M SW00 FTD M () () SW00 DSS CN00 LE 00 00(D) [SCLK] [GND] [BCK] [BCK(Left Jus)] [DATA] [CLKO] V DD+ 0. µ F RA00 k x 0 DAI select INT(CS8) [MC] [ML] [MC] [ML] E] [MOD [OW] [SF0] [SF] [DEM] [OSS] [SRO] [BCK] [LRCK] [DATA] [BCK] [LRCK] [DATA] [OW0] ERF VERF CN00 R00 k R00 k [e-sclk] [e BCK] [e LRCK] [e DATA] Schematics and Board Layout -

16 Schematics Figure. Connector and Regulator CN08 banana jack (black) CN0 banana jack (red) V DD + U0 REG. V DD + V V CC +V V CC CN0 CN0 CN0 banana jack banana jack banana jack (blue) (black) (red) V V CC CN0 banana jack (blue) CN0 banana jack (green) +V V CC CN0 banana jack (orange) C0 0. µf C0 00 µf /V IN OUT GND C00 C09 0. µf 0 µf/ V CN09 FFC BMEP C0 C08 0. µf 00 µf /V C0 00 µf /V C0 0. µf C0 00 µf /V C0 C0 0. µf 00 µf/ V C0 0. µf -

17 Schematics Figure. Analog Section (DAC, I/V, and LPF Amplifier) BCKO WCKO DOL DOR CN0 FFC 0BMEP SW0 DSS0 C0. µ F /V C0. µ F /V C0. µ F /V C0. µ F /V U0 PCM0U DATA BCLK NC V DD DGND +V DD WCLK NC 0bit INVE +V PCM0 V CC REF DC NC SERVO AGND AGND I OUT NC BP0 CC C0. µ F/ V U0 PCM0U DATA BCLK NC V DD DGND +V DD WCLK NC 0bit INVER V CC REF DC NC SERVO AGND AGND I OUT NC BP0 +V CC PCM C0. µ F/ V C. µ F /V C. µ F /V C09. µ F /V C0 00 µ F /V C. µ F /V C. µ F /V C0. µ F /V C08 00 µ F /V C pf R0.k C. µ F/ V U0 OPAAP C9. µ F/ V +V V CC V V CC C pf R0.k C8. µ F /V U0 OPAAP C0. µ F/ V R0 k C 0pF JP0 JP0 R0 R0 C 0pF JP0 k k R09 CN0 00 RCA pj C 00pF C 00pF U0 OPAA / +V V CC C9. µ F/ V C0. µ F/ V R08 k V V CC C8 0pF JP0 JP0 R0 k C 00pF JP0 C 00pF R0 k C 0pF 8 U0 OPAA / R0 00 CN0 RCA pj Schematics and Board Layout -

18 Board Layout. Board Layout Figure. Board Layout Top View This section presents the DEM DAI0/0 board layout. -

19 Board Layout Figure. Board Layout Bottom View Schematics and Board Layout -

20 Board Layout Figure. Board Layout Silkscreen -8