HFCT-5014 Evaluation Board For Avago Technologies HFCT-711XPDZ, HFCT-721XPDZ 10 Gb/s 1310 nm Optical Transceiver. SW1 - all off Manual Mod_Desel - on

Transcription

1 HFCT-0 Evaluation Board For Avago Technologies HFCT-XPDZ, HFCT-XPDZ 0 Gb/s 0 nm Optical Transceiver User Guide Introduction The document provides a brief introduction to the Avago HFCT-XPDZ and HFCT-XPDZ 0 nm hotpluggable XFP transceivers. It describes the functionality of the evaluation board and suggests a recommended procedure to test the product. It should be used in conjunction with the XFP preliminary Data Sheet. The Avago HFCT-**XPDZ is a single mode 0 nm optical transceiver that has a link distance of up to 0 km (0 GbE and 0 GFC) or km (OC9). The transmitter contains a directly modulated 0 nm Distributed Feedback (DFB) laser, and a PIN photo detector within the receiver section. The module is fully compliant to the XFP Multi Source Agreement and to the appropriate 0 Gb/s standards for the networking protocol. The optical interface to the module is provided via a duplex LC receptacle and the electrical interface through a 0 pin pluggable connector. Evaluation board and Graphical User Interface, GUI The evaluation kit comprises: Quantity Description CD-ROM containing the GUI and the XFP preliminary data sheet sets Power Supply Leads for.0mm connector Evaluation board (PCB) including micro controller Preliminary Documentation: Data sheet Standard RS male/female cable A photograph of the evaluation board is shown in Figure a []. Figure b shows a close-up (cage removed) of the module are and shows all electrical connections and the default setting for the jumpers. This setting enables microprocessor control of the XFP module and evaluation board. Note all of the PCB connections, including the RS lead, must be completed prior to the supply of power to the PCB. However, the XFP module maybe hot-plugged into the PCB after the power supply has been connected. SW - all off Manual Mod_Desel - on IC lines - both on B jumpers - all on C jumpers - all off A jumpers - all on -.V +V +.V +.V +.V +.V Figure a. Evaluation board top surface (XFP heat sink removed) Figure b. Detail of jumpers and power supply filters (XFP cage and heatsink removed) Some evaluation boards may not be populated with the / reference clock oscillators.

2 Power Supply Filters As suggested in the XFP MSA, the evaluation board is fitted with a power supply filter network for each of the power supply pins on the XFP connector. Where there are two pins on the XFP0 connector for a Vcc supply level, e.g.. V, there are two separate supply filters to enable the isolation of one of the supply rails. Each of the six power supply filters can be configured in the following ways:. Filter connected. Filter bypassed Note that the power supply for the evaluation board ICs is not filtered as it is directly connected to connector. This connection must be present under all circumstances. See Table for the appropriate jumper settings for each power supply filter. For each of the power supply circuits, the following modes of operation are used:. When Jumpers A and B are ON and C is off the filter is connected. This is the recommended mode of operation.. When Jumpers A and B are off and only C is ON the power supply filter is bypassed. This mode is useful for testing individual Vcc power supply noise immunity. See the XFP MSA for Power Supply Noise Immunity testing requirements. When the Vcc pairs present on the connector are connected within the module, only one of the.0 mm connectors need be used. However, the maximum current of.0 A of the XFP connector must be considered. JP A JP B CON.0 mm connector C 00 nf L. H C C F 00 nf JP C Vcc_ Figure. Example of the eval board power supply filter circuit Table. Jumper numbers for each power supply filter mm Connector Voltage supply Jumper A Jumper B Jumper C Con + V JP JP JP Con -. V JP JP JP0 Con +. V JP9 JP JP Con +. V JP JP JP Con N/A N/A N/A Con +. V JP JP JP9 Con +. V JP JP0 JP Note: The maximum current on any single connector is.0 A.

3 Manual control mode The dipswitches (SW) allow the user to manually control the P_Down/RST, Tx_Dis, and Mod_Desel pins on the 0 pin connector. In order to place the evaluation board under microprocessor control all dipswitches must be set to OFF. In order to enter manual control mode it is necessary to set dipswitch (marked as Not used on the evaluation board) to ON this causes the microcontroller on the evaluation board to release control of the XFP module and its connector. The behaviour of dipswitches - when the evaluation board is in manual mode is summarised in Table. Other jumpers and switches Jumper interrupts the connection between dipswitch and the 0 pin connector. If the evaluation board is in manual mode (dipswitch set to ON ), setting jumper to OFF will set the Mod_Desel pin to a high state disabling the I C interface in the XFP module. It is recommended that this jumper be left in the ON position and that dipswitch be used to control the logic level on the Mod_Desel pin when in manual mode. Jumpers and interrupt the SDA and SCL lines respectively of the I C bus. Setting either of these to OFF will impede communication between the microcontroller on the evaluation board and the XFP module. It is recommended that these two jumpers be set to the ON position. Button A is for resetting the evaluation board to its default (power-up) state. Pressing this button will also reset the XFP module by cycling the P_down/RST pin. Button A00 is for selecting the reference clock mode. The possible modes are: 0GbE, 0GFC, OC9, EXT. See the section entitled Reference clock options for details. LED Indicators There are several LED indicators on the board. They are listed in table, below. Table. Dipswitch When set to OFF When set to ON Sets the P_down/RST pin on the 0 pin connector to, setting the XFP module in power down mode Sets the TX_Dis pin on the 0 pin connector to, disabling laser output Sets the Mod_Desel pin on the 0 pin connector to, disabling the I C interface in the XFP module Table. Sets the P_down/RST pin on the connector to 0, setting the XFP module in normal mode and resetting the module completely Sets the TX_Dis pin on the connector to 0, enabling laser output Sets the Mod_Desel pin on the 0 pin connector to 0, enabling the I C interface in the XFP module. LED Name Colour Description Mod_desel Green Module selected for communication Red Module de-selected Tx Disable Green Laser output enabled Red Laser disabled Interrupt Green Module status normal Red Internal Fault Detected Interrupt Requested Mod_ABS Green Module present Red Module not correctly inserted Rx_LOS Green Light input to Rx is normal Red Light input to Rx is below the limit Green Module status is ok Mod_NR Red MOD_NR = (Txfault asserted) OR (Loss of lock on the Tx) OR (Loss of Lock in Rx signal conditioners) ** Logical OR of possible fault conditions. Red indicates one or more of the fault conditions has occurred. Oscillator Green Oscillator enabled enable Red Oscillator disabled

4 Reference clock options Further LED indicators inform the user of which reference clock oscillator is currently in use. By depressing the RefCLKsel button on the board, one of the three oscillators are sequentially selected. A fourth depression results in all of the oscillators being disabled to allow the user to connect a baud/ differential reference clock to the two SMAs marked Refclk+ and Refclk-. This external clock can be either synchronous or asynchronous with the incoming electrical data to the XFP transmitter, see the XFP MSA for conditions of use. High speed signals The evaluation board has been made using standard FR, and the high speed traces for transmit and receive signals are approximately in length. Hence the board is not suitable for compliance testing of the XFP receiver output eye as it has already been degraded by the traces by the time it reaches the SMA connector. An example of an optimal output eye is shown in Figure. This was obtained by passing a signal from a 0Gb/s BERT through the 0-pin connector using a host-compliance test board as described in the XFP MSA. The XFP transmitter input signal amplitude can be varied to test for module compliance to the XFP MSA. When testing Avago XFP modules error-free operation can be observed when an input signal compliant to MSA Compliance Point B is input to the evaluation board, showing that Avago XFP modules significantly exceed the MSA requirements. 0GbE 0GFC OC9 None/Ext Ref Clock Figure. Reference Clock Selection sequence using RefCLKsel button Figure. Optimal receiver output eye Some evaluation boards may not be populated with the / reference clock oscillators.

5 How to install the Graphical User Interface, GUI The graphical user interface is supplied as a self-extracting installation file for Win-based personal computers. The executable file can be copied from the supplied CD-ROM to a convenient location on the hard drive and run directly by double-clicking. This will install all necessary software and create a program group in the Start Menu. Using the VIEWER Program When the program is first started, there is an initial welcome splash screen. The evaluation board is preset to its default condition. The oscillator mode is set to off. The TX Disable is set to OFF (enabled). The Power Down line is also set to OFF (powered up). The screen shown in Figure is then displayed. The VIEWER program consists of tabbed pages, three pull-down menus, and a series of buttons along the bottom edge. The buttons permit the reading of the data from the module once only or repeatedly every or seconds. A repeated Read can be stopped by using the Stop Reading button. Please note, any changes made to the write-able areas of the GUI are not written to the module until the Write button is pushed. Pull-Down Menus Main: Allows reading the whole of the A0 address space. The contents of the upper bytes of this space can be one of various tables depending upon the value of the table select byte (byte ). Also allows exiting the GUI application. Communication: Allows the choice of the RS com port used by the GUI (default COM), the selection of frequency of the I C bus, and the frequency of the on-board reference clock oscillators (if populated). In addition, this menu contains items for de/asserting the Pdown/RST and TxDisable pins on the 0-pin connector, and for displaying the module s FW revision (this function is specific to Avago Technologies). Help: Displays information about the GUI application itself. Figure. GUI opening screen

6 Tabbed Pages The tabbed pages provide an MSA-compliant interface to the memory space of the XFP module. There are three pages which cover the address space A0 up to byte, in which the MSA defined registers are listed and interpreted, so that both raw register contents and calibrated data are displayed. The page entitled A0: Address 0- displays the contents of the signal conditioner control byte and the alarm and warning threshold values. Some of the bits of the signal conditioner control byte are userprogrammable please see the Avago Technologies HFCT-XPDZ datasheet for information on which of these options are available. The page entitled A0: Address - displays registers pertaining to Variable Power Supply control, and also to BER, FEC, and wavelength control features. Please refer to the HFCT-XPDZ datasheet for further information on the availability of these features. The lower half of this page shows the status of all the latched flags showing alarm or warning conditions. Once read, these are cleared, but will be re-asserted if the alarm or warning condition persists. The page entitled A0: Address 9- displays the masking flags corresponding to the latched interrupt flags. Selecting one or more of these prevents the corresponding fault condition in the module from generating an interrupt. At the bottom of the page, the values of the analog readbacks are shown, both as raw register values and as scaled physical quantities. To the right of this area, the two status bytes are shown (bytes 0 and ). In the former, it is possible to set the SoftPDown and SoftTxDisable bits to put the module into the corresponding state. Finally, at the bottom right of the page, it is possible to enable or disable packet error checking. The page entitled Demo Screen displays all of the analog readbacks in large format (see the HFCT-XPDZ datasheet for the definition of the AUX- and AUX_ signals), along with the most important fault flags: TxFault, LOS, TxLoL, RxLoL, ModNR. To the left, there is information on the Manufacturer, Serial Number and Part Number; displayed are also the oscillator frequency and the data rate selected. The data rate is read back from the appropriate register in the module and does not necessarily reflect the actual data rate being transmitted or received. On page entitled Paging, it is possible to enter the user or vendor passwords. There is also a field for entering a new user password. To the right, there is a pull-down menu for page selection, and a button for viewing the contents of that page. If the page selected is, then a new window with three tabbed pages is opened. These detail the contents of the Serial ID registers in the module and are selfexplanatory. For other values of the page number, a new window is opened which lists the contents of all the registers in that page in hexadecimal. It is also possible to write to these registers by selecting the checkbox for the bytes in question, writing the new value in the appropriate fields, and pushing the Write button.

7 Bill of Materials for the XFP Customer Evaluation Board Table shows the full bill of materials with details of vendors used for some of the components. Table. Bill of Material for Eval Board Used Part Type Designator Footprint Vendor/Part number 9 R R R R R R9 00 Resistors R0 R0 R.0 mm connector CON CON CON CON CON CON CON MM_SOCKET Connector: Farnell no. 9-. k R R 00 Resistors. H L L L L L L L_FILTER 0 k R R R R R R R R09 R 00 Resistors 0 nf C 00 Capacitor k R 00 F C C C9 C C C9 00 Capacitor J 0 PIN XFP 0 PIN surface mount connector XFP-CON0 C onnector nf C C 00 Capacitor LVC0APW Logic Logic Logic00 TSSOP Logic IC 0 R0 R nf C C C C C0 C C C C C C C0 00 Capacitor C C C C C C C9 C00 C0 C0 00 nf C C0 C0 00 Capacitor 00 ohm R R 00 Resistors 0 R00 R0 00 R R R R R R9 R0 R R R R0 00 R0 R0 R0 R0 R0 Bit rate select A00 DTS Microswitch JP JP JP JP JP JP JP JP JP9 JP0 JP Jumper JP JP JP JP JP JP JP JP9 JP0 JP 9 L L L9 L0 L L L00 L0 L0 MAXCPE U DIP Maxim IC Micro Reset A DTS Microswitch OSCILLATOR O OSC-0Y (0.0 MHz) Oscillator NEL Frequency Controls Inc. OSC00 OSC0 OSC0 SD-A90 SD-A90 SD-A90 DPECL (. MHz) DPECL (. MHz) DPECL (. MHz) PICLF U DIP-00 Microcontroller RJ Connector RJ-RA Pin Header 9 pin D-type RS Connector F. DB-9/F Connector SMA SMA SMA SMA SMA Connector Rosenberger K-0ME SMA SMA SMA SW-DIP SW DIPSWITCH DIP Switch

8 R R k C 0nF U A Micro Reset PICLF R 00 ohm C 00nF Mod_ABS C 00nF C 00nF C 00nF L R IN R IN T IN T IN C+ C - R L9 R L R L C 00nF O STANDBY OSCILLATOR VDD OUTPUT Man_Sw SCL SDA RS_TX RS_RX Interrupt Pwd/RST Mod_NR Mod_desel Tx_Dis Rx_LOS V+ V- VCC C 00nF 0 U R OUT R OUT T OUT T OUT C+ C - 9 C9 00nF MAXCPE PC 9 RS Connector F. Logic 9 0 LVC0APW R R R9 R0 C 00 nf RS_TX RS_RX R9 L Mod_desel Interrupt Tx_Dis R R R R C0 00 nf R0 R L0 The schematics of the evaluation board are shown in the following pages. Logic 9 0 0GFC_enable 0GbE_enable OC9_enable LVC0APW Mod_ABS Mod_NR Rx_LOS R 0k R 0k R 0k R R R9 U_pin R0 0 RJ RJ for up on EvalBoard R 0

9 J 0 PIN XFP CONNECTOR TD+ TD- Ref clk- Ref clk+ Pwd/RST Vcc RD+ RD- Rx_LOS ModNR Mod_ABS SDA SCL Vcc Vcc Vcc TxDis Interrupt Mod_des Vee C nf C nf Pwd/RST Vcc_0 SDA SCL Pin9 Pin Vcc_ Tx_Dis Interrupt Mod_Desel Vee_ Rx_LOS ModNR Mod_Abs L.uH C 00nF C 00nF JP Pin9 JP JP SW SW-DIP R 0k JP JP Vcc_ Vcc Vcc.V R 0k R 0k R 0k JP R.k R.k Man_Sw Refclk_P Refclk_N C uf SMA TD+ SMA TD- SMA Ref_clk+ SMA SMA RD+ SMA Ref_clk- SMA SMA RD- CON.0mm connector L.uH C 00nF C 00nF JP9 Vcc_ JP JP L.uH C0 00nF C 00nF JP Pin JP0 JP L.uH C 00nF C 00nF JP Vcc_ JP JP L.uH C 00nF C 00nF JP Vcc_0 JP JP9 L.uH C0 00nF C 00nF JP Vee_ JP JP0 Vcc.0V Vee.0V Vcc.V Vcc.V Vcc.V C uf C uf C9 uf C uf C9 uf CON.0mm connector CON.0mm connector CON.0mm connector CON.0mm connector CON.0mm connector CON.0mm connector

10 R0 L0 U_pin R0 L0 0 0GbE_enable 0GFC_enable Logic LVC0APW C0 00 nf R0 R0 R0 L00 OC9_enable R OC9_enable R0 0GbE_enable Refclk_N C00 00nF OSC00 Oscillator DPECL Refclk_P Refclk_N Refclk_P 0GFC_enable Refclk_N C0 00nF OSC0 Oscillator DPECL Refclk_P R00 0 R0 0 OC9_enable Refclk_N C0 00nF OSC0 Oscillator DPECL Refclk_P 0GbE_enable 0GFC_enable R0 R0 R09 0k Man_Sw Figure. Schematic for the additional components to provide on-board reference clocks R 0k A00 Bit rate select R 00 ohm

11 Errata In versions of the evaluation board prior to v. there is a trace missing in the V power supply filter (visible on the top surface between C and L). In order to use the V supply it is necessary to bypass the filtering by setting jumper JP to ON. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 00-0 Avago Technologies. All rights reserved. AV0-9EN - February, 0