STX Technical Manual & Baseboard Design Guide

Transcription

1 STX Technical Manual &

2 Disclaimers The information in this document has been carefully checked and is believed to be accurate. AXIOMTEK Co., Ltd. assumes no responsibility for any infringements of patents or other rights of third parties which may result from its use. AXIOMTEK assumes no responsibility for any inaccuracies that may be contained in this document. AXIOMTEK makes no commitment to update or to keep current the information contained in this manual. No part of this document may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of AXIOMTEK Co., Ltd. All brand and product names are trademarks or registered trademarks of their respective companies. Please visit our web site for newest version of this Hardware Specification and for other information (like Product Info or drivers). Copyright 2003 by AXIOMTEK Co., Ltd. All rights reserved. March 2003 Printed in Taiwan ii

3 Table of Contents Table of Contents... iii List of Figures... v List of Tables... v Introduction What is a STX Module? STX Baseboard STX Interface Side and View Definitions STX SoM Module Mounting Description System Block Diagram Functional Block Diagram... 5 Signal Descriptions & Pin Definitions Interface Signals Signal Summary Signal Group Location Signal Description PCI Bus Interface PCI Function Module ISA ISA Function Module IDE E-IDE Function Module FDD FDD Function Module PPI PPI Function Module SPI 1, SPI 1,2 Function Module IrDA KB/MS KB/MS Function Module USB 1& USB 1&2 Function Module USB 3& USB 3&4 Function Module ETH ETH Function Module AC AC 97 Function Module CRT CRT Function Module FPI & TV-Out FPI & TV-Out Function Module FEAT FEAT Function Module MISC JTAG JTAG Design Notes iii

4 PWR Reserved Pin Definitions P1/J1 Connector Pinout P2/J2 Connector Pinout FC2 ZV from STX Module FC1 IDE2 from STX Module Electrical Characteristics Flat Panel Interface PCI Bus Interface Clock Distribution IDSEL Mapping Interrupt Routing Signaling Voltage Level Electrical Power Requirements Mechanical Specifications STX Dimensions FPC1 and FPC2 Connectors STX Base Board Award BIOS Defaults Standard CMOS Features Advanced BIOS Features Advanced Chipset Features Integrated Peripherals Power Management Setup Wake Up Events PnP/PCI Configurations IRQ Resources DMA Resources Frequency/Voltage Control Troubleshooting Technical References Abbreviations iv

5 List of Figures Figure 1-1 Bare STX Module... 1 Figure 1-2 Boxed STX Module...2 Figure 2-1 Signal Group Location (J1 & J2 Connectors on STX Baseboard Top View)... 7 Figure 2-2 PCI Slot Sample Design Figure 2-3 PCI Slot Sample Design Figure 2-4 PCI Slot Sample Design Figure 2-5 PCI Slot Sample Design Figure 2-6 ISA Function Module Schematic Figure 2-7 IDE1 Function Module Schematic Figure 2-8 IDE2 Function Module Schematic Figure 2-9 FDD Function Module Schematic Figure 2-10 PPI Function Module Schematic Figure 2-11 SPI 1,2 Function Module Schematic Figure 2-12 Keyboard and Mouse Function Module Schematic Figure 2-13 USB 1&2 Function Module Schematic Figure 2-14 USB 3&4 Function Module Schematic Figure 2-15 ETH Function Module Schematic Figure 2-16 AC 97 Function Module Schematic Figure 2-17 CRT Function Module Schematic Figure 2-18 FPI Function Module Schematic Figure 2-19 TV-Out Function Module Schematic Figure 4-1 STX Module Dimensions Figure 4-2 STX Module Dimensions Figure 4-3 STX Module Layout Figure 4-4 STX Height Dimensions Figure 4-5 J1/J2 Connector Specifications Figure 4-6 FC1, FC2 Location of STX Baseboard Figure 4-7 FPC41 Top View v

6 List of Tables Table 1-1 STX Baseboard Format Examples... 2 Table 2-1 STX Connectors... 6 Table 2-2 STX Signal Groups (P1&P2)... 6 Table 2-3 Signal Direction... 7 Table 2-4 Driver Type... 8 Table 2-5 Signal Type... 8 Table 2-6 PCI Bus Signals Table 2-7 ISA Bus Signals 8-bit Table 2-8 ISA Bus Signals 16-bit extension Table 2-9 E-IDE Interface Signals Table 2-10 E-IDE Interface Signals Table 2-11 Floppy Disk Drive Interface Signals Table 2-12 PPI Interface Signals Table 2-13 SPI 1 Interface Signals Table 2-14 SPI 2 Interface Signals Table 2-15 IrDA Interface Signals Table 2-16 Keyboard and Mouse Signals Table 2-17 Universal Serial Bus 1 Interface Signals Table 2-18 Universal Serial Bus 3&4 Interface Signals Table 2-19 Ethernet 10/100Mbit Interface Signals Table 2-20 Audio Codec 97 Interface Signals Table 2-21 CRT Interface Signals Table 2-22 Flat Panel Interface Signals Table 2-23 FC2 Connector Pinout Table 2-24 Feature Signals Table 2-25 Miscellaneous Signals Table 2-26 Power and Ground Pins Table 2-27 STX P1 / J1 Connector Pin out Table 2-28 STX P2/J2 Connector Pin out Table 2-29 FC2 Connector Pin out Table 2-30 FC1 Connector Pin out Table 3-1 Flat Panel Pixel Data Mapping Table 3-2 DSTN and TFT Flat Panel Pixel Data Mapping Table 3-3 TFT Flat Panel Pixel Data Mapping Table 3-4 Flat Panel Interface Pins of Color DSTN and Color TFT LCD Table 3-5 Sampling Edge in 24-bitMode (FP_BSEL=1) Table 3-6 Sampling Edge in 12-bitMode (FP_BSEL=0) Table 3-7 PCI Interrupt Routing Table 3-8 STX88600 Electrical Power Requirements Table 3-9 STX88601 Electrical Power Requirements Table 4-1 STX Module Type I. Heights Table B-1 Abbreviations Used vi

7 C h a p t e r 1 Introduction 1.1 What is a STX Module? A general-purpose processing module, a STX module contains the complete functionality of common industrial PC on a very small space. STX module always provides all the functionality through its STX Interface regardless of the various memory configurations or computational power it possesses. STX s major difference to other SoMs is that STX follows the PC/104 module standard. Therefore, the current enclosure design does not need to be changed once they choose to use STX as a new solution. In case that STX Baseboard is to contain some components below the STX Module, it might be necessary to make sure that there is sufficient empty space below the STX Module. There are two STX Module types defined: For detailed description of dimensions and used plugs see Chapter 4. Mechanical Specification on. For various purposes, the STX Hardware Specification defines two types of modules: Bare STX Module Boxed STX Module Bare STX Module is only a PCB with assembled components and no cooling mechanism implemented. The Bare STX Module is targeted for high integrated embedded and industrial applications where variability is the primary goal. It is presumed that the system designer will provide necessary heat removal according to application requirements. Figure 1-1 Bare STX Module Page 1 of 84

8 Boxed STX Module has the top cover with heatsink. There is no need for additional heat removal as the heat removal capabilities of the Boxed STX Module are satisfied. Boxed STX Module is an ultimate, easy-to-upgrade solution and has to be designed to comply with mechanical specification. Figure 1-2 Boxed STX Modules 1.2 STX Baseboard STX Baseboard provides receptacles for STX Module, supplies it with power and interfaces it with peripherals and expansion slots. The STX Baseboard can be designed in accordance with different formats AT, ATX, LPX, NLX, PC-104 or custom format. Table 1-1 Format desktop PC-104+ bare minimal STX Baseboard Format Examples Description ATX form factor Baseboard with standard desktop connectors and functionality including ISA/PCI expansion slots all the required connectors and PC-104+ interface for typical PC-104+ applications all the required connectors (CRT, keyboard/mouse, IDE, floppy, net, audio etc.) for standalone applications defined as bare with PC-104 size 1.3 STX Interface The STX Interface is an assembly of two pairs of 200-pin AMP connectors two plugs on STX Module and two receptacles on STX Baseboard. The STX Interface uses 400 pins total. The plugs used on STX Module are referred to as P1 and P2 while the opposite receptacles used on STX Baseboard are referred to as J1 and J2. For more information see chapter 4. Mechanical Specification. Page 2 of 84

9 1.4 Side and View Definitions STX Module Bottom side of the STX Module is defined as the side equipped with the STX Interface plugs. Top side is the opposite side. Top view for the STX Module is defined as view at the top side. In opposite, bottom view is defined as view at the bottom side. STX Baseboard Top side of the STX Baseboard is defined as the side equipped with the STX Interface receptacles. Bottom side is the opposite side. Top view for the STX Baseboard is defined as view at the top side. In opposite, bottom view is defined as the bottom side. 1.5 STX SoM Module AXIOMTEK s STX is a STX form factor SoM (System On Module) that comes with low power consumption processors (i.e., VIA Eden and INTEL ULV-PIII), core logic, graphics controller with CRT/LCD/TV-out, multiple I/O, fast Ethernet controller and AC-link interface for external audio Codec output. In addition to these integrated features onboard the STX, the STX standard interface provides 4 PCI Masters and ISA output for expansion design purpose applied on the related Baseboard. With AXIOMTEK s STX SoMs, customers can now adapt various I/O combinations for different application purposes while maintaining the same hardware kernel. The SoM architecture of AXIOMTEK basically follows the standard STX definition with Type-II module and configuration No. 2 stacking combination. In addition to the standard pin-out from STX interfaces, AXIOMTEK s STX SoM provides additional functions from it such as USB 3/4 from STX interface N/C pins, max. Of up to 36-bit TTL LCD plus STN, TV-out and ZV port support. Other than 24-bit from STX interface, AXIOMTEK defines a 41-pin FPC connector on the edge of SoM located on the back side of STX SoM, and an IDE2 port via 2nd 41-pin FPC connector on the components side of AXIOMTEK s STX SoM. Basically, the STX SoM only provides key kernel computing functions as engine; other I/O signal converting and interfacing are done through the Baseboard. Like AC-link, this is a digital signal for Audio, Modem control; but this signal cannot be used without converted into analog interface. Therefore, we need to have a Baseboard which is equipped with AC 97 Codec to convert these AC-link digital signals to become the real world can accept type as analog. Page 3 of 84

10 1.5.1 Mounting Description Mounting orientation of the SoM is similar with the stack mounting of PC/104 modules. However, the stacking between SoM and Baseboard goes through STX connectors with 2 male connectors on SoM and 2 female connectors for the Baseboard. These connectors are 6.6 mm height plugs that allow the use of the components on the STX Baseboard underneath the STX Module. Basically, board-to-board is horizontal, but interface connectors are vertical. At this moment, there is no clear indication/explanation describing multiple stacking from the rear side of the Baseboard. The current STX-compatible Baseboards are STB86600, STB97100, STB97200, STB97300 and STB More Baseboards will be added soon in AXIOMTEK s product line. 1.6 System Block Diagram Page 4 of 84

11 1.7 Functional Block Diagram Page 5 of 84

12 2.1 Interface Signals C h a p t e r 2 Signal Descriptions & Pin Definitions Table 2-1 Connectors STX base board Connector STX base board Connector ZV from STX module IDE2 from STX module STX Connectors Label P1 P2 FC2 FC1 2.2 Signal Summary Table 2-2 Signal Group Group Description Pins Count PCI PCI Bus 60 ISA ISA Bus 88 E-IDE E-IDE Interface 28 FDD Floppy Disk Drive Interface 15 PPI PPI Interface 17 SPI1 Serial Port 1 Interface 8 SPI2 Serial Port 2 Interface 8 IrDA IrDA Interface 2 KB/MS Keyboard and PS/2 Mouse Signals 4 USB 1&2 Universal Serial Bus 1 Interface 3 USB3&4 Universal Serial Bus 3 and 4 Interface 3 ETH Ethernet 10/100Mbit Interface 6 AC 97 Audio Codec 97 Interface 5 CRT CRT Interface 9 FPI Flat Panel Interface 36 FEAT Feature Signals 7 MISC Miscellaneous Signals 9 JTAG JTAG/Boundary Scan Signals 5 PWR Power and Ground Pins 81 RSVD Reserved Pins 6 Total 400 STX Signal Groups (P1&P2) Page 6 of 96 AXIOMTEK reserves the right to make improvements to this document and/or product at any time and without notice. STXVEA STX Module Data book Version 1.0, March 2003 :

13 2.3 Signal Group Location Figure 2-1 Signal Group Location (J1 & J2 Connectors on STX Baseboard Top View) 2.4 Signal Description This section describes all the signals (sorted in alphabetical order) in each group. The following notations are used to describe the signal direction: Table 2-3 Symbol I O B DC Signal Direction Input-only signal Output-only signal Description Bi-directional input / output signal Refers to power or ground pins that are not used for any information transfer. Page 7 of 84

14 The signal description also includes the output driver type used for the particular signal: Table 2-4 Symbol TP OD TS STS A Driver Type Standard totem pole active driver Description Open-drain driver allows multiple devices to share a signal as a wire-or. A pull-up resistor is required to sustain the inactive state. Output or bi-directional tri-state pin driver Sustained tri-state is an active low tri-state signal owned and driven by one and only one device at a time. The device that drives a STS pin low must drive it high for at least one clock before letting it float. A new device cannot start driving a STS signal any sooner than one clock after the previous owner tri-states it. A pull-up resistor is required to sustain the inactive state until another device drives it. Analog output driver The following notation is used if pull-up or pull-down resistor is implemented on the STX Module: Table 2-5 Symbol U D Signal Type Description Pull-up resistor is implemented on the STX Module. Pull-down resistor is implemented on the STX Module. Whole signal type is composed from one or more of these symbols divided by a hyphen. For example, B-STS-U means bi-directional sustained tri-state signal with pull-up resistor implemented on the STX Module. Page 8 of 84

15 2.4.1 PCI Bus Interface STX Interface supports up to three PCI devices or slots. The clock distribution for each PCI device is 33MHz, under any CPU so long as the skew requirement is within 500PS. Signal Pin Type Description AD0 J1/43 B-TS Address and Data are multiplexed signals connected to the PCI AD1 J1/45 address/data bus. Address is driven during the address phase with FRAME# assertion, data is driven or received in the following clocks. AD2 J1/48 AD3 J1/51 AD4 J1/49 AD5 J1/50 AD6 J1/55 AD7 J1/56 AD8 J1/57 AD9 J1/60 AD10 J1/61 AD11 J1/62 AD12 J1/67 AD13 J1/68 AD14 J1/66 AD15 J1/69 AD16 J1/96 AD17 J1/97 AD18 J1/98 AD19 J1/103 AD20 J1/104 AD21 J1/102 AD22 J1/105 AD23 J1/108 AD24 J1/114 AD25 J1/117 AD26 J1/120 AD27 J1/123 AD28 J1/121 AD29 J1/122 AD30 J1/129 AD31 J1/127 Page 9 of 84

16 C/BE0# J1/54 C/BE1# J1/72 C/BE2# J1/95 C/BE3# J1/116 CLK3 J1/145 CLK2 J1/141 CLK1 J1/144 CLK0 J1/115 B-TS O-TP Bus Command and Byte Enables define the bus command during the address phase of a transaction, while are used as byte enables during the data phase. The byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE[0]# applies to byte 0 (LSB) and C/BE[3]# applies to byte 3 (MSB). Clock provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals, except RST#, INT[D..A]#, are sampled on the rising edge of CLK and all other timing parameters are defined with respect to this edge. Currently the STX supports 33 MHz frequency. DEVSEL# J1/87 B-STS-U Device Select indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. FRAME# J1/90 B-STS-U Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is disserted, the transaction is in the final data phase or has completed. GNT0# J1/135 GNT1# J1/138 GNT2# J1/136 GNT3# J1/33 INTA# J1/154 INTB# J1/155 INTC# J1/153 INTD# J1/152 O-TS B-OD-U Grant indicates to the agent that access to the bus has been granted. This is a point to point signal. Every master has its own GNT# which must be ignored while RST# is asserted. Interrupts are level sensitive, asserted low, using open drain output drivers. A device asserts its INTx# line when requesting attention from its device driver. Once the INTx# signal is asserted, it remains asserted until the device driver clears the pending request. When the request is cleared, the device desserts its INTx# signals. IRDY# J/89 B-STS-U Initiator Ready indicates the initiating agents (bus masters) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on AD[31..00]. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. Continued..... Page 10 of 84

17 Signal Pin Type Description LOCK# J1/81 B-STS-U Lock indicates an atomic operation that may require multiple transactions to complete. When LOCK# is asserted, non-exclusive transactions may proceed to an address that is not currently locked. PAR J1/75 B-TS Parity is even parity across AD[31..00] and C/BE[3..0]#. Parity generation is required by all PCI agents. PAR is stable and valid one clock after the address phase. For data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. The master drives PAR for address and write data phases; the target drives PAR for read data phases. PERR# J1/80 B-STS-U Parity Error reports data parity errors during all PCI transactions except a Special Cycle. The PERR# pin is sustained tri-state and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected. REQ3# J1/130 REQ2# J1/128 REQ1# J1/137 REQ0# J1/127 I-U Request indicates to the arbiter that this agent desires use of the bus. This is a point to point signal. Every master has its own REQ# which must be tri-stated while RST# is asserted. RST# J1/151 O-TP Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. Any time RST# is asserted, all PCI output signals must be driven to their benign state. SERR# J1/74 B-OD-U System Error reports address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. SERR# is open drain output and is actively driven for a single PCI clock by the agent reporting the error. STOP# J1/82 B-STS-U Stop indicates the current target is requesting the master to stop the current transaction. TRDY# J1/88 B-STS-U Target Ready indicates the target agent s (selected device s) ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that valid data is present on AD[31..00]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. Table 2-6 PCI Bus Signals Page 11 of 84

18 PCI Function Module The standard STX interface can support up to four PCI devices or slots on the Baseboard and only up to three PCI devices with bus master capability. AXIOMTEK module, however, can support four PCI devices with BUS master capability. Sample Design for Four PCI Slot on STX Baseboard. The trace length of all PCI clocks should be similar. The trace attribute of all clocks and signals must have a minimum of 6 mils width and 12 mils between two adjacent traces. J1/155 J1/152 J1/145 J1/130 J1/127 J1/122 J1/123 J1/117 J1/116 J1/108 J1/102 J1/103 J1/97 J1/95 J1/89 J1/87 J1/81 J1/80 J1/74 J1/72 J1/66 J1/67 J1/61 J1/57 J1/56 J1/50 J1/51 J1/45 VCC5 VCC12 VCC5 INTB INTD CLK0 REQ0 AD31 AD29 AD27 AD25 C_BE3 AD23 AD21 AD19 AD17 C_BE2 IRDY DEVSEL PLOCK PERR SERR C_BE1 AD14 AD12 AD10 AD8 AD7 AD5 AD3 AD1 VCC3 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 PCI1-12V TCK TDO +5V +5V INTB INTD PRSNT1 RESERVED PRSNT2 RESERVED CLK REQ +5V AD31 AD29 AD27 AD V C/BE3 AD23 AD21 AD V AD17 C/BE2 IRDY +3.3V DEVSEL LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 AD12 AD10 AD8 AD7 +3.3V AD5 AD3 AD1 +5V ACK64 +5V +5V TRST +12V TMS TDI +5V INTA INTC +5V RESERVED +5V RESERVED 3.3V_AUX RST +5V GNT PME AD V AD28 AD26 AD24 IDSEL +3.3V AD22 AD20 AD18 AD V FRAME TRDY STOP +3.3V SDONE SBO PAR AD V AD13 AD11 AD9 C/BE0 +3.3V AD6 AD4 AD2 AD0 +5V REQ64 +5V +5V VCC5 VCC3 VCC12 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 INTA INTC PCI_RST GNT1 PME AD30 AD28 AD26 AD24 AD21 AD22 AD20 AD18 AD16 FRAME E TRDY STOP PAR AD15 AD13 AD11 AD9 C_BE0 0 AD6 AD4 AD2 AD0 VCC5 3VSB J1/154 J1/153 J1/151 J1/135 J1/110 J1/129 J1/121 J1/120 J1/114 J1/105 J1/104 J1/98 J1/96 J1/90 J1/88 J1/82 J1/75 J1/69 J1/68 J1/62 J1/60 J1/54 J1/55 J1/49 J1/48 J1/43 Figure 2-2 PCI Slot Sample Design 1 Page 12 of 84

19 Page 13 of 84 B14 INTC INTA VCC5 3VSB VCC12 VCC3 VCC5 PCI2 VCC12 VCC5 VCC3 J1/154 VCC5 J1/141 J1/128 J1/127 J1/122 J1/123 J1/117 J1/116 J1/108 J1/102 J1/103 J1/97 J1/95 J1/89 J1/87 J1/81 J1/80 J1/74 J1/72 J1/66 J1/67 J1/61 J1/57 J1/56 J1/50 J1/51 J1/45 AD21 J1/151 J1/138 J1/110 J1/129 J1/121 J1/120 J1/114 J1/105 J1/104 J1/98 J1/96 J1/90 J1/88 J1/82 J1/75 J1/69 J1/68 J1/62 J1/60 J1/54 J1/55 J1/49 J1/48 J1/43 J1/153 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B10 B11 B12 B13 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B1 B2 B3 B4 B5 B6 B7 B8 B9 CLK1 REQ1 AD31 AD29 AD27 AD25 C_BE3 AD23 AD19 AD17 C_BE2 IRDY DEVSEL PLOCK PERR SERR C_BE1 AD14 AD12 AD10 AD8 AD7 AD5 AD3 AD1 AD21 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 INTD INTB PCI_RST GNT1 AD30 AD28 AD26 AD24 AD22 AD20 AD18 AD16 FRAME TRDY STOP PAR AD15 AD13 AD11 AD9 C_BE0 AD6 AD4 AD2 AD0 J1/154 J1/152 IDSEL TDI RESERVED RESERVED +5V +5V +5V +5V +5V +5V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +12V +5V AD0 AD2 AD4 AD6 AD9 AD11 AD15 AD13 AD16 AD18 AD20 AD22 AD26 AD24 AD28 AD30 GNT PME REQ64 C/BE0 SDONE PAR SBO STOP TRDY FRAME RST 3.3V_AUX INTA INTC TRST TMS -12V TCK TDO +5V +5V INTB INTD PRSNT1 RESERVED PRSNT2 RESERVED CLK +5V +5V +5V +5V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V AD12 AD10 AD8 AD7 AD5 AD3 AD1 AD31 AD29 AD27 AD25 AD23 AD21 AD19 AD17 AD14 REQ C/BE3 C/BE2 IRDY DEVSEL LOCK SERR C/BE1 ACK64 PERR Figure 2-3 PCI Slot Sample Design 2

20 J1/152 J1/155 J1/141 J1/137 J1/127 J1/122 J1/123 J1/117 J1/116 J1/108 J1/102 J1/103 J1/97 J1/95 J1/89 J1/87 J1/81 J1/80 J1/74 J1/72 J1/66 J1/67 J1/61 J1/57 J1/56 J1/50 J1/51 J1/45 VCC5 VCC12 VCC5 VCC3 INTD INTB CLK2 REQ2 AD31 AD29 AD27 AD25 C_BE3 AD23 AD21 AD19 AD17 C_BE2 IRDY DEVSEL PLOCK PERR SERR C_BE1 AD14 AD12 AD10 AD8 AD7 AD5 AD3 AD1 PCI3 B1-12V B2 TCK B3 B4 TDO B5 +5V B6 +5V B7 INTB B8 B9 INTD B10 PRSNT1 RESERVED B11 B12 PRSNT2 B13 B14 RESERVED B15 B16 CLK B17 B18 B19 REQ +5V B20 B21 AD31 B22 AD29 B23 B24 AD23 B25 AD V B26 B27 C/BE3 B28 AD23 B29 B30 AD21 B31 AD19 B V B33 AD17 B34 C/BE2 B35 J1/122 B36 IRDY +3.3V B37 B38 DEVSEL B39 B40 LOCK B41 PERR +3.3V B42 B43 SERR B V B45 C/BE1 B46 AD14 B47 B48 AD12 B49 AD10 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 AD8 AD7 +3.3V AD5 AD3 AD1 +5V ACK64 +5V +5V TRST +12V TMS TDI +5V INTA INTC +5V RESERVED +5V RESERVED 3.3V_AUX RST +5V GNT PME AD V AD28 AD26 AD24 IDSEL +3.3V AD22 AD20 AD18 AD V FRAME TRDY STOP +3.3V SDONE SBO PAR AD V +3.3V AD11 AD9 C/BE0 +3.3V AD6 AD4 AD2 AD0 +5V REQ64 +5V +5V VCC5 VCC3 VCC12 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 INTC INTA PCI_RST GNT2 PME AD30 AD28 AD26 AD24 AD22 AD20 AD18 AD16 FRAME TRDY STOP PAR AD15 AD13 AD11 AD9 C_BE0 AD6 AD4 AD2 AD0 J1/151 J1/151 J1/110 J1/129 J1/121 J1/120 J1/114 J1/105 J1/104 J1/98 J1/96 J1/90 J1/88 J1/82 J1/75 J1/69 J1/68 J1/62 J1/60 3VSB J1/153 J1/154 J1/54 J1/55 J1/49 J1/48 J1/43 VCC5 Figure 2-4 PCI Slot Sample Design 3 Page 14 of 84

21 Figure 2-5 PCI Slot Sample Design 4 Page 15 of 84

22 2.4.2 ISA STX Interface supports both 8-bit ISA and 16-bit ISA extensions. Signal Pin Type Description AEN J2/50 O-TP Address Enable is driven by the Permanent Master to indicate that the address lines are driven by a DMA controller. The assertion of AEN disables response to I/O port addresses when the I/O command strobes are asserted. When AEN is asserted only the device asserting DRQn should respond. BALE J2/186 O-TP Bus Address Latch Enable is used to latch valid addresses from the current master on the falling edge of BALE. DACK3# J2/84 DACK2# J2/170 DACK1# J2/100 DACK0# J2/104 DRQ0 J2/112 DRQ1 J2/106 DRQ2 J2/24 DRQ3 J2/92 O-TP I-D DMA Acknowledges is driven by the Permanent Master to indicate that a DMA operation can begin. They are driven at all times for those DMA channels that are attached. DMA Requests are driven by a DMA bus adapter to indicate a request for a DMA bus operation. DRQ[3..1] request 8-bit DMA operations. All bus DMA adapters will drive these lines with a tri-state driver. The Permanent Master monitors this signal to determine which if any of the DMA devices are requesting the bus. ENDXFR# J2/32 I-U End of Transfer is asserted by a 16-bit memory mapped device that may cause an early termination of the current transfer. It should be gated with MEMR# or MEMW# and is not valid during DMA transfers. It is called 0WS# on some implementations. IOCHCHK# J2/4 I-U I/O Channel Check is driven active by an adapter detecting a fatal error during bus operation. This open collector signal is driven low typically causing a nonmaskable interrupt. IOCHRDY J2/42 B-OD-U I/O Channel Ready is driven inactive by the target of either a memory or I/O operation to extend the current cycle. This open collector signal is driven based on the system address and the appropriate control strobe. IOR# J2/76 B-TS-U I/O Read is driven to indicate an I/O read operation. I/O mapped devices using this strobe should decode for selection of adapter and address based on SA[15..00] and AEN. Additionally, DMA devices will use IOR# in conjunction with the appropriate DACKn# to decode a DMA transfer from the I/O device. IOW# J2/68 B-TS-U I/O Write is driven to indicate an I/O write operation. I/O mapped devices using this strobe should decode for selection of adapter and address based on SA[15..00] and AEN. Additionally, DMA devices will use IOW# in conjunction with the appropriate DACKn# to decode a DMA transfer from the I/O device. Continued..... Signal Pin Type Description Page 16 of 84

23 IRQ9, J2/16 IRQ7 J2/122 IRQ6 J2/138 IRQ5 J2/146 IRQ4 J2/154 IRQ3 J2/162 I-U Interrupt Requests indicate the presence of an interrupting bus adapter. Because of the use of pull-ups, unused interrupt inputs must be masked. OSC J2/194 O-TP Oscillator This is a clock signal with a MHz frequency. REFRESH# J2/114 B-TS-U Refresh is driven by the Current Master to indicate a memory refresh operation. RESETDRV J2/8 O-TP Reset Drive indicates that the adapter should be brought to an initial reset condition. SA0 J2/198 SA1 J2/196 SA2 J2/192 SA3 J2/188 SA4 J2/180 SA5 J2/172 SA6 J2/164 SA7 J2/160 SA8 J2/148 SA9 J2/140 SA10 J2/132 SA11 J2/124 SA12 J2/116 SA13 J2/108 SA14 J2/94 SA15 J2/90 SA16 J2/82 SA17 J2/74 SA18 J2/66 SA19 J2/58 B-TS System Address signals define the selection with the granularity of one byte within the 1 MB section of memory defined by the LA[19..17] address lines. The address lines SA[19..17] that are coincident with LA[19..17] are defined to have the same value as LA[19..17] for all memory cycles. During a refresh initiated transfer only SA[7..0] are valid. Continued..... Page 17 of 84

24 Signal Pin Type Description SD0 J2/34 B-TS System Data are defined for the low order byte of a 16-bit bus and the only bus SD1 J2/30 for 8-bit adapters and systems. Memory or I/O transfers on this bus are defined SD2 J2/26 for 8-bit operations with even or odd addresses and for 16-bit operations for odd SD3 J2/22 addresses only. The signals SA0 and SBHE# are used to define the data present SD4 J2/18 on this bus. SD5 J2/14 SD6 J2/10 SD7 J2/6 SMEMR# J2/60 O-TP Standard Memory Read is driven to indicate a memory read operation in the first 1 MB of system memory. Memory mapped devices using this strobe should decode addresses SA[19..00] only. SMEMW# J2/52 O-TP Standard Memory Write is driven to indicate a memory write operation in the first 1 MB of system memory. Memory mapped devices using this strobe should decode addresses SA[19..00] only. SYSCLK J2/122 O-TP System Clock is the reference clock for the ISA bus. This clock signal may vary in frequency from 6 MHz to 8.33 MHz. TC J2/178 O-TP Terminal Count is asserted during a read or writes command indicating that the DMA controller has reached a terminal count for the current transfer. DACKn# must be presented by the bus adapter to validate the TC signal. Table 2-7 ISA Bus Signals 8-bit The following table shows signals in 16-bit ISA extension. Signal Pin Type Description DACK7# J2/152 O-TP DMA Acknowledges is driven by the Permanent Master to indicate that a DMA DACK6# J2/136 operation can begin. They are driven with a totem pole driver at all times for DACK5# J2/120 those DMA channels that are attached. DRQ7 J2/160 I-D DMA Requests are driven by a DMA bus adapter to indicate a request for a DMA bus operation. DRQ[7..5] request 16-bit DMA DRQ6 J2/144 operations while DRQ0 requests 8-bit DMA operations. All bus DMA adapters will drive these lines with a tri-state driver. The DRQ5 J2/128 Permanent Master monitors this signal to determine which if any of the DMA devices are requesting the bus. IOCS16# J2/54 I-U 16 bit I/O Chip Select is driven by an I/O mapped adapter indicating that the I/O device located at the address on the bus is 16 bits wide. This signal is driven based only on SA[15..00] when AEN is not asserted. IRQ15 J2/86 I-U Interrupt Requests indicate the presence of an interrupting bus IRQ14 J2/94 adapter. Because of the use of pull-ups, unused interrupt inputs IRQ12 J2/78 must be masked. IRQ11 J2/70 IRQ10 J2/62 Continued..... Page 18 of 84

25 Signal Pin Type Description LA17 J2/102 B-TS Latched Address signals define the selection of a 128 KB of memory LA18 J2/96 space within the 16 MB address range of the 16-bit data bus. These signals are not defined for I/O access. LA19 J2/88 LA20 J2/80 LA21 J2/72 LA22 J2/64 LA23 J2/56 MASTER# J2/176 I-U Master is driven by a DMA bus adapter to indicate that the adapter is going to drive the system address, data and control lines. MEMCS16# J2/46 B-OD-U 16 bit Memory Chip Select is driven by a memory mapped adapter indicating that the memory device located at the address on the bus is 16 bits wide. This signal is driven based on LA[23..17] only. MEMR# J2/110 B-TS-U Memory Read is driven to indicate a memory read operation. Memory mapped devices using this strobe should decode addresses LA[23..17] and SA[19..00]. MEMW# J2/118 B-TS-U Memory Write is driven to indicate a memory write operation. Memory mapped devices using this strobe should decode addresses LA[23..17] and SA[19..00]. SBHE# J2/48 B-TS System Byte High Enable indicates that a byte is being transferred on the upper byte (SD[15..08]) of the 16-bit bus. SD8 J2/126 SD9 J2/134 SD10 J2/142 SD11 J2/150 SD12 J2/158 SD13 J2/166 SD14 J2/174 SD15 J2/182 Table 2-8 B-TS ISA Bus Signals 16-bit extension System Data are defined for the high order byte of a 16-bit bus. Memory or I/O transfers on this bus are defined when SBHE# is active ISA Function Module The standard STX interface supports both 8-bit ISA and 16-bit extensions. STX Interface supports ISA devices on the Baseboard. All pull-ups are integrated on the STX module. Page 19 of 84

26 Figure 2-6 ISA Function Module Schematic Page 20 of 84

27 2.4.3 IDE STX Interface supports one E-IDE channel for two (master and slave) devices. If the STX Module contains an on-board IDE device, this device should be connected to different E-IDE channel than the one that is connected to STX Interface. Signal Pin Type Description CS0 J2/53 O-TP Chip Selects are used to select the Command Block or Control CS1 J2/55 Block registers. When DMACK# is asserted, CS[1..0]# shall be negated and transfers shall be 16 bits wide. DA2 J2/51 DA1 J2/47 DA0 J2/49 DD0 J2/31 DD1 J2/27 DD2 J2/23 DD3 J2/19 DD4 J2/15 DD5 J2/7 DD6 J2/5 DD7 J2/3 DD8 J2/5 DD9 J2/9 DD10 J213 DD11 J2/17 DD12 J2/21 DD13 J2/25 DD14 J2/29 DD15 J2/33 O-TP B-TS Device Address is the 3-bit binary coded address asserted by the host to access a register or data port in the device. Device Data is an 8-bit or 16-bit bi-directional data interface between the host and the device. The lower 8 bits are used for 8-bit register transfers. Data transfers are 16 bits wide except for devices that implement 8-bit data transfers only. DIOR# J2/41 O-TS Device I/O Read is the strobe signal asserted by the host to read device registers or the Data port. In Ultra DMA mode this pin is used for Ultra DMA Ready (HDMARDY#) and Ultra DMA Data Strobe (HSTROBE). DIOW# J2/39 O-TS Device I/O Write is the strobe signal asserted by the host to write device registers or the Data port. In Ultra DMA mode this pin is used for Stop Ultra DMA burst (STOP). DMACK# J2/45 O-TP DMA Acknowledge shall be used by the host in response to DMARQ to initiate DMA transfers. DMARQ J2/37 I-D DMA Request is used for DMA data transfers between host and device and shall be asserted by the device when the device is ready to transfer data to or from the host. The direction of data Page 21 of 84

28 transfer is controlled by DIOR# and DIOW#. The device shall wait until the host asserts DMACK# before negating DMARQ, and re-asserting DMARQ if there is more data to transfer. INTRQ J2/35 I-U Device Interrupt is used by the selected device to interrupt the host system when interrupt pending is set. This signal shall be released when the device is not selected. IORDY J2/43 I-U I/O Channel Ready is negated to extend the host transfer cycle of any host register access (read or write) when the device is not ready to respond to a data transfer request. In Ultra DMA mode this pin is used for Ultra DMA Ready (DDMARDY#) and Ultra DMA Data Strobe (DSTROBE). RESET# J2/1 O-TP Hardware Reset is used by the host to reset the device. Table 2-9 E-IDE Interface Signals Page 22 of 84

29 E-IDE Function Module Figure 2-7 IDE1 Function Module Schematic Page 23 of 84

30 Signal Pin Type Description CS0 FC1/38 O-TP Chip Selects are used to select the Command Block or Control CS1 FC1/39 Block registers. When DMACK# is asserted, CS[1..0]# shall be negated and transfers shall be 16 bits wide. DA2 DA1 DA0 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DIOR# DIOW# DMACK# DMARQ INTRQ FC1/37 FC1/33 FC1/36 FC1/22 FC1/20 FC1/17 FC1/15 FC1/11 FC1/9 FC1/6 FC1/4 FC1/5 FC1/7 FC1/10 FC1/12 FC1/16 16 FC1/18 FC1/21 FC1/23 O-TP B-TS FC1/28 O-TS FC1/27 O-TS FC1/30 O-TP FC1/26 I-D FC1/32 I-U Device Address is the 3-bit binary coded address asserted by the host to access a register or data port in the device. Device Data is an 8-bit or 16-bit bi-directional data interface between the host and the device. The lower 8 bits are used for 8-bit register transfers. Data transfers are 16 bits wide except for devices that implement 8-bit data transfers only. Device I/O Read is the strobe signal asserted by the host to read device registers or the Data port. In Ultra DMA mode this pin is used for Ultra DMA Ready (HDMARDY#) and Ultra DMA Data Strobe (HSTROBE). Device I/O Write is the strobe signal asserted by the host to write device registers or the Data port. In Ultra DMA mode this pin is used for Stop Ultra DMA burst (STOP). DMA Acknowledge shall be used by the host in response to DMARQ to initiate DMA transfers. DMA Request is used for DMA data transfers between host and device and shall be asserted by the device when the device is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR# and DIOW#. The device shall wait until the host asserts DMACK# before negating DMARQ, and re-asserting DMARQ if there is more data to transfer. Device Interrupt is used by the selected device to interrupt the host system when interrupt pending is set. This signal shall be released when the device is not selected. Page 24 of 84

31 IORDY RESET# FC1/29 I-U I/O Channel Ready is negated to extend the host transfer cycle of any host register access (read or write) when the device is not ready to respond to a data transfer request. In Ultra DMA mode this pin is used for Ultra DMA Ready (DDMARDY#) and Ultra DMA Data Strobe (DSTROBE). FC1/2 O-TP Hardware Reset is used by the host to reset the device. Table 2-10 E-IDE Interface Signals Page 25 of 84

32 Figure 2-8 IDE2 Function Module Schematic Page 26 of 84

33 2.4.4 FDD STX Interface supports one or two standard floppy disk drives. Signal Pin Type Description DENSEL J2/59 O-TP Density Select indicates whether a high density data rate (500 Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is selected. DIR# J2/71 O-TP Direction signal determines the direction of the FDD head movement (active=step in, inactive=step out) during a seek operation. During reads or writes, DIR# is inactive. DR0# J2/67 DR1# J2/65 O-TP Drive Select 1 and 0 signals are the decoded drive select output signals. DSKCHG# J2/87 I-U Disk Change indicates whether or not the drive door has been opened. HDSEL# J2/85 O-TP Head Select determines which side of the FDD is accessed. Active low selects side 1, inactive selects side 0. INDEX# J2/61 I-U Index indicates the beginning of a FDD track. MTR0# J2/63 MTR1# J2/69 O-TP Motor Select 1 and 0 motor enable lines for drives 1 and 0 respectively. RDATA# J2/83 I-U Read Data holds raw serial data read from the FDD. STEP# J2/73 O-TP Step signal issues pulses to the disk drive at a programmable rate to move the head during a seek operation. TRK0# J2/79 I-U Track 0 indicates to the controller that the head of the selected floppy disk drive is at track 0. WDATA# J2/75 O-TP Write Data holds the write precompensated serial data that is written to the selected floppy disk drive. WGATE# J2/77 O-TP Write Gate enables the write circuitry of the selected disk drive. WP# J2/81 I-U Write Protected indicates that the disk in the selected drive is writing protected. Table 2-11 Floppy Disk Drive Interface Signals Page 27 of 84

34 FDD Function Module The standard STX interface supports one or two standard floppy disk drive. The following diagram shows the proper design layout of all circuitry when defining the FDD function module. Figure 2-9 FDD Function Module Schematic Page 28 of 84

35 2.4.5 PPI STX Interface supports one parallel port to connect to printers, mass storage units and other devices. Signal Pin Type Description ACK# J2/117 I-U Acknowledge signal is pulsed low by the printer to indicate that it has received data from the parallel port. AFD# J2/93 O-U Automatic Feed forces the printer to automatically feed a line after printing each line. BUSY J2/119 I-U Busy is set high by the printer when it cannot accept another character. ERR# J2/97 I-U Error is set active low by the printer when it has detected an error. INIT# J2/101 O-U Initialize causes the printer to be initialized when this signal is low. PD0 J2/95 PD1 J2/99 PD2 J2/103 PD3 J2/107 PD4 J2/109 PD5 J2/111 PD6 J2/113 PD7 J2/115 B-U PPI Data transfer data from the appropriate parallel port data register to the peripheral data bus. Can be configured as a bi-directional bus also. PE J2/121 I-U Paper End is set high by the printer when it is out of paper. SLCT J2/123 I-U Select is set active high by the printer when the printer is selected. SLIN# J2/105 O-U Select Input selects the printer when this signal is low. STB# J2/91 O-U Data Strobe indicates to the printer that valid data is available at the printer port. Table 2-12 PPI Interface Signals PPI Function Module STX Interface supports one parallel port to connect to printers, mass storage and other device. The following diagram shows the proper design layout of all circuitry when defining the PPI function module. Page 29 of 84

36 Figure 2-10 PPI Function Module Schematic Page 30 of 84

37 2.4.6 SPI 1,2 Serial port interface on the STX Interface is TTL-level only. STX Baseboard can convert the SPI to RS-232, RS-485 or other protocols depending on application needs. Signal Pin Type Description CTS1# J2/139 I-U Clear to Send indicates that the modem or other data transfer device is ready to exchange data. DCD1# J2/127 I-U Data Carrier Detected indicates that the modem or other data transfer device has detected the data carrier. DSR1# J2/135 I-U Data Set Ready indicates that the data transfer device, e.g. modem, is ready to establish a communications link. DTR1# J2/133 O-TP Data Terminal Ready indicates to the modem or other data transfer device that the corresponding UART is ready to establish a communications link. RI1# J2/141 I-U Ring Indicator indicates that a telephone ring signal has been received by the modem. RTS1# J2/137 O-TP Request to Send indicates to the modem or other data transfer device that the corresponding UART is ready to exchange data. SIN1 J2/129 I-U Serial Input receives composite serial data from the communications link (peripheral device, modem or other data transfer device). SOUT1 J2/131 O-TP Serial Output sends composite serial data to the communications link (peripheral device, modem or other data transfer device). Table 2-13 SPI 1 Interface Signals Signal Pin Type Description CTS2# J2/155 I-U Clear to Send indicates that the modem or other data transfer device is ready to exchange data. DCD2# J2/143 I-U Data Carrier Detected indicates that the modem or other data transfer device has detected the data carrier. DSR2# J2/151 I-U Data Set Ready indicates that the data transfer device, e.g. modem, is ready to establish a communications link. DTR2# J2/149 O-TP Data Terminal Ready indicates to the modem or other data transfer device that the corresponding UART is ready to establish a communications link. RI2# J2/157 I-U Ring Indicator indicates that a telephone ring signal has been received by the modem. RTS2# J2/153 O-TP Request to Send indicates to the modem or other data transfer device that the corresponding UART is ready to exchange data. SIN2 J2/145 I-U Serial Input receives composite serial data from the communications link (peripheral device, modem or other data transfer device). SOUT2 J2/147 O-TP Serial Output sends composite serial data to the communications link (peripheral device, modem or other data transfer device). Table 2-14 SPI 2 Interface Signals Page 31 of 84

38 SPI 1,2 Function Modules Serial port interface on the STX interface is TTL-level only. STX Baseboard can convert the SPI to RS-232, RS-485 or protocols based on application needs. The following diagram shows the proper design layout of all circuitry when defining the SPI 1,2 function modules. Page 32 of 84

39 Note: The resistor reserved for IBSmm STX module. Because need the design to setting I/O address. If use the Axiomtek STX module doesn t need it. Figure 2-11 SPI 1,2 Function Module Schematic Page 33 of 84

40 2.4.7 IrDA Supported IrDA protocols are not a part of this STX Hardware Specification, see datasheet of the particular STX Module. Signal Pin Type Description IR_RX J1/38 I-U Infrared Reception is used for infrared serial input data. IR_TX J1/40 O-TP Infrared Transmit is used for infrared serial output data. Table 2-15 IrDA Interface Signals KB/MS STX Interface supports standard AT- and PS/2-style keyboards and PS/2-style pointing devices (mouse, touchpad etc.) Signal Pin Type Description KBCLK J1/21 B-OD-U Keyboard Clock transfers the keyboard clock between the keyboard controller and the keyboard using the PS/2 protocol. KBDATA J1/23 B-OD-U Keyboard Data transfers the keyboard data between the keyboard controller and the keyboard using the PS/2 protocol. MSCLK J1/25 B-OD-U Mouse Clock transfers the mouse clock between the controller and the pointing device using the PS/2 protocol. MSDATA J1/27 B-OD-U Mouse Data transfers the mouse data between the controller and the pointing device using the PS/2 protocol. Table 2-16 Keyboard and Mouse Signals KB/MS Function Module The standard STX interface supports AT- and PS/2- type keyboard and PS/2-type pointing devices (mouse, touchpad etc.). The following diagram shows the proper design layout of all circuitry when defining the keyboard and mouse function module. Page 34 of 84

41 Figure 2-12 Keyboard and Mouse Function Module Schematic Page 35 of 84

42 2.4.9 USB 1&2 STX Interface supports two USB ports. Both USB ports have over-current detection so they can signal to the application software that over-current condition appeared on the particular USB port. Signal Pin Type Description USB1_N J2/161 USB1_P J2/163 USB1_OC# J2/173 USB2_N J2/167 USB2_P J2/169 USB2_OC# J2/175 B Universal Serial Bus Port signal pair comprises the differential data signals (positive and negative) for USB port. Required 15 K pull-down resistors have to be implemented on the STX Baseboard even if USB port is not used. J2/173 I-U Over current Detect is used to monitor the status of the USB power supply lines. B Universal Serial Bus Port signal pair comprises the differential data signals (positive and negative) for USB port. Required 15 K pull-down resistors have to be implemented on the STX Baseboard even if USB port is not used. J2/175 I-U Over current Detect is used to monitor the status of the USB power supply lines. Table 2-17 Universal Serial Bus 1 Interface Signals USB 1&2 Function Module STX interface supports two USB ports. AXIOMTEK STX module, however, can support four USB ports. The following diagram shows the proper design layout of all circuitry when defining the USB 1&2 function module. Page 36 of 84

43 Figure 2-13 USB 1&2 Function Module Schematic Page 37 of 84

44 USB 3&4 Signal Pin Type Description USB 3_N J2/107 B-D Universal Serial Bus Port signal pair comprises the differential data signals USB 3_P J2/109 (positive and negative) for USB port. Required 15 K pull-down resistors have to be implemented on the STX Baseboard even if USB port is not used. USB 4_N J2/113 USB 4_P J2/111 B-D Table 2-18 Universal Serial Bus 3&4 Interface Signals USB 3&4 Function Module Universal Serial Bus Port signal pair comprises the differential data signals (positive and negative) for USB port. Required 15 K pull-down resistors have to be implemented on the STX Baseboard even if USB port is not used. Figure 2-14 USB 3&4 Function Module Schematic Page 38 of 84

45 ETH STX Interface supports standard 10/100Mbit Ethernet interface. Note that net isolation transformer is not present on STX Module. Signal Pin Type Description NET_ J1/12 DC Network Ground should be used for termination circuitry and for the transformer center tap bypassing. NET_RX_N J1/10 NET_RX_P J1/8 NET_TX_N J1/4 NET_TX_P J1/2 I O-A Receive Data is analog twisted pair Ethernet differential input pair (positive and negative) that can be configured to accept either 100BASE-TX or 10BASE-T signaling. These signals interface directly that an isolation transformer. Transmit Data is analog twisted pair Ethernet differential pair (positive and negative) which is configurable to either 10BASE-T or 100BASE-TX signaling. These signals interface directly with an isolation transformer. NET_TX_CT J1/6 DC TX Center Tap pin should be connected to TX center tap of isolation transformer. Table 2-19 Ethernet 10/100Mbit Interface Signals ETH Function Module STX interface supports standard 10/100Mbit Ethernet interface. Note that net isolation transformer is not present on STX Module. The following diagram shows the proper design layout of all circuitry when defining the ETH function module. Page 39 of 84

46 Note1: These components are option for signal terminator. If use Axiomtek STX module doesn t place these component. Note2: The capacitor is option base on the transformer. Figure 2-15 ETH Function Module Schematic Page 40 of 84

47 AC 97 STX Interface features AC 97 interface to connect to the AC 97-compatible codec on STX Baseboard. See particular STX Module datasheet for list of the supported AC 97 codes. Signal Pin Type Description AC97_RST# J1/20 O-TP Reset initializes all AC 97 logic (including registers) to its default state. BIT_CLK J1/24 I-U Serial Bit Clock is MHz serial data clock providing clocking granularity. SDATA_IN J1/22 I-U Serial Data In transfers the time division multiplexed AC 97 output stream. SDATA_OUT J1/26 O-TP Serial Data Out transfers the time division multiplexed AC 97 input stream. SYNC J1/28 O-TP Synchronization is 48 khz fixed rate sample synchronization signal. Table 2-20 Audio Codec 97 Interface Signals AC 97 Function Module STX Interface features AC 97 interface to connect to an AC 97 compatible codec onto the STX Baseboard. AC 97 An AC 97 Controller is in the Southbridge of the STX module. AC-link is a digital serial link between the AC 97 Controller and AC 97 devices. For more details, refer to the AC 97 Component Specification Revision 2.1. Audio Codec Design The reference Design of VT1612A Audio Codec is available at The following diagram shows the proper design layout of all circuitry when defining the AX 97 function module. Page 41 of 84

48 Figure 2-16 AC 97 Function Module Schematic Page 42 of 84

49 CRT STX Interface support standard CRT interface for connecting CRT monitors or analog flat panels. Signal Pin Type Description CRT_B J2/191 O-A Analog DAC Blue drives the blue signal of the CRT monitor. CRT_G J2/183 O-A Analog DAC Green drives the green signal of the CRT monitor. CRT_ J2/185 J2/189 DC CRT Ground is analog ground dedicated to the RGB analog signals on CRT monitors. CRT_HS J2/199 O-TP Horizontal Sync provides the horizontal synchronization pulses for the CRTmonitor. CRT_R J2/187 O-A Analog DAC Red drives the red signal of the CRT monitor. CRT_VS J2/195 O-TP Vertical Sync provides the vertical synchronization pulses for the CRT monitor. DDC_SCL J2/177 O-OD-U DDC Clock transfers the DDC clock between the graphics controller and the CRT monitor using the VESA DDC protocol. DDC_SDA J2/179 B-OD-U DDC Data transfers the DDC data between the graphics controller and the CRT monitor using the VESA DDC protocol. Table 2-21 CRT Interface Signals CRT Function Module STX Inter face supports standard CRT interface for connecting CRT monitors or analog flat panels. Analog R,G, and B traces should be designed to be as short as possible. The RGB output is current source and therefore require 75 ohm load resistor from each rgb line to CRT_ to create the output voltage (approximately 0 to 0.7 volts). The trace of CRT_ surrounding the RGB lines and their RLC components should be at lease 15 mil wide and spaced away from outside signal as much as possible. The connection between CRT_ and digital ground should be a ferrite bead. The following diagram shows the proper design layout of all circuitry when defining the CRT function module. Page 43 of 84

50 Figure 2-17 CRT Function Module Schematic Page 44 of 84

51 FPI & TV-Out Flat Panel Interface directly supports TTL-level flat panels and converters from TTL to other interfaces (LVDS, Panel Link etc.). Signal Pin Type Description FP_BKL_EN J1/156 O-TP Back Light Enable controls the flat panel back light converter power. FP_BSEL J1/165 O-TP Bus Select indicates used data bus type (24-bit mode when high, 12-bit mode when low) FP_CLK_P J1/164 O-TP Clock Primary is used to latch the pixel data in both 24-bit and 12-bit mode. FP_CLK_S J1/168 O-TP Clock Secondary is used to latch of the high half pixel in 12-bit mode when dual edge clocking is turned off. In all other modes this signal is unused and driven low. FP_D0 J1/171 FP_D1 J1/173 FP_D2 J1/175 FP_D3 J1/177 FP_D4 J1/181 FP_D5 J1/183 FP_D6 J1/185 FP_D7 J1/187 FP_D8 J1/191 FP_D9 J1/193 FP_D10 J1/195 FP_D11 J1/197 FP_D12 J1/172 FP_D13 J1/174 FP_D14 J1/178 FP_D15 J1/180 FP_D16 J1/182 FP_D17 J1/184 FP_D18 J1/188 FP_D19 J1/190 FP_D20 J1/192 FP_D21 J1/194 FP_D22 J1/198 FP_D23 J1/200 O-TP Flat Panel Data transfers the flat panel pixel data. FP_D[23..12] is used for top half of 24-bit pixel data in 24-bit mode, and it is driven low in 12-bit mode. FP_D[11..00] is used for bottom half of 24-bit pixel data in 24-bit mode, and contains multiplexed low and high half of pixel data in 12-bit mode. FP_DE J1/167 O-TP Data Enable signal is high when pixel data is valid for the flat panel and low otherwise. Page 45 of 84

52 FP_DSEL J1/161 O-TP Dual Edge Clock Select indicates usage of secondary clock FP_CLK_S to latch pixel data. In 12-bit mode is FP_CLK_P used to latch data on both falling and rising edges when FP_DSEL is high, while FP_CLK_P latches low half data and FP_CLK_S latches high half data when FP_DSEL is low. In 24-bit mode is always driven low. FP_EDGE J1/158 O-TP Edge Type Select determines the clock edge that will latch the data. In single edge mode (FP_DSEL is low) the falling edge of the clock is used when FP_EDGE is low and the rising one is used when FP_EDGE is high. In dual edge mode (FP_DSEL is high) the primary edge (first latch edge after FP_DE is asserted) is the falling edge when FP_EDGE is low and the primary edge is the rising one when FP_EDGE is high. FP_HSYNC J1/160 O-TP Horizontal Sync provides the horizontal synchronization pulses for the flat panel. FP_VDD_EN J1/163 O-TP Flat Panel VDD Enable controls the flat panel digital power. FP_VSYNC J1/159 O-TP Vertical Sync provides the vertical synchronization pulses for the flat panel. FP_SCL J1/149 O-OD-U Flat Panel DDC Clock transfers the DDC clock between the graphics controller and the flat panel monitor using the VESA DDC protocol. FP_SDA J1/150 B-OD-U Flat Panel DDC Data transfers the DDC data between the graphics controller and the flat panel monitor using the VESA DDC protocol. Table 2-22 Flat Panel Interface Signals Signal Pin Type Description ZVD0 FC2/3 I-TP Video RGB data from video encoder. ZVD1 FC2/4 I-TP ZVD2 FC2/5 I-TP ZVD3 FC2/6 I-TP ZVD4 FC2/7 I-TP ZVD5 FC2/8 I-TP ZVD6 FC2/9 I-TP ZVD7 FC2/10 I-TP ZVD8 FC2/13 I-TP ZVD9 FC2/14 I-TP ZVD10 FC2/15 I-TP ZVD11 FC2/16 I-TP Continued..... Signal Pin Type Description ZVD12 FC2/17 I-TP Page 46 of 84

53 ZVD13 ZVD14 ZVD15 ZVREF ZVS ZVCLK FPD24(TVD6) FPD25(TVD4) FPD26(TVD5) FPD27(TVD7) FPD28(TVD0) FPD29(TVD1) FPD30(TVD3) FPD31(TVVS) FPD32(TVCLK) FPD33(TVD2) FPD34(TVHS) FPD35 FC2/18 FC2/19 FC2/20 I-TP I-TP I-TP FC2/23 I-TP VSYNC input from video decoder FC2/24 I-TP HSYNC input from video decoder FC2/25 I-TP Pixel Clock FC2/27 FC2/28 FC2/29 O-TP O-TP O-TP FC2/30 O-TP FC2/31 FC2/32 FC2/34 O-TP O-TP O-TP Table 2-23 FC2 Connector Pinout Multifunction Pin: 1. Panel Data for 36 Bit TFT LCD. Internally pulled down during reset. 8 ma is the default. 16mA is selected. 2. TV data RGBdata is output at one pixel/clock. Internally pulled down during reset. FC2/35 O-TP Multifunction Pin: 1. Panel Data for 36 Bit tft LCD. Internally pulled down during reset. 8 ma is the default. 16mA is selected 2. TV VSYNC. Internally pulled down during reset. FC2/36 O-TP Multifunction Pin: 1. Panel Data for 36 Bit TFT LCD. Internally pulled down during reset. 8 ma is the default. 16mA is selected 2. TV clock. Output clock to TV encoder. Internally pulled down during reset. FC2/37 O-TP Multifunction Pin: 1. Panel Data for 36 Bit TFT LCD. Internally pulled down during reset. 8 ma is the default. 16mA is selected. 2. TV data RGB data is output at one pixel/clock. Internally pulled down during reset. FC2/38 O-TP Multifunction Pin: 1. Panel Data for 36 bit TFT LCD. Internally pulled down during reset. 8 ma is the default. 16mA is selected 2. TV HSYNC. Output clock to TV encoder. Internally pulled down during reset. FC2/39 O-TP Panel Data for 36 bit TFT LCD. Internally pulled down during reset. 8 ma is the default. 16mA is selected Page 47 of 84

54 FPI & TV-Out Function Module Flat Panel Interface directly supports TTL-Level flat panels and converters from TTL to other interfaces (LVDS, Panel Link etc.) AXIOMTEK STX module increased the FC2 connector features to provide TV-out and panel interface upgrade capabilities into 36 bits. The following diagram shows the proper design layout of all circuitry when defining the FPI function module. Figure 2-18 FPI Function Module Schematic TV-Out Function Module You may visit to for related details on CH7006. The following diagram shows the proper design layout of all circuitry when defining the TC-Out function module. Page 48 of 84

55 Figure 2-19 TV-Out Function Module Schematic Page 49 of 84

56 FEAT Feature signals provide standard functionality of common motherboard's feature connector (signaling LEDs, keylock, reset and power buttons etc.). Signal Pin Type Description ACT_LED# J1/3 O-TP Ethernet TX/RX Activity is driven low to indicate active transmission or reception, and can be used to drive a LED. The activity event is stretched to a minimum duration to be always visible. DSK_LED# J1/7 O-OD STX Module On-board Disk Activity is driven low to indicate that an on-board disk is active. It does not indicate activity on STX E-IDE interface; however external disk activity signal can be wired-or with DSK_LED# if needed. KBD_LOCK# J1/11 I-U Keyboard Lock inhibits keyboard interface. LNK_LED# J1/5 O-TP Ethernet 10/100Mbit/s Link is driven low to indicate Good Link status for 10 Mbit/s or 100 Mbit/s operation and can be used to drive a LED. PWR_BTN# J1/15 I-U Power Button input signal is used by power management logic to monitor external system events, typically a front panel on/off button. RST_BTN# J1/13 I-U Reset Button input signal is used as an external reset signal from front panel button or external system supervisor. SPEAKER J1/9 O-TP Speaker output signal drives an external speaker device. Table 2-24 Feature Signals FEAT Function Module Feature signals provide standard functionality of common motherboard s feature connector. ACT_LED# Ethernet TX/RX Activity is driven low to indicate active transmission or reception, and can be used to drive a LED. LNK_LED# Ethernet 10/100Mbit/s Link is driven low to indicate Good Link status for 10 Mbit/s or 100Mbit/s operation and can be used to drive a LED. DSK_LED# It does not indicate activity on STX E-IDE interface, however external disk activity signal can be wired-or with DSK_LED# if needed. SPEAKER Speaker out signal drives an external speaker device or buzzer. KBD_LOCK# Keyboard Lock inhibits keyboard interface. Axiomtek STX module can t support this function. Page 50 of 84

57 RST_BTN# Reset Button input signal is used as an external reset signal from front panel button or external system supervisor. PWR_BTN# Power Button input signal is used by power management logic to monitor external system events, typically a front on/off button MISC Miscellaneous signals are most commonly used for hardware monitoring and system and power management. Signal Pin Type Description CPU_TD_N J1/37 O-A CPU Thermal Diode may be used to monitor the die temperature of the CPU for CPU_TD_P J1/35 thermal management purposes. CPU_TD_P is connected to diode anode (P junction) and CPU_TD_N is connected to diode cathode (N junction). EXT_SMI# J1/31 I-U External SMI Interrupt can be asserted by external logic to enter System Management Mode (SMM). I2C_SCL J1/32 O-OD-U I2C Clock transfers the clock between the I2C controller and the external device using the I2C protocol. I2C_SDA J1/34 B-OD-U I2C Data transfers the data between the I2C controller and the external device using the I2C protocol. PS_ON# J1/18 O-OD Power Supply On turns on all the main power rails when active. Typically it is used for ATX power supply control. V_CORE J1/42 O-A CPU Core Voltage can be monitored by the external HW monitor or system supervisor. WUE J1/17 I-U Wake-Up Event indicates that external wake-up event has occurred. This may cause the chipset to turn the power supply on, or to exit its current sleep state. The exact behavior (edge, level or pulse-train detection) can be programmed by software. Table 2-25 Miscellaneous Signals Page 51 of 84

58 JTAG JTAG interface is used for manufacturing purposes. Input voltages are defined by pull-up/down resistors on the STX Module and should be left unconnected on the STX Baseboard JTAG Design Notes JTAG interface is used for manufacturing purposes only. AXIOMTEK STX module does not support this function PWR Power pins provide required power supply to the STX Module as well as AC return path for signals. Therefore, all the power pins have to be connected. Signal Type Description DC Digital ground V_BAT V_SB VCC VCC3 DC DC DC DC Backup battery cell voltage (typically 3V) for maintaining RTC and CMOS functionality during the absence of power. +5V standby voltage for suspend and wake-up logic. Shall be left unconnected if not used. +5V power supply +3.3V power supply Table 2-26 Power and Ground Pins VCC & VCC3 STX Module requires both 5V & 3.3V power supply. The maximum current for VCC & VCC3 is 3.5A on any STX Module. V_SB STX Module requires 5V for standby power. Typically it connects to ATX power. Page 52 of 84

59 Battery STX Module needs a battery to maintain operation of the Real-Time-Clock in power off state. The designer should choose a battery voltage between 2.2V~3.6V.Axiomtek used the Panasonic CR-2030 battery on the STX Baseboard Reserved Pins marked as RSVD are reserved for future use and must be left unconnected. 2.5 Pin Definitions In this section are described all used signals, their positions on STX Interface and their group classification P1/J1 Connector Pin out The following table shows pins arrangement of either P1 plug (used on STX Module) or J1 receptacle (used on STX Baseboard). Pin Name Group Pin Name Group 1 PWR 2 NET_TX_P ETH 3 ACT_LED# FEAT 4 NET_TX_N ETH 5 LNK_LED# FEAT 6 NET_TX_CT ETH 7 DSK_LED# FEAT 8 NET_RX_P ETH 9 SPEAKER FEAT 10 NET_RX_N ETH 11 KBD_LOCK# FEAT 12 NET_ ETH 13 RST_BTN# FEAT 14 V_SB PWR 15 PWR_BTN# FEAT 16 V_SB PWR 17 WUE MISC 18 PS_ON# MISC 19 PWR 20 AC97_RST# AC KBCLK KB/MS 22 SDATA_IN AC KBDATA KB/MS 24 BIT_CLK AC MSCLK KB/MS 26 SDATA_OUT AC MSDATA KB/MS 28 SYNC AC VCC PWR 30 PWR 31 EXT_SMI# MISC 32 I2C_SCL MISC 33 EXT_BIOS# MISC 34 I2C_SDA MISC 35 CPU_TD_P MISC 36 PWR 37 CPU_TD_N MISC 38 IR_RX IrDA 39 V_BAT PWR 40 IR_TX IrDA Continued..... Page 53 of 84

60 Pin Name Group Pin Name Group 41 VCC PWR 42 V_CORE MISC 43 AD0 PCI 44 VCC PWR 45 AD1 PCI 46 VCC PWR 47 VCC PWR 48 AD2 PCI 49 AD4 PCI 50 AD5 PCI 51 AD3 PCI 52 PWR 53 PWR 54 C/BE0# PCI 55 AD6 PCI 56 AD7 PCI 57 AD8 PCI 58 PWR 59 PWR 60 AD9 PCI 61 AD10 PCI 62 AD11 PCI 63 VCC3 PWR 64 VCC3 PWR 65 RSVD 66 AD14 PCI 67 AD12 PCI 68 AD13 PCI 69 AD15 PCI 70 VCC3 PWR 71 VCC3 PWR 72 C/BE1# PCI 73 VCC3 PWR 74 SERR# PCI 75 PAR PCI 76 PWR 77 PWR 78 PWR 79 PWR 80 PERR# PCI 81 LOCK# PCI 82 STOP# PCI 83 VCC3 PWR 84 VCC3 PWR 85 VCC3 PWR 86 VCC3 PWR 87 DEVSEL# PCI 88 TRDY# PCI 89 IRDY# PCI 90 FRAME# PCI 91 PWR 92 PWR 93 PWR 94 PWR 95 C/BE2# PCI 96 AD16 PCI 97 AD17 PCI 98 AD18 PCI 99 VCC3 PWR 100 VCC3 PWR 101 VCC3 PWR 102 AD21 PCI 103 AD19 PCI 104 AD20 PCI 105 AD22 PCI 106 VCC3 PWR 107 TRST# JTAG 108 AD23 PCI Continued..... Page 54 of 84

61 Pin Name Group Pin Name Group 109 TCK JTAG 110 RSVD 111 TDI JTAG 112 PWR 113 TMS JTAG 114 AD24 PCI 115 TDO JTAG 116 C/BE3# PCI 117 AD25 PCI 118 PWR 119 PWR 120 AD26 PCI 121 AD28 PCI 122 AD29 PCI 123 AD27 PCI 124 VCC3 PWR 125 VCC3 PWR 126 VCC3 PWR 127 AD31 PCI 128 REQ1# PCI 129 AD30 PCI 130 REQ0# PCI 131 VCC PWR 132 VCC PWR 133 VCC PWR 134 VCC PWR 135 GNT0# PCI 136 GNT2# PCI 137 REQ2# PCI 138 GNT1# PCI 139 PWR 140 PWR 141 CLK1 PCI 142 PWR 143 PWR 144 CLK2 PCI 145 CLK0 PCI 146 VCC PWR 147 VCC PWR 148 RSVD 149 FP_SCL FPI 150 FP_SDA FPI 151 RST# PCI 152 INTD# PCI 153 INTC# PCI 154 INTA# PCI 155 INTB# PCI 156 FP_BKL_EN FPI 157 PWR 158 FP_EDGE FPI 159 FP_VSYNC FPI 160 FP_HSYNC FPI 161 FP_DSEL FPI 162 PWR 163 FP_VDD_EN FPI 164 FP_CLK_P FPI 165 FP_BSEL FPI 166 PWR 167 FP_DE FPI 168 FP_CLK_S FPI 169 VCC PWR 170 VCC PWR 171 FP_D0 FPI 172 FP_D12 FPI 173 FP_D1 FPI 174 FP_D13 FPI 175 FP_D2 FPI 176 PWR Continued..... Page 55 of 84

62 Pin Name Group Pin Name Group 177 FP_D3 FPI 178 FP_D14 FPI 179 PWR 180 FP_D15 FPI 181 FP_D4 FPI 182 FP_D16 FPI 183 FP_D5 FPI 184 FP_D17 FPI 185 FP_D6 FPI 186 PWR 187 FP_D7 FPI 188 FP_D18 FPI 189 PWR 190 FP_D19 FPI 191 FP_D8 FPI 192 FP_D20 FPI 193 FP_D9 FPI 194 FP_D21 FPI 195 FP_D10 FPI 196 PWR 197 FP_D11 FPI 198 FP_D22 FPI 199 PWR 200 FP_D23 FPI Table 2-27 STX P1 / J1 Connector Pin out P2/J2 Connector Pin out The following table shows pins arrangement of either P2 plug (used on STX Module) or J2 receptacle (used on STX Baseboard). Pin Signal Name Group Pin Signal Name Group 1 RESET# E-IDE 2 PWR 3 DD7 E-IDE 4 IOCHCHK# ISA 5 DD8 E-IDE 6 SD7 ISA 7 DD6 E-IDE 8 RESETDRV ISA 9 DD9 E-IDE 10 SD6 ISA 11 DD5 E-IDE 12 VCC PWR 13 DD10 E-IDE 14 SD5 ISA 15 DD4 E-IDE 16 IRQ9 ISA 17 DD11 E-IDE 18 SD4 ISA 19 DD3 E-IDE 20 PWR 21 DD12 E-IDE 22 SD3 ISA 23 DD2 E-IDE 24 DRQ2 ISA 25 DD13 E-IDE 26 SD2 ISA 27 DD1 E-IDE 28 VCC PWR 29 DD14 E-IDE 30 SD1 ISA 31 DD0 E-IDE 32 ENDXFR# ISA Continued..... Page 56 of 84

63 Pin Signal Name Group Pin Signal Name Group 33 DD15 E-IDE 34 SD0 ISA 35 INTRQ E-IDE 36 RSVD 37 DMARQ E-IDE 38 RSVD 39 DIOW# E-IDE 40 RSVD 41 DIOR# E-IDE 42 IOCHRDY ISA 43 IORDY E-IDE 44 PWR 45 DMACK# E-IDE 46 MEMCS16# ISA DA1 E-IDE 48 SBHE# ISA DA0 E-IDE 50 AEN ISA 51 DA2 E-IDE 52 SMEMW# ISA 53 CS0# E-IDE 54 IOCS16# ISA CS1# E-IDE 56 LA23 ISA PWR 58 SA19 ISA 59 DENSEL FDD 60 SMEMR# ISA 61 INDEX# FDD 62 IRQ10 ISA MTR0# FDD 64 LA22 ISA DR1# FDD 66 SA18 ISA 67 DR0# FDD 68 IOW# ISA 69 MTR1# FDD 70 IRQ11 ISA DIR# FDD 72 LA21 ISA STEP# FDD 74 SA17 ISA 75 WDATA# FDD 76 IOR# ISA 77 WGATE# FDD 78 IRQ12 ISA TRK0# FDD 80 LA20 ISA WP# FDD 82 SA16 ISA 83 RDATA# FDD 84 DACK3# ISA 85 HDSEL# FDD 86 IRQ15 ISA DSKCHG# FDD 88 LA19 ISA PWR 90 SA15 ISA 91 STB# PPI 92 DRQ3 ISA 93 AFD# PPI 94 IRQ14 ISA PD0 PPI 96 LA18 ISA ERR# PPI 98 SA14 ISA 99 PD1 PPI 100 DACK1# ISA Continued..... Page 57 of 84

64 Pin Signal Name Group Pin Signal Name Group 101 INIT# PPI 102 LA17 ISA PD2 PPI 104 DACK0# ISA SLIN# PPI 106 DRQ1 ISA 107 PD3 PPI 108 SA13 ISA 109 PD4 PPI 110 MEMR# ISA PD5 PPI 112 DRQ0 ISA PD6 PPI 114 REFRESH# ISA 115 PD7 PPI 116 SA12 ISA 117 ACK# PPI 118 MEMW# ISA BUSY PPI 120 DACK5# ISA PE PPI 122 SYSCLK ISA 123 SLCT PPI 124 SA11 ISA 125 PWR 126 SD8 ISA DCD1# SPI1 128 DRQ5 ISA SIN1 SPI1 130 IRQ7 ISA 131 SOUT1 SPI1 132 SA10 ISA 133 DTR1# SPI1 134 SD9 ISA DSR1# SPI1 136 DACK6# ISA RTS1# SPI1 138 IRQ6 ISA 139 CTS1# SPI1 140 SA9 ISA 141 RI1# SPI1 142 SD10 ISA DCD2# SPI2 144 DRQ6 ISA SIN2 SPI2 146 IRQ5 ISA 147 SOUT2 SPI2 148 SA8 ISA 149 DTR2# SPI2 150 SD11 ISA DSR2# SPI2 152 DACK7# ISA RTS2# SPI2 154 IRQ4 ISA 155 CTS2# SPI2 156 SA7 ISA 157 RI2# SPI2 158 SD12 ISA PWR 160 DRQ7 ISA USB 1/ 2_N USB 1/ IRQ3 ISA 163 USB 1/ 2_P USB 1/ SA6 ISA 165 PWR 166 SD13 ISA USB 3/4_N USB 3/4 168 VCC PWR Continued..... Page 58 of 84

65 Pin Signal Name Group Pin Signal Name Group 169 USB 3/4_P USB 3/4 170 DACK2# ISA 171 PWR 172 SA5 ISA 173 USB 1/ 2_OC# USB 1/ SD14 ISA USB 3/4_OC# USB 3/4 176 MASTER# ISA DDC_SCL CRT 178 TC ISA 179 DDC_SDA CRT 180 SA4 ISA 181 PWR 182 SD15 ISA CRT_G CRT 184 RSVD 185 CRT_ CRT 186 BALE ISA 187 CRT_R CRT 188 SA3 ISA 189 CRT_ CRT 190 VCC PWR 191 CRT_B CRT 192 SA2 ISA 193 PWR 194 OSC ISA 195 CRT_VS CRT 196 SA1 ISA 197 PWR 198 SA0 ISA 199 CRT_HS CRT 200 PWR Table 2-28 STX P2/J2 Connector Pin out FC2 ZV from STX Module The ZV-Port, or Zoomed Video Port, allows direct transmission of video data from a STX module to STB Base board. This connector also includes EX_LCD signal and TV signal from STX module. FC2 connector is a 41 Pin 0.5m/m Pitch FPC/FFC-CONN ZIF 90D SMT type connector that provides interfaces for the following functions. Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal FPD28(TVD0) 41 NC FPD29(TVD1) 3 ZVD0 13 ZVD8 23 ZVREF 33 4 ZVD1 14 ZVD9 24 ZVS 34 FPD30(TVD7) 5 ZVD2 15 ZVD10 25 ZVCLK 35 FPD31(TVVS) 6 ZVD3 16 ZVD FPD32(TVCLK) 7 ZVD4 17 ZVD12 27 FPD24(TVD6) 37 FPD33(TVD2) 8 ZVD5 18 ZVD13 28 FPD25(TVD4) 38 FPD34(TVHS) 9 ZVD6 19 ZVD14 29 FPD26(TVD5) 39 FPD35 10 ZVD7 20 ZVD15 30 FPD27(TVD7) 40 NC Table 2-29 FC2 Connector Pin out Page 59 of 84

66 2.5.4 FC1 IDE2 from STX Module FC1 connector is a 41 Pin 0.5m/m Pitch FPC/FFC-CONN ZIF 90D SMT type connector that provides interfaces for the following functions. Pin # Signal Name Pin # Signal Name 1 22 SDD0 2 BRSTDRV- 23 SDD SDD SDD8 26 SSDDREQ 6 SDD6 27 SSDIOW- 7 SDD9 28 SSDIOR SSDIORDY 9 SDD5 30 SSDDACK- 10 SDD SDD4 32 IRQ15 12 SDD11 33 SDA SD SDD3 36 SDA0 16 SDD12 37 SDA2 17 SDD2 38 SCS1-18 SDD13 39 SCS N.C. 20 SDD SDD14 Table 2-30 FC1 Connector Pin out Page 60 of 84

67 C h a p t e r 3 Electrical Characteristics This chapter provides a detailed description of STX Interface signals. The signals are arranged in functional groups according to their associated interface. All signals are described from STX Module point of view for example, input means direction from the STX Baseboard to the STX Module. 3.1 Flat Panel Interface Axiomtek STX Interface supports all modes of digital flat panel interface. It allows using the different types of graphics controllers on the STX Module. STX flat panel interface is compatible with the Silicon Image's SiI154 and SiI164 Panel Link transmitters that can be used to drive the flat panels with TMDS interface. Flat panel interface mode in use is indicated by BIOS setting. The pixel data mapping is described in the following table. Flat Panel Data Signal 24-bit Mode (Pixel Data) 12-bit Mode (Low/High Half of Pixel Data) Flat Panel Data Signal 24-bit Mode (Pixel Data) 12-bit Mode (Low/High Half of Pixel Data) FP_D23 R7 FP_D11 G3 G3/R7 FP_D22 R6 FP_D10 G2 G2/R6 FP_D21 R5 FP_D9 G1 G1/R5 FP_D20 R4 FP_D8 G0 G0/R4 FP_D19 R3 FP_D7 B7 B7/R3 FP_D18 R2 FP_D6 B6 B6/R2 FP_D17 R1 FP_D5 B5 B5/R1 FP_D16 R0 FP_D4 B4 B4/R0 FP_D15 G7 FP_D3 B3 B3/G7 FP_D14 G6 FP_D2 B2 B2/G6 FP_D13 G5 FP_D1 B1 B1/G5 FP_D12 G4 FP_D0 B0 B0/G4 Table 3-1 Flat Panel Pixel Data Mapping R, G, B denotes red, green, and blue color pixel components. Bit significance within a color is defined by number (7 denotes MSB). When modes with color depth less than 8 bit are used, LSB pixel bits are driven low. Page 56 of 96 AXIOMTEK reserves the right to make improvements to this document and/or product at any time and without notice. STXVEA STX Module Data book Version 1.0, March 2003 :

68 The FP_DSEL signal defines single or dual clock mode used in 12-bit mode. The FP_EDGE selects an active edge of the clock signal. See following tables for definition of the clock edge used for pixel data sampling in different modes. DSTN TFT Pin 16-bit 24-bit 18-bit 24-bit LP LP LP HSYNC HSYNC FLM FP FP VSYNC VSYNC SHFCLK XCK XCK CK CK M DE DE ENAVDD ENAVDD ENAVDD ENAVDD ENAVDD ENABLK ENABLK ENABLK ENABLK ENABLK P23 UR0 UR0 R5 R7 P22 UR1 UR1 R4 R6 P21 UR2 UR2 R3 R5 P20 UR3 R2 R4 P19 LR0 LR0 R1 R3 P18 LR1 LR1 R0 R2 P17 LR2 LR2 R1 P16 LR3 R0 P15 UG0 UG0 G5 G7 P14 UG1 UG1 G4 G6 P13 UG2 UG2 G3 G5 P12 UG3 G2 G4 P11 LG0 LG0 G1 G3 P10 LG1 LG1 G0 G2 P9 LG2 LG2 G1 P8 LG3 G0 P7 UB0 UB0 B5 B7 P6 UB1 UB1 B4 B6 P5 UB2 B3 B5 P4 UB3 B2 B4 P3 LB0 LB0 B1 B3 P2 LB1 LB1 B0 B2 P1 LB2 B1 P0 LB3 B0 Table 3-2 DSTN and TFT Flat Panel Pixel Data Mapping Page 57 of 84

69 Pin Name TFT2X9 TFT2X12 TFT2X18 LP LP LP HSYNC FLM FP FP VSYNC SHFCLK XCK XCK CK M DE ENAVDD ENAVDD ENAVDD ENAVDD ENABLK ENABLK ENABLK ENABLK P35 B12 B13 B15 P34 B02 B03 B05 P33 B11 B12 B14 P32 B01 B02 B04 P31 B10 B11 B13 P30 B00 B01 B03 P29 B10 B12 P28 B00 B02 P27 B11 P26 B01 P25 B10 P24 B00 P23 G12 G13 G15 P22 G02 G03 G05 P21 G11 G12 G14 P20 G01 G02 G04 P19 G10 G11 G13 P18 G00 G01 G03 P17 G10 G12 P16 G00 G02 P15 G11 P14 G01 P13 G10 P12 G00 P11 R12 R13 R15 P10 R02 R03 R05 P9 R11 R12 R14 P8 R01 R02 R04 Continued..... Page 58 of 84

70 Table 3-3 Pin Name TFT2X9 TFT2X12 TFT2X18 P7 R10 R11 R13 P6 R00 R01 R03 P5 R10 R12 P4 R00 R02 P3 R11 P2 R01 P1 R10 P0 R00 TFT Flat Panel Pixel Data Mapping STN DSTN Pin 8-bit 16-bit 24-bit 8-bit LP LP LP HSYNC HSYNC FLM FP FP VSYNC VSYNC SHFCLK XCK XCK CK CK M DE DE DE DE ENAVDD ENAVDD ENAVDD ENAVDD ENAVDD ENABLK ENABLK ENABLK ENABLK ENABLK P0 R0 R0 R0 LR0 P1 G0 G0 G0 P2 B0 B0 B0 LG0 P3 R1 R1 R1 P4 G1 G1 G1 LB0 P5 B1 B1 B1 P6 R2 R2 R2 LR1 P7 G2 G2 G2 P8 B2 B2 P9 R3 R3 P10 G3 G3 P11 B3 B3 P12 R4 R4 P13 G4 G4 P14 B4 B4 P15 R5 R5 P!6 G5 P17 B5 Continued..... Page 59 of 84

71 STN DSTN Pin 8-bit 16-bit 24-bit 8-bit P18 R6 UR0 P19 G6 P20 B6 UG0 P21 R7 P22 G7 UB0 P23 B7 P24 UR1 DSTN TFT Pin 16-bit 24-bit 9-bit 2X9-bit LP LP LP HSYNC HSYNC FLM FP FP VSYNC VSYNC SHFCLK XCK XCK CK CK M DE DE DE DE ENAVDD ENAVDD ENAVDD ENAVDD ENAVDD ENABLK ENABLK ENABLK ENABLK ENABLK P0 LB3 P1 LB2 P2 LB1 LB1 P3 LB0 LB0 P4 UB3 P5 UB2 P6 UB1 UB1 R0 R00 P7 UB0 UB0 R10 P8 LG3 R1 R01 P9 LG2 LG2 R11 P10 LG1 LG1 R2 R02 P11 LG0 LG0 R12 P12 UG3 P13 UG2 UG2 P14 UG1 UG1 P15 UG0 UG0 P16 LR3 P17 LR2 LR2 P18 LR1 LR1 G0 G00 P19 LR0 LR0 G10 Continued..... Page 60 of 84

72 DSTN TFT Pin 16-bit 24-bit 9-bit 2X9-bit P20 UR3 G1 G01 P21 UR2 UR2 G11 P22 UR1 UR1 G2 G02 P23 UR0 UR0 G12 P30 B0 B00 P31 B10 P32 B1 B01 P33 B11 P34 B2 B02 P35 B12 TFT TFT Pin 12-bit 2X12-bit 15-bit 2X15-bit LP LP LP HSYNC HSYNC FLM FP FP VSYNC VSYNC SHFCLK XCK XCK CK CK M DE DE DE DE ENAVDD ENAVDD ENAVDD ENAVDD ENAVDD ENABLK ENABLK ENABLK ENABLK ENABLK P0 P1 P2 R0 R00 P3 R10 P4 R0 R00 R1 R01 P5 R10 R11 P6 R1 R01 R2 R02 P7 R11 R12 P8 R2 R02 R3 R03 P9 R12 R13 P10 R3 R03 R4 R04 P11 R13 R14 P12 P13 P14 G0 G00 P15 G10 P16 G0 G00 G1 G01 Continued..... Page 61 of 84

73 TFT TFT Pin 12-bit 2X12-bit 15-bit 2X15-bit P17 G10 G11 P18 G1 G01 G2 G02 P19 G11 G12 P20 G2 G02 G3 G03 P21 G12 G13 P22 G3 G03 G4 G04 P23 G13 G14 P24 P25 P26 B0 B00 P27 B10 P28 B0 B00 B1 B01 P29 B10 B11 P30 B1 B01 B2 B02 P31 B11 B12 P32 B2 B02 B3 B03 P33 B12 B13 P34 B3 B03 B4 B04 P35 B13 B14 TFT TFT Pin 18-bit 24-bit 2X18-bit LP LP LP HSYNC FLM FP FP VSYNC SHFCLK XCK XCK CK M DE DE DE ENAVDD ENAVDD ENAVDD ENAVDD ENABLK ENABLK ENABLK ENABLK P0 B0 R00 P1 B1 R10 P2 B0 B2 R01 P3 B1 B3 R11 P4 B2 B4 R02 P5 B3 B5 R12 P6 B4 B6 R03 P7 B5 B7 R13 Continued..... Page 62 of 84

74 TFT TFT Table 3-4 Pin 18-bit 24-bit 2X18-bit P8 G0 R04 P9 G1 R14 P10 G0 G2 R05 P11 G1 G3 R15 P12 G2 G4 G00 P13 G3 G5 G10 P14 G4 G6 G01 P15 G5 G7 G11 P16 R0 G02 P17 R1 G12 P18 R0 R2 G03 P19 R1 R3 G13 P20 R2 R4 G04 P21 R3 R5 G14 P22 R4 R6 G05 P23 R5 R7 G15 P24 B00 P25 B10 P26 B01 P27 B11 P28 B02 P29 B12 P30 B03 P31 B13 P32 B04 P33 B14 P34 B05 P35 B15 Flat Panel Interface Pins of Color DSTN and Color TFT LCD FP_DSEL FP_EDGE 24-bit Pixel Data 0 0 FP_CLK_P falling edge 0 1 FP_CLK_P rising edge Table 3-5 Sampling Edge in 24-bitMode (FP_BSEL=1) Page 63 of 84

75 Table 3-6 FP_DSEL FP_EDGE Low Half of Pixel Data High Half of Pixel Data 0 0 FP_CLK_P falling edge FP_CLK_S falling edge 0 1 FP_CLK_P rising edge FP_CLK_S rising edge 1 0 FP_CLK_P falling edge FP_CLK_P rising edge 1 1 FP_CLK_P rising edge FP_CLK_P falling edge Sampling Edge in 12-bitMode (FP_BSEL=0) 3.2 PCI Bus Interface STX interface supports up to three external PCI devices with bus master capability. Additionally the fourth PCI device without bus master support can be connected provided that clock signal is replicated Clock Distribution The STX Module provides clock signals for three external PCI devices or slots on the STX Baseboard. The maximum skew of 2 ns shall be maintained across the system operating at 33 MHz between any two PCI devices at the clock input of the integrated circuits. There are two components that contribute to clock skew in a STX system: STX Module clock skew STX Baseboard clock skew The STX Module clock distribution circuitry has to be designed to accommodate the STX Baseboard skew. The clock distribution circuitry provides a discrete clock signal to each of the STX connector pins defined as PCI clock (CLK[3..0]). The routing of these signals shall be matched in length. Any on-board STX device shall be provided a clock that is delayed to accommodate the maximum propagation delay of the Baseboard clocks and still meet the 2 ns overall skew requirement. Clock Signal Length Each external PCI device on STX Baseboard shall be provided a discrete clock signal. The clock signals on the STX Baseboard have to be designed with a delay of 800 ps between STX connector clock pins and PCI device clock input pins. As the typical trace velocity is in the range of ps/cm, the trace length of the clock signals should be cm. The fourth PCI device can be connected provided that clock signal is replicated. The zero-delay buffer based on PLL technology must be used in this case to maintain the overall maximum skew IDSEL Mapping To avoid possibility of contention between selecting PCI devices on the STX Baseboard and PCI devices on the STX Module, AD[23..20] lines are used to support IDSEL signals on the STX Baseboard devices as can be seen in Table 30 PCI Interrupt Routing on page 35. This mapping is compatible with PC-104+ specification. Page 64 of 84

76 Expansion connectors and devices connected directly to STX connectors are considered to be on bus Interrupt Routing To standardize the interrupt assignation in the system BIOS and OS, the interrupt binding scheme is defined in the following table. Used interrupt routing is compatible with PC-104+ specification. Table 3-7 IDSEL Mapping STX Interrupt Signal INTA# INTB# INTC# INTD# AD23 INTB INTC INTD INTA AD22 INTC INTD INTA INTB AD21 INTD INTA INTB INTC AD20 INTA INTB INTC INTD PCI Interrupt Routing For example: INTA# pin of device with IDSEL=AD21 has to be connected to INTB# signal on the STX Interface. Note Relation between PCI device number and IDSEL mapping depends on the used chipset and may differ on various STX Modules Signaling Voltage Level The STX Module can use 5V or 3.3V PCI signaling level. To allow design of universal STX Baseboard with PCI devices supporting the both signaling levels, the V_IO pin is defined on the STX Interface. This pin is connected to VCC when 5V signaling level is used and to VCC3 in 3.3V environment. V_IO can be used for PCI I/O buffer power supply and maximal current drawn from this pin must not exceed 250mA. There is no mechanical keying system defined for STX Module to specify whether the STX Module uses 5V or 3.3V signaling level. Note STX Module requires both 5V and 3.3V power supply irrespective of used PCI signaling level. 3.3 Electrical Power Requirements Table 3-8 Pin Name Pin Count Range Tolerance STX88600 Electrical Power Requirements Page 65 of 84 Max. Cur CPU400 CPU533 CPU667 CPU800 VCC V 5% 0.9A 1.8A 1.9A 3.2A VCC V 5% 2A 2A 2A 2A V_SB V 5% 0.8A 0.8A 0.8A 0.8A V_BAT V -10%;+20% 5uA 5Ua 5uA 5uA

77 Table 3-9 Pin Pin Max. Cur Range Tolerance Name Count CPU400 CPU650 CPU933 VCC V 5% 1.65A 2.5A 3A VCC V 5% 2.A 2A 2A V_SB V 5% 0.8A 0.8A 0.8A V_BAT V -10%;+20% 5uA 5Ua 5uA STX88601 Electrical Power Requirements Page 66 of 84

78 C h a p t e r 4 Mechanical Specifications The standard STX compliant hardware, defined by IBS Industrieelektronik Multimedia, must comply with the following mechanical specifications. Figure 4-1 STX Module Dimensions 4.1 STX Dimensions The STX defines its dimensions on the following illustrations. Figure 4-2 STX Module Dimensions Page 66 of 84

79 Figure 4-3 STX Module Layout NOTE: Fastening mechanism for STX Module consists of four mounting holes in PCB and four inner threads M3 5 mm. Figure 4-4 STX Height Dimensions Page 67 of 84

80 Figure 4-5 J1/J2 Connector Specifications Figure 4-6 FC1, FC2 Location of STX Baseboard Page 68 of 84