APPLICATION NOTE. AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I. Atmel AVR XMEGA. Introduction. Features

Transcription

1 APPLICATION NOTE AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I Atmel AVR XMEGA Introduction This application note lists out the differences and changes between Revision E and Revision I of Atmel ATxmega16D4/32D4 devices. For complete device details, always refer to the most recent version of the ATxmega16D4/32D4 datasheet and the Atmel XMEGA D manual. Errata differences are not listed in this document, only in the device datasheet. In addition to the differences described in this document, other typical characteristics could be different. Check the latest datasheets for details. The new configuration options and functions available in Revision I of ATxmega16D4/32D4 are a superset of existing functions, and this means that existing code for these revisions will work on the new revision without changing existing configuration or enabling new functions. Features Enhancements and added functions Memories System clock and clock options Reset system I/O ports Registers Changes in electrical characteristics

2 1 Enhancements and Added Functions In this chapter, we summarize the list of enhancements or added features available in the Revision I of the Atmel ATxmega16D4/32D Clock System Alternate pin location for TOSC1 and TOSC2 pins for kHz crystal connection on devices with shared TOSC and XTAL location A divide-by-two option for the PLL output that enables output frequency down to 10MHz PLL lock failure detection with optionally Non-Maskable Interrupt (NMI), for improved safety and robustness Non-prescaled Real Time Counter clock source options: External clock from TOSC1, kHz from TOSC, and the kHz from the kHz internal oscillator Higher drive option for external crystal oscillator to support crystals with higher load The 32MHz internal oscillator can be tuned to run at any frequency between 30MHz and 55MHz 1.2 I/O Ports Alternate pin locations for Timer/Counter 0 Compare Channels, USART0 and SPI Alternate pin locations for the Peripheral Clock and Event output functions The Real Time Counter clock can be output to a port pin Any Event Channel can be output to a port pin 1.3 Two-wire Interface The SDA Hold time can be increased and configured in order to be SMBUS compliant 1.4 Analog to Digital Converter Automatic input channel scan V CC /2 voltage reference option 1/2x (divide-by-two) gain stage setting Internal Ground can be used as negative input in differential mode with and without gain Sample time is configurable 1.5 Analog Comparator Analog Comparator 1 can be output on a port pin A constant current source 1.6 CRC16/CRC32 Generator A CRC16/CRC32 Generator Module that supports CRC16 (RC-CCITT) and CRC-32 (IEEE 802.3) bit Timer/Counter 0 Split mode that enable two 8-bit Timer/Counters with four PWM channels each 1.8 High Resolution Extension Hi-Res+ option to allow PWM resolution to be increased with 8x (3-bit) 1.9 Power Management Possibility to enable sequential start of the components used for analog modules ADC and Analog Comparator in order to reduce start-up current 2

3 2 Memories 2.1 NVM Controller For Atmel ATxmega16D4/32D4 Revision E devices, the chip erase time is about 40ms. The chip erase time of ATxmega32D4/16/D4 Revision I is longer. The typical chip erase time of ATxmega16D4/32D4 Revision I are listed in Table 2-1. Table 2-1. ATxmega16D4/32D4 Revision E Chip Erase Time Product Flash and Boot Code Size Chip Erase Time ATxmega16D4 16KB + 4KB 45ms ATxmega32D4 32KB + 4KB 50ms To ensure that the flash chip erase is finished correctly, no flash access should be done during the chip erase time. In the user code, it is always needed to check the FBUSY bit in the Non-Volatile Memory Status Register to see when the chip erase is finished. CRC32 is automatically used instead of existing CRC module if the new CRC16/CRC32 module is enabled. There is no change in the commands. 2.2 Fuses and Lock Bits BOD levels are different in ATxmega16D4/32D4 Revision I. See Section 4.1 Brown-out Detection for the differences. 3 System Clock and Clock Options 3.1 Clock Failure The PLLDFIF flag, indicating if the PLL looses lock, is no longer automatically cleared, but must be done from software. 3

4 4 Reset System 4.1 Brown-out Detection The programmable BODLEVEL settings are different in ATxmega16D4/32D4 Revision I. See Table 4-1 for details. Refer to the device datasheet regarding tolerance for the brown-out levels. Table 4-1. Brown-out Levels BODLEVEL VBOT Revision E VBOT Revision I V 1.6 V V 1.8 V V 2.0 V V 2.2 V V 2.4 V V 2.6 V V 2.8 V V 3.0 V For devices until Revision E, the BOD is forced on for all Non-Volatile Memory (NVM) programming. For the new Revision I, the BOD is only forced on during chip erase and when the PDI is enabled. For other NVM programming operations, the POR threshold voltage (V POT+) is the limit for aborting. 5 I/O Ports The I/O port pins are LV-TTL and LVCOMS compatible for Atmel ATxmega16D4/32D4 Revision I. The minimum Input High Voltage is never higher than 2.0V for V CC > 2.7V. In ATxmega16D4/32D4 Revision E, the minimum Input High Voltage is 0.7V CC, and could be higher than 2.0V for V CC > 2.86V. 5.1 I/O Pin Behavior when Disabling TX in USART When the transmitter is disabled in USART peripheral, it will no longer override the TxDn pin, and the pin direction is set as input automatically by hardware, even if it was configured as output by the user. This behavior as mentioned in the XMEGA D manual is valid from Revision I. In the previous revisions, the pin direction does not get changed to input automatically. 4

5 6 Registers 6.1 Added Registers and Bits Table 6-1 lists the registers and bits, which has been added in the ATxmega16D4/32D4 Revision I. Table 6-1. Register Bits and Functionality added in the ATxmega16D4/32D4 Revision I Register Name Bit Function SAMPCTRL Bit[5:0] - SAMPVAL[5:0] Sampling time control register The SAMPVAL bits control the ADC sampling time in number of half ADC prescaled clock cycles (depends on ADC_PRESCALER value), thus controlling the ADC input impedance. Sampling time is set according to the formula: Sampling time = (SAMPVAL+1)*(Clk ADC /2) 6.2 Removed Registers and Bits Table 6-2 lists the registers and bits, which exist in devices until Atmel ATxmega16D4/32D4 revision E but not in ATxmega16D4/32D4 Revision I. Table 6-2. Register Bits and Functionality that does not exist in ATxmega16D4/32D4 Revision I Register Name Bit Function COMP0 COMP[7:0] Oscillator Compare Register CALH Register Not Applicable For the ATxmega16D4/32D4 Revision I, CALH is not applicable hence it cannot be written. When read, the CALH register will return zero. This new design ATxmega16D4/32D4 ADC requires only one calibration byte (only 8 bit value not 12 bit value). For code compatibility with the earlier revisions, dependent registers like CALH, CALL, ADC CAL0, and ADC CAL1 has been kept same as the older design. 5

6 6.4 MUXNEG Configurations in ADC Channel MUX Control Register In the Revision E of the ATxmega16D4/32D4 devices, Bit 2 of the MUXNEG configuration in ADC Channel MUX Control registers is reserved. This bit is now available for configuration in the Revision I. Below are the configurations available in the older and latest revision: Revision E: Bit x01 - MUXPOS[3:0] - MUXNEG[1:0] MUXCTRL Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value Table 6-3. ADC MUXNEG Configuration, INPUTMODE[1:0] = 10, Differential without Gain MUXNEG[1:0] Group Configuration Analog Input 00 PIN0 ADC0 pin 01 PIN1 ADC1 pin 10 PIN2 ADC2 pin 11 PIN3 ADC3 pin Table 6-4. ADC MUXNEG Configuration, INPUTMODE[1:0] = 11, Differential with Gain MUXNEG[1:0] Group Configuration Analog Input 00 PIN4 ADC4 pin 01 PIN5 ADC5 pin 10 PIN6 ADC6 pin 11 PIN7 ADC7 pin 6

7 Revision I: Bit x01 - MUXPOS[3:0] MUXNEG[2:0] Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value Table 6-5. ADC MUXNEG Configuration, INPUTMODE[1:0] = 10, Differential without Gain MUXNEG[2:0] Group Configuration Analog Input 000 PIN0 ADC0 pin 001 PIN1 ADC1 pin 010 PIN2 ADC2 pin 011 PIN3 ADC3 pin Reserved 101 GND PAD ground Reserved 111 INTGND Internal ground Table 6-6. ADC MUXNEG Configuration, INPUTMODE[1:0] = 11, Differential with Gain MUXNEG[2:0] Group Configuration Analog Input 000 PIN4 ADC4 pin 001 PIN5 ADC5 pin 010 PIN6 ADC6 pin 011 PIN7 ADC7 pin 100 INTGND Initial ground Reserved Reserved 111 GND PAD ground 7

8 7 Changes in Electrical Characteristics 7.1 Reduced Current Consumption in Active and Idle Mode Table 7-1 lists the typical and maximum current consumption in the Revision E and Revision I. Table 7-1. Current Consumption in Sleep Modes Revision E Revision I Parameter Condition Min. Typ. Max. Min. Typ. Max. Units 32kHz, ext. clk. V CC = 1.8V µa V CC = 3.0V Active power consumption Idle power consumption 1MHz, ext. clk. V CC = 1.8V V CC = 3.0V MHz, ext. clk. V CC = 1.8V V CC = 3.0V MHz, ext. clk kHz, ext. clk. V CC = 1.8V V CC = 3.0V MHz, ext. clk. V CC = 1.8V V CC = 3.0V MHz, ext. clk. V CC = 1.8V ma µa 32MHz, ext. clk ma T = 25 C Power-down power consumption T = 85 C V CC = 3.0V WDT and sampled BOD enabled, T = 25 C WDT and sampled BOD enabled, T = 85 C RTC from ULP clock, WDT and sampled BOD enabled, T = 25 C V CC = 1.8V V CC = 3.0V µa Power-save power consumption Reset power consumption RTC from 1.024kHz low power kHz TOSC, T = 25 C RTC from low power kHz TOSC, T = 25 C Current through RESET pin subtracted V CC = 1.8V V CC = 3.0V V CC = 1.8V V CC = 3.0V V CC = 3.0V

9 7.2 Increased ADC Maximum Samples Rate The maximum ADC clock frequency and sample rate is increased, as shown in Table 7-2. Table 7-2. ADC Characteristics Revision E Revision I Parameter Min. Typ. Max. Min. Typ. Max. Units ADC clock frequency khz ADC samples rate ksps 7.3 Reduced Analog Comparator Propagation Delay The Analog Comparator propagation delay is reduced, as shown in Table 7-3. Table 7-3. Analog Comparator Characteristics Revision E Revision I Parameter Condition Min. Typ. Max. Min. Typ. Max. Units Propagation delay V CC = 3.0V, T = 85 C Propagation delay V CC = V, T = 25 C ns kHz Internal ULP Oscillator Frequency The frequency of the 32kHz internal ULP oscillator is increased to match its nominal frequency with guaranteed accuracy. Table kHz Internal ULP Oscillator Frequency Revision E Revision I Parameter Condition Min. Typ. Max. Min. Typ. Max. Units Factory calibrated frequency khz Factory calibration accuracy V CC = 3.0V, T = 85 C na na Accuracy na Na % 9

10 8 Revision History Doc Rev. Date Comments 42401A 02/2015 Initial document release. 10

11 Atmel Corporation 1600 Technology Drive, San Jose, CA USA T: (+1)(408) F: (+1)(408) Atmel Corporation. / Rev.:. Atmel, Atmel logo and combinations thereof, AVR, Enabling Unlimited Possibilities, XMEGA, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death ( Safety-Critical Applications ) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended AT11008: for use in Migration military or aerospace from applications ATxmega16D4/32D4 or environments unless specifically Revision designated E to Revision by Atmel as military-grade. I [APPLICATION Atmel products NOTE] are not designed nor intended for use in automotive applications unless specifically designated by as automotive-grade. 11