NUP2202W1T2G. ESD Protection Diode Low Clamping Voltage SC 88 LOW CAPACITANCE DIODE SURGE PROTECTION ARRAY 500 WATTS PEAK POWER 6 VOLTS

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1 ESD Protection Diode Low Clamping Voltage The NUP2202W1 surge protection is designed to protect high speed data lines from ESD, EFT, and lightning. Features: Low Clamping Voltage Stand Off Voltage: 5 V Low Leakage Protection for the Following IEC Standards: IEC Level 4 ESD Protection UL Flammability Rating of 94 V 0 This is a Pb Free Device SC 88 LOW CAPACITANCE DIODE SURGE PROTECTION ARRAY 500 WATTS PEAK POWER VOLTS PIN CONFIGURATION AND SCHEMATIC Typical Applications: High Speed Communication Line Protection USB 1.1 and 2.0 Power and Data Line Protection Digital Video Interface (DVI) and HDMI Monitors and Flat Panel Displays MP3 I/O 1 V N 2 N/C 3 I/O 5 V P 4 N/C MAXIMUM RATINGS (T J = 25 C unless otherwise noted) Rating Symbol Value Unit Peak Power Dissipation 8 x 20 T A = 25 C (Note 1) P pk 500 W Operating Junction Temperature Range T J 40 to +125 C Storage Temperature Range T stg 55 to +150 C Lead Solder Temperature Maximum (10 Seconds) Human Body Model (HBM) Machine Model (MM) IEC Air (ESD) IEC Contact (ESD) T L 20 C ESD IEC (5/50 ns) EFT 40 A Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2). See Application Note AND8308/D for further description of survivability specs. V SC 88 CASE 419B PLASTIC MARKING DIAGRAM ORDERING INFORMATION Device Package Shipping NUP2202W1T2G 1 1 SCALE 2:1 2 M 2 = Specific Device Code M = Date Code = Pb Free Package (Note: Microdot may be in either location) SC 88 Pb Free 3000/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2009 October, 2017 Rev. 4 1 Publication Order Number: NUP2202W1/D

2 ELECTRICAL CHARACTERISTICS (T A = 25 C unless otherwise noted) Symbol I PP Parameter Maximum Reverse Peak Pulse Current I F I V C Clamping I PP V RWM I R Working Peak Reverse Voltage Maximum Reverse Leakage V RWM V RWM V C V BR I R I T V F V V BR Breakdown I T I T Test Current I F Forward Current I PP V F Forward I F P pk Peak Power Dissipation C V R = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. Uni Directional ELECTRICAL CHARACTERISTICS (T J =25 C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage V RWM (Note 2) 5.0 V Breakdown Voltage V BR I T = 1 ma, (Note 3).0 V Reverse Leakage Current I R V RWM = 5 V 5.0 A Clamping Voltage V C I PP = 5 A (Note 4) V Clamping Voltage V C I PP = 8 A (Note 4) V Maximum Peak Pulse Current I PP 8x20 s Waveform (Note 4) 28 A Junction Capacitance C J V R = 0 V, f = 1 MHz between I/O Pins and GND pf Junction Capacitance C J V R = 0 V, f = 1 MHz between I/O Pins pf Clamping Voltage V C Per IEC (Note ) Figure 1 and 2 V 2. surge protection devices are normally selected according to the working peak reverse voltage (V RWM ), which should be equal or greater than the DC or continuous peak operating voltage level. 3. V BR is measured at pulse test current I T. 4. Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2). 5. Surge current waveform per Figure 5.. For test procedure see Figures 3 and 4 and Application Note AND8307/D. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kv Contact per IEC Figure 2. ESD Clamping Voltage Screenshot Negative 8 kv Contact per IEC

3 IEC Spec. Level Test Voltage (kv) First Peak Current (A) Current at 30 ns (A) Current at 0 ns (A) IEC Waveform I peak 100% 90% 30 ns 0 ns 10% t P = 0.7 ns to 1 ns Figure 3. IEC Spec ESD Gun Device Under Test Oscilloscope 50 Cable 50 The following is taken from Application Note AND8308/D Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC waveform. Since the IEC was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT Figure 4. Diagram of ESD Test Setup t r t P PEAK VALUE I 8 s t, TIME ( s) Figure 5. 8 x 20 s Pulse Waveform systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. PULSE WIDTH (t P ) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 s HALF VALUE I RSM 20 s 3

4 TYPICAL PERFORMANCE CURVES (T J = 25 C unless otherwise noted) PEAK POWER DISSIPATION (%) T A, AMBIENT TEMPERATURE ( C) Figure. Pulse Derating Curve JUNCTION CAPACITANCE (pf) I/O Ground I/O lines CLAMPING VOLTAGE (V) V BR, REVERSE VOLTAGE (V) Figure 7. Junction Capacitance vs Reverse Voltage PEAK PULSE CURRENT (A) Figure 8. Clamping Voltage vs. Peak Pulse Current (8 x 20 s Waveform) 4

5 APPLICATIONS INFORMATION The NUP2202W1 is a low capacitance surge protection diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used on high speed I/O data lines. The integrated design of the NUP2202W1 offers surge rated, low capacitance steering diodes and a surge protection diode integrated in a single package (SC 88). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The surge protection device protects the power line against overvoltage conditions to avoid damage to the power supply and any downstream components. NUP2202W1 Device Configuration Options The NUP2202W1 is able to protect two data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or V CC + Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1 and. The negative reference is connected at pin 2. This pin must be connected directly to ground by using a ground plane to minimize the PCB s ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductance. Option 1 Protection of two data lines and the power supply using V CC as reference. I/O 1 I/O V CC For this configuration, connect pin 5 directly to the positive supply rail (V CC ), the data lines are referenced to the supply voltage. The internal surge protection diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. Option 2 Protection of two data lines with bias and power supply isolation resistor. I/O 1 I/O V CC 10 k The NUP2202W1 can be isolated from the power supply by connecting a series resistor between pin 5 and V CC. A 10 k resistor is recommended for this application. This will maintain bias on the internal surge protection and steering diodes, reducing their capacitance. Option 3 Protection of two data lines using the internal surge protection diode as reference. I/O 1 I/O In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal surge protection can be used as the reference. For these applications, pin 5 is not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the surge protection plus one diode drop (Vc = Vf + V RWM ). ESD Protection of Power Supply Lines When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: 5 4 NC 5

6 Power Supply Protected Device Data Line V CC D1 D2 I ESDpos I ESDneg I ESDpos VF + V CC I ESDneg VF Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = V CC + Vf D1 For negative pulse conditions: Vc = Vf D2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. Power Supply V CC Protected Device Data Line D1 D2 I ESDpos I ESDpos I ESDneg V C = V CC + Vf + (L diesd/dt) I ESDneg Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP2202W1 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a surge protection diode within a network of steering diodes. D1 D2 D3 D4 Figure 9. NUP2202W1 Equivalent Circuit During an ESD condition, the ESD current will be driven to ground through the surge protection diode as shown below. Power Supply V CC 0 D1 I ESDpos V C = Vf (L diesd/dt) An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = V CC + Vf + (L diesd/dt) For negative pulse conditions: Vc = Vf (L diesd/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the L diesd/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board layout. Taking care to minimize the effects of parasitic inductance will provide significant benefits in transient immunity. Protected Device Data Line The resulting clamping voltage on the protected IC will be: Vc = VF + VRWM. The clamping voltage of the surge protection diode is provided in Figure 8 and depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. D2

7 TYPICAL APPLICATIONS UPSTREAM USB PORT D+ D GND USB Controller C T C T R T R T NUP4202W1 D+ D GND DOWNSTREAM USB PORT NUP2202W1 C T C T R T R T D+ D GND DOWNSTREAM USB PORT Figure 10. ESD Protection for USB Port 7

8 PACKAGE DIMENSIONS SC 88/SC70 /SOT 33 CASE 419B 02 ISSUE Y E 2X bbb H D e X ccc C A D B TOP VIEW SIDE VIEW A1 2X D E1 aaa H aaa 2X 3 TIPS X b ddd M A2 A C D L2 C C DETAIL A SEATING PLANE H A-B D L DETAIL A END VIEW GAGE PLANE c NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU- SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H.. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI- TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. MILLIMETERS DIM MIN NOM MAX A 1.10 A INCHES MIN NOM MAX A b C D E E e 0.5 BSC 0.02 BSC L L BSC 0.00 BSC aaa bbb ccc ddd RECOMMENDED SOLDERING FOOTPRINT* X 0.30 X PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8

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