1N5333B Series. 5 Watt Surmetic 40 Zener Voltage Regulators

Transcription

1 Preferred Device Watt Surmetic 40 Zener Voltage Regulators This is a complete series of Watt Zener diodes with tight limits and better operating characteristics that reflect the superior capabilities of silicon-oxide passivated junctions. All this in an axial lead, transfer-molded plastic package that offers protection in all common environmental conditions. Features Zener Voltage Range V to 0 V ESD Rating of Class 3 (>6 kv) per Human Body Model Surge Rating of up to ms Maximum Limits Guaranteed on up to Six Electrical Parameters Pb-Free Packages are Available* Mechanical Characteristics CASE: Void free, transfer-molded, thermosetting plastic FINISH: All external surfaces are corrosion resistant and leads are readily solderable MAXIMUM LEAD TEMPERATURE FOR SOLDERING PURPOSES: 60 C, /6 in. from the case for seconds POLARITY: Cathode indicated by polarity band MOUNTING POSITION: Any MAXIMUM RATINGS Rating Symbol Value Unit Max. Steady State Power T L = 7 C, Lead Length = 3/8 in Derate above 7 C P D 40 W mw/ C Operating and Storage Temperature Range T J, T stg -6 to +0 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Cathode Anode AXIAL LEAD CASE 07AA PLASTIC MARKING DIAGRAM A N 3xxB YYWW A = Assembly Location N3xxB = Device Number (Refer to Tables on Pages 3 & 4) YY = Year WW = Work Week = Pb-Free Package (Note: Microdot may be in either location) Device Package Shipping N3xxB, G N3xxBRL, G ORDERING INFORMATION Axial Lead (Pb-Free) Axial Lead (Pb-Free) 00 Units/Box 4000/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. Preferred devices are recommended choices for future use and best overall value. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 08 January, 08 - Rev. Publication Order Number: N333B/D

2 ELECTRICAL CHARACTERISTICS (T A = C unless otherwise noted, V F =. V I F =.0 A for all types) Symbol Parameter I F I V Z I ZT Z ZT I ZK Z ZK V R I F Reverse Zener I ZT Reverse Current Maximum Zener I ZT Reverse Current Maximum Zener I ZK Reverse Leakage V R Breakdown Voltage Forward Current V R V Z I ZT V F V V F Forward I F Maximum Surge T A = C V Z Reverse Zener Voltage Change I ZM Maximum DC Zener Current Zener Voltage Regulator ELECTRICAL CHARACTERISTICS (T A = C unless otherwise noted, V F =. V I F =.0 A for all types) Device (Note ) Device Marking Zener Voltage (Note ) Zener Impedance (Note ) Leakage Current V Z I ZT Z I ZT Z I ZK I V R (Note 3) V Z (Note 4) I ZM (Note ) Min Nom Max ma ma A Max Volts A Volts ma N333B, G N333B N334BG N334B N33BG N33B N336BG N336B N337BG N337B N338BG N338B N339B, G N339B N340B, G N340B N34B, G N34B N34BG N34B N343BG N343B N344B, G N344B N34B, G N34B N346BG N346B N347B, G N347B Devices listed in bold, italic are ON Semiconductor Preferred devices. Preferred devices are recommended choices for future use and best overall value.. TOLERANCE AND TYPE NUMBER DESIGNATION: The JEDEC type numbers shown indicate a tolerance of ±%.. ZENER VOLTAGE (V Z ) and IMPEDANCE (I ZT and I ZK ): Test conditions for zener voltage and impedance are as follows: I Z is applied 40 ± ms prior to reading. Mounting contacts are located 3/8 to / from the inside edge of mounting clips to the body of the diode (T A = C +8 C, - C). 3. SURGE CURRENT ( ): Surge current is specified as the maximum allowable peak, non-recurrent square-wave current with a pulse width, PW, of 8.3 ms. The data given in Figure may be used to find the maximum surge current for a square wave of any pulse width between ms and 00 ms by plotting the applicable points on logarithmic paper. Examples of this, using the 3.3 V and 0 V zener are shown in Figure 6. Mounting contact located as specified in Note (T A = C +8 C, - C). 4. VOLTAGE REGULATION ( V Z ): The conditions for voltage regulation are as follows: V Z measurements are made at % and then at 0% of the I Z max value listed in the electrical characteristics table. The test current time duration for each V Z measurement is 40 ± ms. Mounting contact located as specified in Note (T A = C +8 C, - C).. MAXIMUM REGULATOR CURRENT (I ZM ): The maximum current shown is based on the maximum voltage of a % type unit, therefore, it applies only to the B-suffix device. The actual I ZM for any device may not exceed the value of watts divided by the actual V Z of the device. T L = 7 C at 3/8 maximum from the device body. The G'' suffix indicates Pb-Free package or Pb-Free packages are available.

3 ELECTRICAL CHARACTERISTICS (T A = C unless otherwise noted, V F =. V I F =.0 A for all types) Device (Note 6) Device Marking Zener Voltage (Note 7) Zener Impedance (Note 7) Leakage Current V Z I ZT Z I ZT Z I ZK I V R (Note 8) V Z (Note 9) I ZM (Note ) Min Nom Max ma ma A Max Volts A Volts ma N348BG N348B N349B, G N349B N30B, G N30B N3BG N3B N3B, G N3B N33B, G N33B N34B, G N34B N3B, G N3B N36BG N36B N37BG N37B N38B, G N38B N39B, G N39B N360BG N360B N36B, G N36B N36BG N36B N363BG N363B N364BG N364B N36B, G N36B N366B, G N366B N367BG N367B N368BG N368B N369B, G N369B N370B, G N370B N37BG N37B N37BG N37B N373B, G N373B N374BG N374B N37BG N37B N377BG N377B N378B, G N378B N380BG N380B N38BG N38B N383B, G N383B N384BG N384B N386BG N386B N387BG N387B N388B, G N388B Devices listed in bold, italic are ON Semiconductor Preferred devices. Preferred devices are recommended choices for future use and best overall value. 6. TOLERANCE AND TYPE NUMBER DESIGNATION: The JEDEC type numbers shown indicate a tolerance of ±%. 7. ZENER VOLTAGE (V Z ) and IMPEDANCE (I ZT and I ZK ): Test conditions for zener voltage and impedance are as follows: I Z is applied 40 ± ms prior to reading. Mounting contacts are located 3/8 to / from the inside edge of mounting clips to the body of the diode (T A = C +8 C, - C). 8. SURGE CURRENT ( ): Surge current is specified as the maximum allowable peak, non-recurrent square-wave current with a pulse width, PW, of 8.3 ms. The data given in Figure may be used to find the maximum surge current for a square wave of any pulse width between ms and 00 ms by plotting the applicable points on logarithmic paper. Examples of this, using the 3.3 V and 0 V zener are shown in Figure 6. Mounting contact located as specified in Note 7 (T A = C +8 C, - C). 9. VOLTAGE REGULATION ( V Z ): The conditions for voltage regulation are as follows: V Z measurements are made at % and then at 0% of the I Z max value listed in the electrical characteristics table. The test current time duration for each V Z measurement is 40 ± ms. Mounting contact located as specified in Note 7 (T A = C +8 C, - C)..MAXIMUM REGULATOR CURRENT (I ZM ): The maximum current shown is based on the maximum voltage of a % type unit, therefore, it applies only to the B-suffix device. The actual I ZM for any device may not exceed the value of watts divided by the actual V Z of the device. T L = 7 C at 3/8 maximum from the device body. The G'' suffix indicates Pb-Free package or Pb-Free packages are available. 3

4 θ JL, JUNCTION TO LEAD THERMAL RESISTANCE ( C/W) PRIMARY PATH OF CONDUCTION IS THROUGH THE CATHODE LEAD L, LEAD LENGTH TO HEATSINK (INCH) L L Figure. Typical Thermal Resistance TEMPERATURE COEFFICIENTS θvz, TEMPERATURE COEFFICIENT (mv/ I ZT RANGE V Z, ZENER I ZT (VOLTS) Figure. Temperature Coefficient Range for Units 3 to Volts θvz, TEMPERATURE COEFFICIENT (mv/ I ZT RANGE V Z, ZENER I ZT (VOLTS) Figure 3. Temperature Coefficient Range for Units to Volts 4

5 θjl (t, D), TRANSIENT THERMAL RESISTANCE JUNCTION TO LEAD ( C/W) 0. D = 0. D = 0. D = 0. D = 0.0 D = 0.0 NOTE: BELOW 0. SECOND, THERMAL NOTE: RESPONSE CURVE IS APPLICABLE NOTE: TO ANY LEAD LENGTH (L). D = t, TIME (SECONDS) Figure 4. Typical Thermal Response L, Lead Length = 3/8 Inch P PK DUTY CYCLE, D = t /t SINGLE PULSE T JL = JL (t)p PK REPETITIVE PULSES T JL = JL (t, D)P PK t t I r, PEAK SURGE CURRENT (AMPS) *SQUARE WAVE PW = ms* PW = 0 ms* PW = 8.3 ms* 0. PW = 00 ms* NOMINAL V Z (V) Figure. Maximum Non Repetitive Surge Current versus Nominal Zener Voltage (See Note 3) I r, PEAK SURGE CURRENT (AMPS) V Z = 0 V V Z = 3.3 V 0. PLOTTED FROM INFORMATION GIVEN IN FIGURE PW, PULSE WIDTH (ms) Figure 6. Peak Surge Current versus Pulse Width (See Note 3) 00 I Z, ZENER CURRENT (ma) 00 0 T C = C T = C I Z, ZENER CURRENT (ma) 0 T = C V Z, ZENER VOLTAGE (VOLTS) Figure 7. Zener Voltage versus Zener Current V Z = 3.3 thru Volts V Z, ZENER VOLTAGE (VOLTS) Figure 8. Zener Voltage versus Zener Current V Z = thru 7 Volts

6 I Z, ZENER CURRENT (ma) V Z, ZENER VOLTAGE (VOLTS) Figure 9. Zener Voltage versus Zener Current V Z = 8 thru 0 Volts APPLICATION NOTE Since the actual voltage available from a given Zener diode is temperature dependent, it is necessary to determine junction temperature under any set of operating conditions in order to calculate its value. The following procedure is recommended: Lead Temperature, T L, should be determined from: T L = LA P D + T A LA is the lead to ambient thermal resistance and P D is the power dissipation. Junction Temperature, T J, may be found from: T J = T L + T JL T JL is the increase in junction temperature above the lead temperature and may be found from Figure 4 for a train of power pulses or from Figure for dc power. T JL = JL P D For worst case design, using expected limits of I Z, limits of P D and the extremes of T J ( T J ) may be estimated. Changes in voltage, V Z, can then be found from: V = VZ T J VZ, the Zener voltage temperature coefficient, is found from Figures and 3. Under high power pulse operation, the Zener voltage will vary with time and may also be affected significantly by the zener resistance. For best regulation, keep current excursions as low as possible. Data of Figure 4 should not be used to compute surge capability. Surge limitations are given in Figure. They are lower than would be expected by considering only junction temperature, as current crowding effects cause temperatures to be extremely high in small spots resulting in device degradation should the limits of Figure be exceeded. 6

7 PACKAGE DIMENSIONS SURMETIC 40, AXIAL LEAD CASE 07AA-0 ISSUE O B D F K NOTES:. CONTROLLING DIMENSION: INCH. LEAD DIAMETER AND FINISH NOT CONTROLLED WITHIN DIMENSION F. 3. CATHODE BAND INDICATES POLARITY INCHES MILLIMETERS DIM MIN MAX MIN MAX A B D F K A K F SURMETIC is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative N333B/D