SP512MBRDE333K pin DDR SDRAM Registered Module

Transcription

1 SP512MBRDE333K01 184pin DDR SDRAM Registered Module SILICON POWER Computer and Communications, INC. Corporate Office 7F, No. 106, Zhou-Z Street NeiHu Dist., Taipei 114, Taiwan, R.O.C. This document is a general product description and is subject to change without notice Rev 1.0 July 2007

2 Revision History Revision No. Date Remarks /07/25 First issue Table of contents 1. Description Features Module Specification Simplified Mechanical Drawing with Keying Positions outs Description Block Diagram Register and PLL Specifications PLL Clock Driver Timing Requirements and Switching Characteristics Absolute Maximum DC Ratings AC Operating Conditions DC Electrical Characteristics and Operating Conditions Command Truth Table IDD Specifications and Conditions Timing Parameters & Specifications Serial Presence-Detect Matrix Rev 1.0 July 2007

3 1. Description The SP512MBRDE333K01 is a 32M x 8bits Double Data Rate SDRAM high-density for DDR-333.The SP512MBRDE333K01 consists of 16pcs CMOS 32x8 bits Double Data Rate SDRAMs in 66 pin TSOP package, and a 2048 bits serial EEPROM on a 184-pin printed circuit board. The SP512MBRDE333K01 is a Dual In-Line Memory Module and is intended for mounting into 184-pin connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. 2. Features Double--data--rate architecture; two data transfers per clock cycle Bidirectional, data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver DQS is edge--aligned with data for READs; center--aligned with data for WRITEs Differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Four internal banks for concurrent operation Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver to reduce loading Supports ECC error detection and correction Data mask (DM) for write data Burst lengths: 2, 4, or 8 AUTOPRECHARGE option for each burst access Auto Refresh and Self Refresh Modes JEDEC standard 2.5 V (SSTL_2 compatible) I/O 66pin TSOP II Leaded & Pb-Free (RoHS compliant) package 2 Rev 1.0 July 2007

4 3. Module Specification Item Specification Capacity 512MByte Physical Bank(s) 2 Module Organization 64M x 72bit Module Type Registered Speed Grade PC 2700/CL=2.5,tRCD=3,tRP=3 (DDR333) Voltage Interface SSTL_2 Power Supply Voltage 2.5V±0.1V Burst Lengths 2,4,8 DRAM Organization 32M x 8bit DDR SDRAM PCB Layer 6Layers Contact Tab 184pin GOLD Flash Plating Serial PD Support 4. Simplified Mechanical Drawing with Keying Positions Notes:1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 3 Rev 1.0 July 2007

5 5. outs Num Name Num Name Num Name Num Name Num Name Num Name Num Name Num Name 01 VREF 24 DQ17 47 DQS8 70 VDD 93 VSS 116 VSS 139 VSS 162 DQ47 02 DQ0 25 DQS2 48 A0 71 NC 94 DQ4 117 DQ DM8 163 NC 03 VSS 26 VSS 49 CB2 72 DQ48 95 DQ5 118 A A VDDQ 04 DQ1 27 A9 50 VSS 73 DQ49 96 VDDQ 119 DM2 142 CB6 165 DQ52 05 DQS0 28 DQ18 51 CB3 74 VSS 97 DM0 120 VDD 143 VDDQ 166 DQ53 06 DQ2 29 A7 52 BA1 75 */CK2 98 DQ6 121 DQ CB7 167 NC/A13 07 VDD 30 VDDQ 53 DQ32 76 *CK2 99 DQ7 122 A8 145 VSS 168 VDD 08 DQ3 31 DQ19 54 VDDQ 77 VDDQ 100 VSS 123 DQ DQ DM6 09 NC 32 A5 55 DQ33 78 DQS6 101 NC 124 VSS 147 DQ DQ54 10 /RESET 33 DQ24 56 DQS4 79 DQ NC 125 A6 148 VDD 171 DQ55 11 VSS 34 VSS 57 DQ34 80 DQ NC 126 DQ DM4 172 VDDQ 12 DQ8 35 DQ25 58 VSS 81 VSS 104 VDDQ 127 DQ DQ NC 13 DQ9 36 DQS3 59 BA0 82 VDDID 105 DQ VDDQ 151 DQ DQ60 14 DQS1 37 A4 60 DQ35 83 DQ DQ DM3 152 VSS 175 DQ61 15 VDDQ 38 VDD 61 DQ40 84 DQ DM1 130 A3 153 DQ VSS 16 *CK1 39 DQ26 62 VDDQ 85 VDD 108 VDD 131 DQ /RAS 177 DM7 17 */CK1 40 DQ27 63 /WE 86 DQS7 109 DQ VSS 155 DQ DQ62 18 VSS 41 A2 64 DQ41 87 DQ DQ DQ VDDQ 179 DQ63 19 DQ10 42 VSS 65 /CAS 88 DQ CKE1 134 CB4 157 /S0 180 VDDQ 20 DQ11 43 A1 66 VSS 89 VSS 112 VDDQ 135 CB5 158 /S1 181 SA0 21 CKE0 44 CB0 67 DQS5 90 NC 113 *BA2 136 VDDQ 159 DM5 182 SA1 22 VDDQ 45 CB1 68 DQ42 91 SDA 114 DQ CK0 160 VSS 183 SA2 23 DQ16 46 VDD 69 DQ43 92 SCL 115 NC/A /CK0 161 DQ VDDSPD NOTE:1. * : These pins are not used in this module is No Connect for 256MB, or A12 for 512MB and 1GB is NC for 256MB, 512MB, and 1GB, or A13 for 2GB. 4 Rev 1.0 July 2007

6 6. Description SYMBOL TYPE DESCRIPTION CK, /CK Input Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output data (DQs and DQS /DQS) is referenced to the crossings of CK and /CK. /RAS, /CAS, /WE Input Command Inputs: /RAS, /CAS and /WE (along with /S) define the command being entered. CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. /S0-/S1 Input Chip Select: Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 DM0-DM8 BA0 - BA2 A0 - A15 Input Input Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command. Bank Address Inputs: BA0 and BA1 for 256 and 512Mb, BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands. DQ0-DQ63 Input/Output Data bit Input/ Output: Bi-directional data bus. CB0-CB7 Input/Output ECC check bits. DQS0-DQS7 /DQS0-/DQS7 NC VDDQ VDD, VSS Input/Output Supply Supply Data Strobe: output with read data, input with write data for source-synchronous operation. Edge-aligned with read data, center-aligned with write data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM. No Connect: No internal electrical connection is present. Power supplies for the DDR SDRAM output buffers to provide improved noise immunity. For all current DDR unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins Power and ground for the DDR SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD / VDDQ planes on these modules. VREF Supply Reference voltage for SSTL 18 inputs. SDA SCL VDDSPD SA0-SA2 /RESET Input/Output Input Supply Input Input This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pullup on the system board. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pullup onthe system board. Power supply for SPD EEPROM. This supply is separate from the VDD / VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. These signals and tied at the system planar to either VSS or VDD to configure the serial SPD EERPOM address range. The /RESET pin is connected to the /RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchronized with the input clock. 5 Rev 1.0 July 2007

7 7. Block Diagram 6 Rev 1.0 July 2007

8 8. Register and PLL Specifications Register Symbol Paramerter Condition VDD = +2.6V Units Notes ±0.1V Min Max STL (bit pattern by JESD82-3 or JESD82-4) tclock Clock Frequency MHz tpd Clock to Output Time 30pF to GND and ns tphl Reset to Output Time 50Ω to VTT 5 ns tw Pulse Duration CK, /CK HIGH or LOW ns tact Differential Inputs - 22 ns 2 Active Time tinact Differential Inputs - 22 ns 3 Inactive Time tsu Setup Time, Fast Slew Data Before CK ns 4, 6 Rate HIGH, /CK LOW Setup Time, Slow Slew ns 5, 6 Rate th Hold Time, Fast Slew Data After CK 0.75 ns 4, 6 Rate HIGH, /CK LOW Hold Time, Slow Slew 0.9 ns 5, 6 Rate NOTE:1. Timing and switching specifications for the register listed above are critical for proper operation of DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD Data inputs must be low a minimum time of tact max, after /RESET is taken HIGH. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after /RESET is taken LOW. 4. For data signal input slew rate 1 V/ns. 5. For data signal input slew rate 0.5 V/ns and < 1V/ns. 6. CK, /CK signals input slew rate 1V/ns. 7 Rev 1.0 July 2007

9 9. PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Symbol VDD = +2.6V ±0.1V Units notes Min Nominal Max Operating Clock Frequency tck MHz 2, 3 Input Duty Cycle tdc % Stabilization Time tstab ms 4 Cycle to Cycle Jitter tjitcc ps Static Phase Offset t ps 5 Output Clock Skew tsko ps Period Jitter tjitper ps 6 Half-Period Jitter tjithper ps 6 Input Clock Slew Rate tlsi V/ns Output Clock Slew Rate tlso V/ns 7 NOTE:1. Timing and switching specifications for the PLL listed above are critical for proper operation of DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this PLL is available in JEDEC Standard JESD The PLL must be able to handle spread spectrum induced skew. 3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low-speed system debug.) 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. 5. Static Phase Offset does not include Jitter. 6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. 7. The Output Slew Rate is determined from the IBIS model: 8 Rev 1.0 July 2007

10 10. Absolute Maximum DC Ratings Parameter Value Unit Voltage on Vdd Supply Relative to Vss - 1 V to +3.6 V V Voltage on VddQ Supply Relative to Vss - 1 V to +3.6 V V Voltage on Inputs Relative to Vss - 1 V to +3.6 V V Voltage on I/O s Relative to Vss V to VddQ+0.5 V V Operating Temperature, TA 0 C to +70 C C Storage Temperature - 55 C to +150 C C Short Circuit Output Current 50 ma ma NOTE:1.Permanent damage to the device may occur if Absolute Maximum Ratings are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. 11. AC Operating Conditions PARAMETER/CONDITION SYMBOL MIN MAX UNITS Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(ac) VREF V Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(ac) VREF V Input Differential Voltage, CK and /CK inputs VID(ac) 0.7 VDDQ V Input Crossing Point Voltage, CK and /CK inputs VIX(ac) 0.5*VDDQ *VDDQ+0.2 V NOTE:1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. 12. DC Electrical Characteristics and Operating Conditions ARAMETER/CONDITION SYMBOL MIN MAX UNITS Supply Voltage (for DDR400) VDD V I/O Supply Voltage (for DDR400) VDDQ V I/O Reference Voltage VREF 0.49*VDDQ 0.51*VDDQ V I/O Termination Voltage (system) VTT VREF VREF+0.04 V Input High (Logic 1) Voltage VIH(DC) VREF+0.15 VDD+0.3 V Input Low (Logic 0) Voltage VIL(DC) -0.3 VREF-0.15 V Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.36 VDDQ+0.6 V V--I Matching: Pullup to Pulldown Current Ratio VI(Ratio) INPUT LEAKAGE CURRENT ILI -2 2 µa 9 Rev 1.0 July 2007

11 ARAMETER/CONDITION SYMBOL MIN MAX UNITS OUTPUT LEAKAGE CURRENT ILO -5 5 µa Output High Current (VOUT = 1.95V) IOH ma Output Low Current (VOUT = 0.35V) IOL 16.8 ma NOTE:1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed ± 2% of the DC value. 4. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to VIN=0 to VDD, All other pins are not tested under VIN =0V. 7. DQs are disabled, VOUT=0 to VDDQ 13. Command Truth Table (V=Valid, X=Don't Care, H=Logic High, L=Logic Low) COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/ AP Register Extended MRS H X L L L L OP CODE Register Mode Register Set H X L L L L OP CODE A0~A9 A11,A12 Refresh Auto Refresh Self Refresh H H Entry L Exit L H L L L H X L H H H X H X X X Bank Active & Row Addr. H X L L H H V ROW Address Read & Column Address Auto Precharge Disable Auto Precharge Enable H X L H L H V L H Column Address Write & Column Address Auto Precharge Disable Auto Precharge Enable H X L H L L V L H Column Address Burst Stop H X L H H L X Precharge Bank Selection V L H X L L H L All Banks X H X Active Power Down Entry H L H X X X L V V V X Exit L H X X X X 10 Rev 1.0 July 2007

12 COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/ AP Precharge Power Down Mode Entry H L Exit L H H X X X L H H H H X X X L H H H X A0~A9 A11,A12 DM H X X Device Deselect H X X X H X No operation L H H H X NOTE:1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at trp after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. 11 Rev 1.0 July 2007

13 14. IDD Specifications and Conditions Values shown for DDR SDRAM components only Parameter/Condition Symbol MAX Units Operating one bank active-precharge current: tck = tck (IDD), trc = trc (IDD), tras = tras MIN (IDD); CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. IDD ma Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tck = tck (IDD), trc = trc (IDD), tras = tras MIN (IDD); trcd = trcd (IDD); CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Precharge power-down current: All device banks idle; tck = tck (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge quiet standby current: All device banks idle; tck = tck (IDD); CKE is HIGH, /S is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge standby current: All device banks idle; tck = tck (IDD); CKE is HIGH, /S is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Active power-down current: All device banks open; tck = tck (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Active standby current: All device banks open; tck = tck (IDD)); tras = tras MAX (IDD), trp = trp (IDD), CKE is HIGH, /S is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst write current: All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tck = tck (IDD), tras = tras MAX (IDD), trp = trp (IDD), CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst read current: All device banks open, Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tck = tck (IDD), tras = tras MAX (IDD), trp = trp (IDD), CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Burst refresh current: tck = tck (IDD); Refresh command at every trfc (IDD) interval; CKE is HIGH, /S is HIGH between valid commands; Others control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Self refresh current: CK and /CK at 0V; CKE = 0.2V; Others control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating device bank interleave read current: All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = trcd (IDD)-1 x tck (IDD), tck = tck (IDD), trc = trc (IDD), trrd = trrd (IDD), trcd = trdd (IDD),CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are STABLE during DESELECT; Data bus inputs are SWITCHING, See IDD7 Conditions for detail. IDD ma IDD2P 72 ma IDD2Q 900 ma IDD2N 950 ma IDD3P 540 ma IDD3N 1080 ma IDD4W 1611 ma IDD4R 1611 ma IDD ma IDD6 72 ma IDD ma 12 Rev 1.0 July 2007

14 15. Timing Parameters & Specifications (These AC characteristics were tested on the Component) Parameter Symbol MIN MAX Units Access window of DQs from CK, /CK tac ns CK high-level width tch tck CK low-level width tcl tck Clock cycle time CL = ns tck CL = ns DQ and DM input hold time relative to DQS tdh 0.45 ns DQ and DM input setup time relative to DQS tds 0.45 ns DQ and DM input pulse width (for each input) tdipw 1.75 ns Access window of DQs from CK, /CK tdqsck ns DQS input high pulse width tdqsh 0.35 tck DQS input low pulse width tdqsl 0.35 tck DQS-DQ skew, DQS to last DQ valid, per group, per access tdqsq 0.45 ns Write command to first DQS latching transition tdqss tck DQS falling edge to CK rising - setup time tdss 0.20 tck DQS falling edge from CK rising - hold time tdsh 0.20 tck Half clock period thp tch, tcl ns Data-out high-impedance window from CK, /CK thz ns Data-out low-impedance window from CK, /CK tlz ns Address and control input hold time (fast slew rate) tihf 0.75 ns Address and control input setup time (fast slew rate) tisf 0.75 ns Address and control input hold time (slow slew rate) tihs 0.80 ns Address and control input setup time (slow slew rate) tiss 0.80 ns LOAD MODE REGISTER command cycle time tmrd 2 tck DQ-DQS hold, DQS to first DQ to go non-valid, per access tqh thp - tqhs ns Data hold skew factor tqhs 0.55 ns ACTIVE to PRECHARGE command tras 42 70,000 ns ACTIVE to READ with auto precharge command trap 18 ns ACTIVE to ACTIVE/AUTO REFRESH command period trc 60 ns AUTO REFRESH command period trfc 72 ns ACTIVE to READ or WRITE delay trcd 18 ns PRECHARGE command period trp 18 ns DQS read preamble trpre tck DQS read postamble trpst tck 13 Rev 1.0 July 2007

15 Parameter Symbol MIN MAX Units ACTIVE bank a to ACTIVE bank b command trrd 12 ns DQS write preamble twpre 0.25 tck DQS Write Postamble setup time twpres 0 ns DQS Write Postamble twpst tck Write recovery time twr 15 ns Internal Write to READ command delay twtr 1 tck Average periodic refresh interval trefi 7.8 µs Exit SELF REFRESH to non-read command txsnr 200 ns Exit SELF REFRESH to READ command txsrd 200 tck 16. Serial Presence-Detect Matrix Byte Description Entry (Version) Value 00 Number of SPD Bytes Total Number of Bytes in SPD Device Fundamental Memory Type DDR SDRAM Number of Row Addresses on Assembly 13 0D 04 Number of Column Addresses on Assembly 10 0A 05 Number of DIMM Ranks Module Data Width Module Data Width Continuation Module Voltage Interface Levels SSTL 2.5V SDRAM Cycle Time (tck) 6ns SDRAM Access from Clock(tAC) 0.70ns Module Configuration Type Registered Refresh Rate/Type 7.8μs SDRAM Device Width (Primary SDRAM) Error-checking SDRAM Data Width ECC SDRAM Device Attributes-Minimum Clock Delay, Back-to-Back trrd=1 tck 01 Random Column Access 16 Burst Lengths Supported 2, 4, 8 0E 17 Number of Banks on SDRAM Device 4Banks ,2 0C CAS Latency 14 Rev 1.0 July 2007

16 Byte Description Entry (Version) Value 19 0 tck 01 CS Latency 20 WE Latency 1 tck SDRAM Module Attributes PLL/Registered/Diff. 26 Clock 22 SDRAM Device Attributes General C1 23 Minimum Clock Cycle Time at Reduced CAS Latency, X ns Maximum Data Access Time(Tac) from Clock at CL X ns Minimum Clock Cycle Time at X Maximum Data Access Time(Tac) from Clock at CL X Minimum Row Precharge Time, trp 15ns 3C 28 Minimum Row Active to Row Active Delay, trrd 10ns ns 3C Minimum RAS to CAS Delay, trcd 30 Minimum Active to Precharge Time, tras 40ns Module Rank Density 256MB Address and Command Setup Time, tisb 0.6ns Address and Command Hold Time, tihb 0.6ns Data Input Setup Time, tdsb 0.40ns Data Input Hold Time, tdhb 0.40ns Superset Information Superset Information Superset Information Superset Information Superset Information Minimum Active Auto Refresh Time, trc 55ns Minimum Auto Refresh to Active Command Period, trfc 70ns SDRAM Device Max Cycle Time, tck max 10ns SDRAM Device DQS-DQ Skew for DQS and associated DQ 0.40ns 28 signals, tdqsq max 45 SDRAM Device Read Data Hold Skew Factor, tqhs 0.50ns PLL Relock Time 100μs DDR SDRAM DIMM Height 1.25inch Reserved SPD Revision Revision Rev 1.0 July 2007

17 Byte Description Entry (Version) Value 63 Checksum For Bytes Manufacturer s JEDEC ID Code Manufacturing Location Module Part Number (ASCII) Variable Data Module Revision Code Module Manufacturing Data Module Serial Number Manufacturer-Specific Data (RSVD) Open for customer use Rev 1.0 July 2007