SP001GBLRU800S pin DDR2 SDRAM Unbuffered Module

Transcription

1 240pin DDR2 SDRAM Unbuffered Module SILICON POWER Computer and Communications, INC. Corporate Office 7F, No. 106, Zhou-Z Street NeiHu Dist., Taipei 114, Taiwan, R.O.C. This document is a general product description and is subject to change without notice Rev 1.0 April 2007

2 Revision History Revision No. Date Remarks /04/12 First issue Table of contents 1. Description Features Module Specification Simplified Mechanical Drawing with Keying Positions outs Description Block Diagram Absolute Maximum DC Ratings AC & DC Operating Conditions ODT DC Electrical Characteristics Input DC Logic Level Input AC Logic Level AC Input Test Conditions IDD Specifications and Conditions Timing Parameters & Specifications Command Truth Table Serial Presence-Detect Matrix Rev 1.0 April 2007

3 1. Description The is a 128M x 8bits Double Data Rate SDRAM high-density for DDR The consists of 8pcs CMOS 128Mx8 bits Double Data Rate SDRAMs in 60 ball FBGA packages, and a 2048 bits serial EEPROM on a 240-pin printed circuit board. The is a Dual In-Line Memory Module and is intended for mounting into 240-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. 2. Features Fast data transfer rates: PC pin, unbuffered dual in-line memory module VDD = VDDQ = +1.8V, VDDSPD = +1.7V to +3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture DLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrent operation Programmable CAS# latency (CL) Posted CAS# additive latency (AL) WRITE latency = READ latency - 1 tck Programmable burst lengths: 4 or 8 Adjustable data-output drive strength 64ms, 8,192-cycle refresh On-die termination (ODT) 60ball FBGA Leaded & Pb-Free (RoHS compliant) package 2 Rev 1.0 April 2007

4 3. Module Specification Item Specification Capacity 1024MByte Physical Bank(s) 1 Module Organization 128M x 64bit Module Type Unbuffered Non ECC Speed Grade PC2-6400/CL=6,tRCD=6,tRP=6 (DDR2 800) Voltage Interface SSTL_18 Power Supply Voltage 1.8V±0.1V Burst Lengths 4 or 8 DRAM Organization 128M x 8bit DDR2 SDRAM PCB Layer 6Layers Contact Tab 240 pin GOLD Flash Plating Serial PD Support 4. Simplified Mechanical Drawing with Keying Positions Notes:1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 3 Rev 1.0 April 2007

5 5. outs 1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDDQ 211 DM5 2 VSS 32 VSS 62 VDDQ 92 /DQS5 122 DQ4 152 DQ A3 212 NC 3 DQ0 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ A1 213 VSS 4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 DQ46 5 VSS 35 VSS 65 VSS 95 DQ DM0 155 DM3 185 CK0 215 DQ47 6 /DQS0 36 /DQS3 66 VSS 96 DQ NC 156 NC 186 /CK0 216 VSS 7 DQS0 37 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52 8 VSS 38 VSS 68 NC 98 DQ DQ6 158 DQ A0 218 DQ53 9 DQ2 39 DQ26 69 VDD 99 DQ DQ7 159 DQ VDD 219 VSS 10 DQ3 40 DQ27 70 A10/AP 100 VSS 130 VSS 160 VSS 190 BA1 220 CK2 11 VSS 41 VSS 71 BA0 101 SA2 131 DQ NC 191 VDDQ 221 /CK2 12 DQ8 42 NC 72 VDDQ 102 NC 132 DQ NC 192 /RAS 222 VSS 13 DQ9 43 NC 73 /WE 103 VSS 133 VSS 163 VSS 193 /S0 223 DM6 14 VSS 44 VSS 74 /CAS 104 /DQS6 134 DM1 164 NC 194 VDDQ 224 NC 15 /DQS1 45 NC 75 VDDQ 105 DQS6 135 NC 165 NC 195 ODT0 225 VSS 16 DQS1 46 NC 76 /S1 106 VSS 136 VSS 166 VSS 196 A DQ54 17 VSS 47 VSS 77 ODT1 107 DQ CK1 167 NC 197 VDD 227 DQ55 18 NC 48 NC 78 VDDQ 108 DQ /CK1 168 NC 198 VSS 228 VSS 19 NC 49 NC 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ DQ60 20 VSS 50 VSS 80 DQ DQ DQ VDDQ 200 DQ DQ61 21 DQ10 51 VDDQ 81 DQ DQ DQ CKE1 201 VSS 231 VSS 22 DQ11 52 CKE0 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4 232 DM7 23 VSS 53 VDD 83 /DQS4 113 /DQS7 143 DQ A NC 233 NC 24 DQ16 54 NC 84 DQS4 114 DQS7 144 DQ A VSS 234 VSS 25 DQ17 55 NC 85 VSS 115 VSS 145 VSS 175 VDDQ 205 DQ DQ62 26 VSS 56 VDDQ 86 DQ DQ DM2 176 A DQ DQ63 27 /DQS2 57 A11 87 DQ DQ NC 177 A9 207 VSS 237 VSS 28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ VDDSPD 29 VSS 59 VDD 89 DQ SDA 149 DQ A8 209 DQ SA0 30 DQ18 60 A5 90 DQ SCL 150 DQ A6 210 VSS 240 SA1 4 Rev 1.0 April 2007

6 6. Description SYMBOL TYPE DESCRIPTION CK, /CK CKE Input Input /S0 Input Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edgeof CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. Chip Select: All commands are masked when /CS is registered HIGH. /CS provides for external Rank selection on systems with multiple Ranks. /CS is considered part of the command code. ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT. /RAS, /CAS, /WE Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. DM (UDM), (LDM) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command. BA0 - BA2 Input Bank Address Inputs: BA0 and BA1 for 256 and 512Mb, BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. A0 - A15 Input Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands. DQ Input/Output Data Input/ Output: Bi-directional data bus. DQS, (/DQS) (UDQS),(/UDQS) (LDQS),(/LDQS) (RDQS),(/RDQS) NC Input/Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals. No Connect: No internal electrical connection is present. V DDQ Supply DQ Power Supply: 1.8V +/- 0.1V V SSQ Supply DQ Ground V DDL Supply DLL Power Supply: 1 8V +/- 0.1V V SSDL Supply DLL Ground VDD Supply Power Supply: 1 8V +/- 0.1V VSS Supply Ground VREF Supply Reference voltage 5 Rev 1.0 April 2007

7 7. Block Diagram 6 Rev 1.0 April 2007

8 8. Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss V ~ 2.3 V V 1 VDDQ Voltage on VDDQ pin relative to Vss V ~ 2.3 V V 1 VDDL Voltage on VDDL pin relative to Vss V ~ 2.3 V V 1 V IN, V OUT Voltage on any pin relative to Vss V ~ 2.3 V V 1 TSTG Storage Temperature -55 to +100 C 1.2 NOTE:1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 9. AC & DC Operating Conditions Symbol Parameter Rating Min. Typ. Max. Units VDD Supply Voltage V 1 Notes VDDL Supply Voltage for DLL V 5 VDDQ Supply Voltage for Output V 1, 5 VDDspd Supply Voltage for EEPROM V VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V 2, 3 VTT Termination Voltage VREF-0.04 VREF VREF+0.04 V 4 NOTE:1.There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 2.The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically, the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3.Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 4.VTT of transmitting device must track VREF of receiving device. 5.VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together 7 Rev 1.0 April 2007

9 10. ODT DC Electrical Characteristics Parameter/Condition Symbol Min Nom Max Units Notes Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt1(eff) ohm 1 Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt2(eff) ohm 1 Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm Rtt3(eff) ohm 1 Deviation of VM with respect to VDDQ/2 delta VM % 1 NOTE: 1. Test condition for Rtt measurements Measurement Definition for Rtt(eff) Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively. VIH(AC), and VDDQ values defined in SSTL_18. Rtt(eff) = Measurement Definition for VM Measure voltage (VM) at test pin (midpoint) with no load. 11. Input DC Logic Level VIH(AC) - VIL(AC) I(VIH(AC))- I(VIL(AC)) 2 VM Δ VM = 1 100% VDDQ Symbol Parameter Min Max Units Notes VIH(dc) dc input logic high VREF VDDQ V VIL(dc) dc input logic low -0.3 VREF V 12. Input AC Logic Level Symbol Parameter Min Max Units Notes VIH (ac) ac input logic high VREF V VIL (ac) ac input logic low - VREF V 8 Rev 1.0 April 2007

10 13. AC Input Test Conditions Symbol Condition Value Units Notes Vref Input reference voltage 0.5 * VDDQ V 1 SWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2, 3 NOTE: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2.The input signal minimum slew rate is to be maintained over the range from VIL(dc) max to VIH(ac) min for rising edges and the range from VIH(dc) min t VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. 9 Rev 1.0 April 2007

11 14. IDD Specifications and Conditions Values shown for DDR2 SDRAM components only Parameter/Condition Symbol PC Units Operating one bank active-precharge current: tck = tck (IDD), trc = trc (IDD), tras = tras MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. IDD ma Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tck = tck (IDD), trc = trc (IDD), tras = tras MIN (IDD); trcd = trcd (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Precharge power-down current: All device banks idle; tck = tck (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge quiet standby current: All device banks idle; tck = tck (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge standby current: All device banks idle; tck = tck (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. IDD ma IDD2P 128 ma IDD2Q 720 ma IDD2N 800 ma Active power-down current: All device banks open; tck = Fast PDN Exit MR[12] =0 560 ma tck (IDD); CKE is LOW; Other control and address bus IDD3P inputs are STABLE; Data bus inputs are FLOATING. Slow PDN Exit MR[12] =1 192 ma Active standby current: All device banks open; tck = tck (IDD)); tras = tras MAX (IDD), trp = trp (IDD), CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst write current: All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tck = tck (IDD), tras = tras MAX (IDD), trp = trp (IDD), CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst read current: All device banks open, Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tck = tck (IDD), tras = tras MAX (IDD), trp = trp (IDD), CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Burst refresh current: tck = tck (IDD); Refresh command at every trfc (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Others control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Self refresh current: CK and CK# at 0V; CKE = 0.2V; Others control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating device bank interleave read current: All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = trcd (IDD)-1 x tck (IDD), tck = tck (IDD), trc = trc (IDD), trrd = trrd (IDD), trcd = trdd (IDD),CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are STABLE during DESELECT; Data bus inputs are SWITCHING, See IDD7 Conditions for detail. IDD3N 400 ma IDD4W 2600 ma IDD4R 2040 ma IDD ma IDD6 80 ma IDD ma 10 Rev 1.0 April 2007

12 15. Timing Parameters & Specifications (These AC characteristics were tested on the Component) Parameter Symbol Min Max Unit DQ output access time from CK & /CK tac ps DQS output access time from CK & /CK tdqsck ps CK high-level width tch tck CK low-level width tcl tck CK half period thp min(tcl/h) X ps Clock cycle time, CL=x tck ps DQ and DM input hold time tdh ps DQ and DM input setup time tds 50 - ps Control & Address input pulse width for each input tipw tck DQ and DM input pulse width for each input tdipw tck Data-out high-impedance time from CK/CK thz tac min tac max ps DQS low-impedance time from CK/CK tlz(dqs) tac min tac max ps DQS-DQ skew for DQS and associated DQ signals tdqsq ps DQ hold skew factor tqhs ps DQ/DQS output hold time from DQS tqh thp - tqhs - ps Write command to first DQS latching transition tdqss WL-0.25tCK WL+0.25tCK tck DQS input high pulse width tdqsh tck DQS input low pulse width tdqsl tck DQS falling edge to CK setup time tdss tck DQS falling edge hold time from CK tdsh tck Mode register set command cycle time tmrd 2 - tck Write postamble twpst tck Write DQS preamble Hold time twpreh tck Address and control input hold time tih ps Address and control input setup time tis ps Read preamble trpre tck Read postamble trpst tck Active to active command period for 1 KB page size products trrd ns /CAS to /CAS command delay tccd 2 - tck Write recovery time twr 15 - ns Auto precharge write recovery + precharge time tdal twr+trp - tck Internal write to read command delay twtr ns Internal read to precharge command delay trtp ns Exit self refresh to a non-read command txsnr trfc ns 11 Rev 1.0 April 2007

13 Parameter Symbol Min Max Unit Exit self refresh to a read command txsrd tck Exit precharge power down to any non-read command txp 2 - tck Exit active power down to read command txard 2 - tck Exit active power down to read command (Slow exit, Lower power) txards 7 - AL - tck CKE minimum pulse width (high and low pulse width) tcke 3 - tck OCD drive mode output delay toit 0 12 ns Minimum time clocks remains ON after CKE asynchronously drops tdelay tis+tck+tih ns LOW 16. Command Truth Table Command Previous Cycle CKE Current Cycle CS RAS CAS WE BA0,BA1 A10 A15-A11,A9-A0 (Extended) Mode Register Set H H L L L L BA OP Code 1,2 Auto-Refresh H H L L L H X X X 1 Self Refresh Entry H L L L L H X X X 1 Note Self Refresh Exit L H H X X X L H H H X X X 1 Single Bank Precharge H H L L H L BA L X 1,2 Precharge all Banks H H L L H L X H X 1 Bank Activate H H L L H H BA Row Address 1,2 Write H H L H L L BA L Column Address 1,2,3 Write with Auto Precharge H H L H L L BA H Column Address 1,2,3 Read H H L H L H BA L Column Address 1,2,3 Read with Auto-Precharge H H L H L H BA H Column Address 1,2,3 No Operation H X L H H H X X X 1 Device Deselect H X H X X X X X X 1 Power Down Entry H L Power Down Exit L H H X X X L H H H H X X X L H H H X X X 1,4 X X X 1,4 (H=Logic High Level, L=Logic Low Level, X=Don t Care, OP Code=Operand Code) NOTE:1. All DDR2 SDRAM commands are defined by states of CS#, WE#, RAS#, CAS#, and CKE at the rising edge of the clock. 2. Bank addresses (BA0, BA1) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. 3. Burst reads or writes at BL = 4 cannot be terminated. See sections Reads interrupted by a Read and Writes interrupted by a Write. 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements. 12 Rev 1.0 April 2007

14 17. Serial Presence-Detect Matrix Byte Description Entry (Version) Value 00 ber of SPD Bytes Total ber of Bytes in SPD Device Fundamental Memory Type DDR2 SDRAM ber of Row Addresses on Assembly 14 0E 04 ber of Column Addresses on Assembly 10 0A 05 ber of DIMM Ranks 1Rank, 30mm Module Data Width Reserved Module Voltage Interface Levels SSTL SDRAM Cycle Time, tck (CL = Maximum value, see byte 18) 2.5ns SDRAM Access from Clock,tAC (CL = Maximum value, see byte 18) 0.40ns Module Configuration Type Non-ECC Refresh Rate/Type 7.8μs SDRAM Device Width (Primary SDRAM) Error-checking SDRAM Data Width None Reserved Burst Lengths Supported 4, 8 0C 17 ber of Banks on SDRAM Device CAS Latencies Supported 6, 5, DIMM Mechanical Characteristics X DDR2 DIMM Type UDIMM SDRAM Module Attributes Standard DIMM SDRAM Device Attributes General SDRAM Cycle Time, tck, Max. CL ns SDRAM Access from CK, tac, Max. CL ns SDRAM Cycle Time, tck, Max. CL ns 3D 26 SDRAM Access from CK, tac, Max. CL ns Minimum Row Precharge Time, trp 15ns 3C 28 Minimum Row Active to Row Active, trrd 7.5ns 1E 29 Minimum RAS# to CAS# Delay, trcd 15ns 3C 30 Minimum RAS# Pulse Width, tras 60ns 3C 31 Module Rank Density 1024MB Address and Command Setup Time, tisb 0.175ns Address and Command Hold Time, tihb 0.25ns Rev 1.0 April 2007

15 Byte Description Entry (Version) Value 34 Data/ Data Mask Input Setup Time, tdsb 0.05ns Data/ Data Mask Input Hold Time, tdhb 0.125ns Write Recovery Time, twr 15ns 3C 37 Write to Read CMD Delay, twtr 7.5ns 1E 38 Read to Precharge CMD Delay, trtp 7.5ns 1E 39 Mem Analysis Probe Extension for bytes 41 and Min Active Auto Refresh Time, trc 57.5ns Minimum Auto Refresh to Active / auto refresh command period, trfc 105ns SDRAM Device Max Cycle Time, tckmax 8ns SDRAM Device Max DQS-DQ Skew Time, tdqsq 0.20ns SDRAM Device Max Read Data Hold Skew Factor, tqhs 0.30ns 1E 46 PLL Relock Time Optional features, not supported SPD Revision Revision Checksum For Bytes 0 62 FC Manufacturer s JEDEC ID Code Manufacturing Location Module Part ber (ASCII) Variable Data Module Revision Code Module Manufacturing Data Module Serial ber Manufacturer-Specific Data (RSVD) Open for customer use Rev 1.0 April 2007