INTEGRATED CIRCUITS. P82B96 Dual bi-directional bus buffer. Product data Supersedes data of 2003 Feb Apr 02. Philips Semiconductors

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1 NTEGRATED CRCUTS Supersedes data of 2003 Feb Apr 02 Philips Semiconductors

2 FEATURES Dual nterface handles both SCL and 2 C signals Bi-directional data transfer Splits 2 C signal into forward/reverse Tx, Ty, Rx and Ry signals Low power supply current Wide supply voltage range ( 2 C logic levels at Sx Sy independent of C supply voltage) Supply voltage range of 2 to ma sink capability for driving low impedance buses Clock speeds to 400 khz on short buses or where delays permit ESD protection exceeds 3500 HBM per JESD22-A114 and 1000 CDM per JESD22-C101 Latch-up free (bipolar process with no latching structures) TYPCAL APPLCATONS nterface between 2 C buses operating at different logic levels (e.g., 5 and 3 or 15 ) nterface between 2 C and SMB (350 A) bus standard. Simple conversion of 2 C or SCL signals to multi-drop differential bus hardware, e.g., via compatible PCA82C250. nterfaces with Opto-couplers to provide Opto isolation between 2 C bus nodes. DESCRPTON The is a bipolar C that creates a non-latching, bi-directional, logic interface between the normal 2 C bus and a range of other bus configurations. t can interface 2 C bus logic signals to similar buses having different voltage and current levels. For example it can interface to the 350 A SMB bus, to 3.3 logic devices, and to 15 levels and/or low impedance lines to improve noise immunity on longer bus lengths. t achieves this interface without any restrictions on the normal 2 C protocols or clock speed. The C adds minimal loading to the 2 C node, and loadings of the new bus or remote 2 C nodes are not transmitted or transformed to the local node. Restrictions on the number of 2 C devices in a system, or the physical separation between them, are virtually eliminated. Transmitting /SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be directly connected, without causing latching, to provide an alternative bi-directional signal line with 2 C properties. PN CONFGURATONS 8-pin dual in-line or SO PNNNG Sx Rx Tx GND CC Sy Ry Ty SU01011 SYMBOL ÁÁÁ PN DESCRPTON Sx ÁÁÁ 1 2 C Bus ( or SCL) Rx ÁÁÁ 2 Receive signal Tx 3 Transmit signal Á GND 4 Negative Supply ÁÁ Ty 5 Transmit signal Ry ÁÁÁ 6 Receive signal Sy ÁÁÁ 7 2 C Bus ( or SCL) CC ÁÁÁ 8 Positive supply ORDERNG NFORMATON PACKAGES TEMPERATURE RANGE ORDER CODE TOPSDE MARK DRAWNG NUMBER 8-pin plastic dual n-line package -40 to +85 C PN PN SOT pin plastic small outline package -40 to +85 C TD T SOT96-1 NOTES: 1. Standard packing quantities and other packaging data are available at Apr 02 2

3 BLOCK DAGRAM + CC (2-15 ) 8 Sx () 1 3 Tx (TxD, ) 2 Rx (RxD, ) Sy (SCL) 7 5 Ty (TxD, SCL) 6 Ry (RxD, SCL) 4 GND SU01012 FUNCTONAL DESCRPTON The has two identical buffers allowing buffering of both of the 2 C ( and SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the 2 C interface pin which drives the buffered bus, and a reverse signal path from the buffered bus input to drive the 2 C bus interface. Thus these paths are: 1. Sense the voltage state of the 2 C pin Sx (or Sy) and transmit this state to the pin Tx (Ty resp.), and 2. Sense the state of the pin Rx (Ry) and pull the 2 C pin low whenever Rx (Ry) is low. The rest of this discussion will address only the x side of the buffer: the y side is identical. The 2 C pin (Sx) is designed to interface with a normal 2 C bus. The logic threshold voltage levels on the 2 C bus are independent of the C supply CC The maximum 2 C bus supply voltage is 15 and the guaranteed static sink current is 3 ma. The logic level of Rx is determined from the power supply voltage CC of the chip. Logic LOW is below 42 % of CC and logic HGH is above 58 % of CC : with a typical switching threshold of half CC. Tx is an open collector output without ESD protection diodes to CC. t may be connected via a pull-up resistor to a supply voltage in excess of CC, as long as the 15 rating is not exceeded. t has a larger current sinking capability than a normal 2 C device, being able to sink a static current of greater than 30 ma, and typical 100 ma dynamic pull-down capability as well. A logic LOW is only transmitted to Tx when the voltage at the 2 C pin (Sx) is below 0.6. A logic LOW at Rx will cause the 2 C bus (Sx) to be pulled to a logic LOW level in accordance with 2 C requirements (max. 1.5 in 5 applications) but not low enough to be looped back to the Tx output and cause the buffer to latch low. The minimum LOW level this chip can achieve on the 2 C bus by a LOW at Rx is typically 0.8. f the supply voltage cc fails then neither the 2 C nor the Tx output will be held low. Their open collector configuration allows them to be pulled up to the rated maximum of 15 even without CC present. The input configuration on Sx and Rx also present no loading of external signals even when CC is not present. The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 7 pf for all bus voltages and supply voltages including CC = Apr 02 3

4 MAXMUM RATNGS n accordance with the Absolute Maximum Rating System (EC 134). oltages with respect to pin GND (pin 4). SYMBOL PARAMETER MN. Á MAX. UNT CC to GND Supply voltage range CC -0.3 ÁÁ bus oltage range on 2 C Bus, or SCL Tx oltage range on buffered output oltage range on receive input Á +18 Á Á Á Rx ÁÁÁ Á Á DC current (any pin) 250 ma R tot ÁÁÁ Á Á Power dissipation 300 mw T stg Á Storage temperature range C T amb Operating ambient temperature range -40 Á +85 Á C CHARACTERSTCS At T amb = 25 C; oltages are specified with respect to GND with CC = 5 unless otherwise stated. SYMBOL PARAMETER MN. TYP. MAX.Á UNT Power Supply ÁÁÁ Supply voltage (operating) Á CC CC Supply current, buses HGH Á ma CC Supply current at CC = 15, buses HGH Á ma CC Additional supply current per Tx or Ty LOW Á ma Bus pull-up (load) voltages and currents Sx, Sy Maximum input/output voltage level Á Open collector ÁÁÁ 2 C bus and Rx, Ry = HGH 15 ÁÁ ÁÁ Sx, Sy Static output loading on 2 C bus 0.2 ÁÁÁ Sx, Sy = 1.2 Rx, Ry 3 Á ma ÁÁ = LOW Sx, Sy Dynamic output sink capability on 2 C bus 7 18 ÁÁ ÁÁÁ Sx, Sy > 2 Rx, Ry ma Á = LOW Sx, Sy Á Leakage current on ÁÁÁ 2 C bus Sx, Sy = 5, and Á 1 A Á Rx, Ry = HGH Sx, Sy Leakage current on 2 C bus Sx, Sy = 15, and 1 Á A Á ÁÁÁ Rx, Ry = HGH ÁÁ Tx, Ty Maximum output voltage level Á 15 Á Open collector Tx, Ty Static output loading on buffered bus ÁÁ ÁÁÁ Tx, Ty = ma Á Sx, Sy = LOW on 2 C bus = 0.4 Tx, Ty Dynamic output sink capability, 60 ÁÁÁ buffered bus: Tx, Ty > Á ma Á Sx, Sy = LOW on 2 C bus = 0.4 Tx, Ty Leakage current on buffered bus 1 A Tx, Ty = CC = 15, and ÁÁ ÁÁÁ Sx, Sy = HGH ÁÁ 2003 Apr 02 4

5 SYMBOL PARAMETER MN. TYP. MAX. UNT nput Currents Sx, Sy nput current from 2 C bus, bus LOW Rx, Ry = HGH -1 Á A Á Rx, Ry nput current from buffered bus, bus LOW -1 Á A Rx, Ry = 0.4 Rx, Ry Leakage current on buffered bus input 1 Rx, Ry = CC A Á nput Thresholds ÁÁÁ Output logic level LOW, on normal 2 C bus Á Sx, Sy Sx, Sy = 3 ma Sx, Sy Output logic level LOW, on normal 2 C bus 750 Sx, Sy = 0.2 ma m Á Sx, Sy nput logic level LOW threshold ÁÁ On normal ÁÁÁ 2 C bus m Á d Sx /dt, d Sy /dt Temperature coefficient of thresholds -2 m/k Rx, Ry nput logic HGH level 0.58 Fraction of applied CC Á Rx, Ry nput threshold 0.5 ÁÁ Fraction of applied ÁÁÁ CC Á Rx, Ry nput logic LOW level Fraction of applied CC 0.42 ÁÁ Bus Release on CC Failure Sx, Sy, Tx, Ty CC voltage at which all buses are guaranteed to be released 1 Á d/dt Temperature coefficient of guaranteed release voltage -4 Á m/k Buffer response time T fall delay Buffer time delay on FALLNG input between Sx = input 100 Á ns Sx to Tx switching threshold: and Sy to Ty Tx output falling 50%. R Tx pull up = 160, no capacitive load, CC = 5 ÁÁ T rise delay Buffer time delay on RSNG input between Sx = input 100 ÁÁ Sx to Tx switching threshold, and Sy to Ty Tx output reaching 50%. R Tx pull up = 160, no capacitive load, CC ns Á = 5 T fall delay Buffer time delay on FALLNG input between Rx = input Rx to Sx switching threshold, and Sx output falling 50%. 300 Á ns Á Ry to Sy R Sx pull up = 1600, no capacitive load, CC = 5 T rise delay Buffer time delay on RSNG input between Rx to Sx Ry to Rx = input switching threshold, and Sx output reaching 50%. 300 Á ns Á Sy R Sx pull up = 1600, no capacitive load, CC = 5 nput capacitance Cin Effective input capacitance of any signal pin measured by Á 7 pf Á incremental bus rise times 2003 Apr 02 5

6 TYPCAL APPLCATONS See AN460 and AN255 for more application detail. + CC (2-15 ) +5 2 C Tx () R1 (NEW LEELS) 1/2 PB2B96 Rx () SU01013 Figure 1. nterfacing an 2 C type of bus with different logic levels. R2 + CC + CC1 R4 R5 R1 +5 Rx () R3 2C 2 C 1/2 Tx () SU01014 Figure 2. Galvanic isolation of 2 C nodes via opto-couplers 2003 Apr 02 6

7 MAN ENCLOSURE REMOTE CONTROL ENCLOSURE LONG CABLES SCL SCL SU01708 Figure 3. Long distance 2 C communications TWSTED-PAR TELEPHONE WRES, USB, OR FLAT RBBON CABLES. UP TO 15 LOGC LEELS, NCLUDE CC AND GND. SCL /SCL /SCL /SCL NO LMT TO THE NUMBER OF CONNECTED BUS DECES. su01709 Figure 4. 2 C multi-point applications ch1: freq = 624 khz ch1: freq = 624 khz Tx 10 Rx Sx Sx 5 CH1!2.00 = AG CH2!2.00 = BWL MTB 200ns dvch1+ Horiz: 200ns/div. ertl 2/div. Figure 5. Propagation Sx to Tx Sx pull-up to 5, Tx pull-up to CC = 10 0 SU01069 CH1!2.00 = AG CH2!2.00 = BWL MTB 200ns dvch1+ Horiz: 200ns/div. ertl 2/div. Figure 6. Propagation Rx to Sx Sx pull-up to 5, Rx pull-up to CC = 10 SU Apr 02 7

8 SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT Apr 02 8

9 DP8: plastic dual in-line package; 8 leads (300 mil) SOT Apr 02 9

10 RESON HSTORY Rev Date Description _ ( ); ECN Dated 28 February 2003; supersedes data of 2003 Jan 22 ( ) Modifications: Additional pin capacitance added. _ ( ); ECN of 22 January 2003; supersedes data of 2001 Mar 06 ( ) _ ( ); ECN of 2001 Mar Apr 02 10

11 Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the nternet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (EC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the productsincluding circuits, standard cells, and/or softwaredescribed or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit Fax: For sales offices addresses send to: sales.addresses@ Koninklijke Philips Electronics N All rights reserved. Printed in U.S.A. Date of release: Document order number: Philips Semiconductors 2003 Apr 02 11