DDR2 SDRAM VLP RDIMM MT36HVS51272PZ 4GB MT36HVS1G72PZ 8GB. Features. 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM.

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1 DDR2 SDRAM VLP RDIMM MT36HVS51272PZ 4GB MT36HVS1G72PZ 8GB 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM Features Features 240-pin, very low-profile, registered dual in-line memory module (VLP RDIMM), ATCA form factor Fast data transfer rates: PC2-6400, PC2-5300, PC2-4200, or PC GB (512 Meg x 72), 8GB (1 Gig x 72) Supports ECC error detection and correction Dual-rank using 2Gb or 4Gb TwinDie devices V DD = V D = 1.8V V DDSPD = V JEDEC-standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (S, S#) option 4n-bit prefetch architecture Multiple internal device banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency - 1 t CK Programmable burst lengths (BL): 4 or 8 Adjustable data-output drive strength 64ms, 8192-cycle refresh On-die termination (ODT) Serial presence-detect (SPD) with EEPROM Halogen-free Gold edge contacts Figure 1: 240-Pin RDIMM (ATCA Form Factor) Module height: 17.9mm (0.7in) Options Marking Parity P Operating temperature Commercial (0 C T A +70 C) None Industrial ( 40 C T A +85 C) 1 I Package 240-pin DIMM (halogen-free) Z Frequency/CL 2 CL = 5 (DDR2-800) -80E CL = 6 (DDR2-800) -800 CL = 6 (DDR2-667) -667 Notes: 1. Contact Micron for industrial temperature module offerings. 2. CL = CAS (READ) latency; registered mode will add one clock cycle to CL. Table 1: Key Timing Parameters Speed Grade Industry Nomenclature Data Rate (MT/s) CL = 6 CL = 5 CL = 4 CL = 3-80E PC PC PC E PC E PC t RCD (ns) t RP (ns) t RC (ns) 1 Products and specifications discussed herein are subject to change by Micron without notice.

2 Features Table 2: Addressing Parameter 4GB 8GB Refresh count 8K 8K Row address 16K A[13:0] 32K A[14:0] Device bank address 8 BA[2:0] 8 BA[2:0] Device configuration 2Gb TwinDie (512 Meg x 4) 4Gb TwinDie (1 Gig x 4) Column address 2K A[11, 9:0] 2K A[11, 9:0] Module rank address 2 S#[1:0] 2 S#[1:0] Table 3: Part Numbers and Timing Parameters 4GB Base device: MT47H512M4, 1 2Gb TwinDie DDR2 SDRAM Part Number 2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT36HVS51272P(I)Z-80E 4GB 512 Meg x GB/s 2.5ns/800 MT/s MT36HVS51272P(I)Z-800 4GB 512 Meg x GB/s 2.5ns/800 MT/s MT36HVS51272P(I)Z-667 4GB 512 Meg x GB/s 3.0ns/667 MT/s Table 4: Part Numbers and Timing Parameters 8GB Base device: MT47H1G4, 1 4Gb TwinDie DDR2 SDRAM Part Number 2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT36HVS1G72P(I)Z-80E 8GB 1 Gig x GB/s 2.5ns/800 MT/s MT36HVS1G72P(I)Z-800 8GB 1 Gig x GB/s 2.5ns/800 MT/s MT36HVS1G72P(I)Z-667 8GB 1 Gig x GB/s 3.0ns/667 MT/s Notes: 1. Data sheets for the base device can be found on Micron s web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT36HVS51272PZ-80EM1. 2

3 Pin Assignments Pin Assignments Table 5: Pin Assignments 240-Pin VLP RDIMM Front 240-Pin VLP RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 V REF A4 91 V SS 121 V SS 151 V SS 181 V D 211 S14 2 V SS 32 V SS 62 V D 92 S5# A3 212 S14# A2 93 S A1 213 V SS V DD 94 V SS 124 V SS 154 V SS 184 V DD V SS 35 V SS 65 V SS S9 155 S CK S0# 36 S3# 66 V SS S9# 156 S12# 186 CK0# 216 V SS 7 S0 37 S3 67 V DD 97 V SS 127 V SS 157 V SS 187 V DD V SS 38 V SS 68 Par_In A V DD V DD 219 V SS A V SS 130 V SS 160 V SS 190 BA1 220 NC 11 V SS 41 V SS 71 BA0 101 SA CB4 191 V D 221 NC CB0 72 V D 102 NC CB5 192 RAS# 222 V SS CB1 73 WE# 103 V SS 133 V SS 163 V SS 193 S0# 223 S15 14 V SS 44 V SS 74 CAS# 104 S6# 134 S S V D 224 S15# 15 S1# 45 S8# 75 V D 105 S6 135 S10# 165 S17# 195 ODT0 225 V SS 16 S1 46 S8 76 S1# 106 V SS 136 V SS 166 V SS 196 A V SS 47 V SS 77 ODT NC 167 CB6 197 V DD RESET# 48 CB2 78 V D NC 168 CB7 198 V SS 228 V SS 19 NC 49 CB3 79 V SS 109 V SS 139 V SS 169 V SS V SS 50 V SS V D V D CKE1 201 V SS 231 V SS CKE0 82 V SS 112 V SS 142 V SS 172 V DD 202 S S16 23 V SS 53 V DD 83 S4# 113 S7# A S13# 233 S16# BA2 84 S4 114 S A V SS 234 V SS Err_Out# 85 V SS 115 V SS 145 V SS 175 V D V SS 56 V D S A S2# 57 A S11# 177 A9 207 V SS 237 V SS 28 S2 58 A7 88 V SS 118 V SS 148 V SS 178 V DD V DDSPD 29 V SS 59 V DD SDA A SA A SCL A6 210 V SS 240 SA1 Note: 1. A15 connected for parity. 3

4 Pin Descriptions Table 6: Pin Descriptions Symbol Type Description The pin description table below is a comprehensive list of all possible pins for all DDR2 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. CKx, CK#x Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DDR2 SDRAM. DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the and S pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT is only applied to the following pins:, S, S#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and are High-Z. S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I 2 C bus. SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the SPD EEPROM on the I 2 C bus. CBx I/O Check bits. Used for system error detection and correction. x I/O Data input/output: Bidirectional data bus. Sx, S#x I/O 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM Pin Descriptions Data strobe: Travels with the and is used to capture at the DRAM or the controller. Output with read data; input with write data for source synchronous operation. S# is only used when differential data strobe mode is enabled via the LOAD MODE command. 4

5 Pin Descriptions Table 6: Pin Descriptions (Continued) Symbol Type Description SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on the I 2 C bus. RSx, RS#x Err_Out# Output Output (open drain) Redundant data strobe (x8 devices only): RS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When RS is enabled, RS is output with read data only and is ignored during write data. When RS is disabled, RS becomes data mask (see DMx). RS# is only used when RS is enabled and differential data strobe mode is enabled. Parity error output: Parity error found on the command and address bus. V DD /V D Supply Power supply: 1.8V ±0.1V. The component V DD and V D are connected to the module V DD. V DDSPD Supply SPD EEPROM power supply: V. V REF Supply Reference voltage: V DD /2. V SS Supply Ground. NC No connect: These pins are not connected on the module. NF No function: These pins are connected within the module, but provide no functionality. NU Not used: These pins are not used in specific module configurations/operations. RFU Reserved for future use. 5

6 Functional Block Diagram 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM Functional Block Diagram Figure 2: Functional Block Diagram V SS RS0# RS1# S0 S0# S1 S1# S2 S2# S3 S3# S4 S4# S5 S5# S6 S6# DM CS# S S# U1b DM CS# S S# U2b DM CS# S S# U3b DM CS# S S# U4b DM CS# S S# U8b DM CS# S S# U9b DM CS# S S# U10b DM CS# S S# U1t DM CS# S S# U2t DM CS# S S# U3t DM CS# S S# U4t DM CS# S S# U8t DM CS# S S# U9t DM CS# S S# U10t S9 S9# S10 S10# S11 S11# S12 S12# S13 S13# S14 S14# S15 S15# DM CS# S S# U22b DM CS# S S# U21b DM CS# S S# U20b DM CS# S S# U19b DM CS# S S# U16b DM CS# S S# U15b DM CS# S S# U14b DM CS# S S# U22t DM CS# S S# U21t DM CS# S S# U20t DM CS# S S# U19t DM CS# S S# U16t DM CS# S S# U15t DM CS# S S# U14t S0# S1# BA[2:0] A[15:0] RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 Par_In RESET# CK0 CK0# V DD /V D V SS RESET# SCL U12 SPD EEPROM WP U7, U17 R e g i s t e r s A0 PLL A1 SA0 SA1 A2 SA2 RS0#: Rank 0 RS1#: Rank 1 RBA[2:0]: DDR2 SDRAM RA[14/13:0]: DDR2 SDRAM RRAS#: DDR2 SDRAM RCAS#: DDR2 SDRAM RWE#: DDR2 SDRAM RCKE0: Rank 0 RCKE1: Rank 1 RODT0: Rank 0 RODT1: Rank 1 Err_Out# Rank 0 = U1b U5b, U8b U11b, U13b U16b, U18b U22b Rank 1 = U1t U5t, U8t U11t, U13t U16t, U18t U22t V DDSPD V REF V SS U6 DDR2 SDRAM x 4 DDR2 SDRAM x 4 DDR2 SDRAM x 4 DDR2 SDRAM x 4 DDR2 SDRAM x 4 DDR2 SDRAM x 4 DDR2 SDRAM x 4 DDR2 SDRAM x 4 DDR2 SDRAM x 4 Register x 2 SDA SPD EEPROM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM S7 S7# DM CS# S S# U11b DM CS# S S# U11t S16 S16# DM CS# S S# U13b DM CS# S S# U13t S8 S8# CB0 CB1 CB2 CB3 DM CS# S S# U5b DM CS# S S# U5t S17 S17# CB4 CB5 CB6 CB7 DM CS# S S# U18b DM CS# S S# U18t 6

7 General Description DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM modules use DDR architecture to achieve high-speed operation. DDR2 architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR2 modules use two sets of differential signals: S, S# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. A bidirectional data strobe (S, S#) is transmitted externally, along with data, for use in data capture at the receiver. S is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. S is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of S, and output data is referenced to both edges of S, as well as to both edges of CK. Serial Presence-Detect EEPROM Operation Register and PLL Operation 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM General Description DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I 2 C bus using the DIMM s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently disabling hardware write protection. DDR2 SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and clock loading. PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL. Parity Operations The registering clock driver can accept a parity bit from the system s memory controller, providing even parity for the control, command, and address bus. Parity errors are flagged on the Err_Out# pin. Systems not using parity are expected to function without issue if Par_In and Err_Out# are left as no connects (NC) to the system. 7

8 Electrical Specifications Table 7: Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Units V DD /V D V DD /V D supply voltage relative to V SS V V IN, V OUT Voltage on any pin relative to V SS V I I Input leakage current; Any input 0V V IN V DD ; V REF input 0V V IN 0.95V; (All other pins not under test = 0V) I OZ Output leakage current; 0V V OUT V D ; s and ODT are disabled Command/Address, RAS#, CAS#, WE# S#, CKE, ODT, BA µa CK, CK# , S, S# µa I VREF V REF leakage current; V REF = Valid V REF level µa T A Module ambient operating temperature Commercial 0 70 C T C 1 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM Electrical Specifications Industrial DDR2 SDRAM device operating case temperature Commercial 0 85 C 2 Industrial Notes: 1. The refresh rate is required to double when T C exceeds 85 C. 2. For further information, refer to technical note TN-00-08: "Thermal Applications," available on Micron s web site. 8

9 DRAM Operating Conditions 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM DRAM Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades. Table 8: Module and Component Speed Grades DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -1GA -187E -80E -25E E -37E -40E -5E Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. 9

10 I DD Specifications I DD Specifications Table 9: DDR2 I CDD Specifications and Conditions 4GB (Die Revision G) Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (512 Meg x 4) component data sheet Parameter Operating one bank active-precharge current: t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ), t RCD = t RCD (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address Combined Symbol -80E/ Units I CDD ma I CDD ma bus inputs are switching; Data pattern is same as I DD4W Precharge power-down current: All device banks idle; t CK = t CK (I DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; t CK = t CK (I DD ); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; t CK = t CK (I DD ); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; t CK = t CK (I DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 Slow PDN exit MR[12] = 1 Active standby current: All device banks open; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst read, I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: t CK = t CK (I DD ); REFRESH command at every t RFC (I DD ) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating I CDD2P ma I CDD2Q ma I CDD2N ma I CDD3P ma I CDD3N ma I CDD4W ma I CDD4R ma I CDD ma I CDD ma 10

11 I DD Specifications Table 9: DDR2 I CDD Specifications and Conditions 4GB (Die Revision G) (Continued) Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (512 Meg x 4) component data sheet Parameter Operating bank interleave read current: All device banks interleaving reads, I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = t RCD (I DD ) - 1 t CK (I DD ); t CK = t CK (I DD ), t RC = t RC (I DD ), t RRD = t RRD (I DD ), t RCD = t RCD (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching Combined Symbol -80E/ Units I CDD ma Table 10: DDR2 I CDD Specifications and Conditions 4GB (Die Revision H) Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (512 Meg x 4) component data sheet Parameter Operating one bank active-precharge current: t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ), t RCD = t RCD (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address Combined Symbol -80E/ Units I CDD ma I CDD ma bus inputs are switching; Data pattern is same as I DD4W Precharge power-down current: All device banks idle; t CK = t CK (I DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; t CK = t CK (I DD ); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; t CK = t CK (I DD ); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; t CK = t CK (I DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 Slow PDN exit MR[12] = 1 Active standby current: All device banks open; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching I CDD2P ma I CDD2Q ma I CDD2N ma I CDD3P ma I CDD3N ma I CDD4W ma 11

12 I DD Specifications Table 10: DDR2 I CDD Specifications and Conditions 4GB (Die Revision H) (Continued) Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (512 Meg x 4) component data sheet Parameter Operating burst read current: All device banks open; Continuous burst read, I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: t CK = t CK (I DD ); REFRESH command at every t RFC (I DD ) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads, I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = t RCD (I DD ) - 1 t CK (I DD ); t CK = t CK (I DD ), t RC = t RC (I DD ), t RRD = t RRD (I DD ), t RCD = t RCD (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching Combined Symbol -80E/ Units I CDD4R ma I CDD ma I CDD ma I CDD ma Table 11: DDR2 I CDD Specifications and Conditions 4GB (Die Revision M) Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (512 Meg x 4) component data sheet Parameter Operating one bank active-precharge current: t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ), t RCD = t RCD (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address Combined Symbol -80E/ Units I CDD ma I CDD ma bus inputs are switching; Data pattern is same as I DD4W Precharge power-down current: All device banks idle; t CK = t CK (I DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; t CK = t CK (I DD ); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; t CK = t CK (I DD ); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; t CK = t CK (I DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 Slow PDN exit MR[12] = 1 I CDD2P ma I CDD2Q ma I CDD2N ma I CDD3P ma

13 I DD Specifications Table 11: DDR2 I CDD Specifications and Conditions 4GB (Die Revision M) (Continued) Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (512 Meg x 4) component data sheet Parameter Active standby current: All device banks open; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst read, I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: t CK = t CK (I DD ); REFRESH command at every t RFC (I DD ) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads, I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = t RCD (I DD ) - 1 t CK (I DD ); t CK = t CK (I DD ), t RC = t RC (I DD ), t RRD = t RRD (I DD ), t RCD = t RCD (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching Combined Symbol -80E/ Units I CDD3N ma I CDD4W ma I CDD4R ma I CDD ma I CDD ma I CDD ma Table 12: DDR2 I CDD Specifications and Conditions 8GB (Die Revision C) Values shown for MT47H1G4 DDR2 SDRAM only and are computed from values specified in the 4Gb TwinDie (1 Gig x 4) component data sheet Parameter Operating one bank active-precharge current: t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ), t RCD = t RCD (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address Combined Symbol -80E/ Units I CDD ma I CDD ma bus inputs are switching; Data pattern is same as I DD4W Precharge power-down current: All device banks idle; t CK = t CK (I DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; t CK = t CK (I DD ); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating I CDD2P ma I CDD2Q ma 13

14 I DD Specifications Table 12: DDR2 I CDD Specifications and Conditions 8GB (Die Revision C) (Continued) Values shown for MT47H1G4 DDR2 SDRAM only and are computed from values specified in the 4Gb TwinDie (1 Gig x 4) component data sheet Parameter Precharge standby current: All device banks idle; t CK = t CK (I DD ); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; t CK = t CK (I DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 Slow PDN exit MR[12] = 1 Active standby current: All device banks open; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst read, I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: t CK = t CK (I DD ); REFRESH command at every t RFC (I DD ) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads, I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = t RCD (I DD ) - 1 t CK (I DD ); t CK = t CK (I DD ), t RC = t RC (I DD ), t RRD = t RRD (I DD ), t RCD = t RCD (I DD ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching Combined Symbol -80E/ Units I CDD2N ma I CDD3P ma I CDD3N ma I CDD4W ma I CDD4R ma I CDD ma I CDD ma I CDD ma 14

15 Register and PLL Specifications 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM Register and PLL Specifications Table 13: Register Specifications SSTU32866 devices or equivalent Parameter Symbol Pins Condition Min Max Units DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage Output high voltage V IH(DC) V IL(DC) V IH(AC) V IL(AC) Control, command, address Control, command, address Control, command, address Control, command, address SSTL_18 V REF(DC) V D mv SSTL_18 0 V REF(DC) mv SSTL_18 V REF(DC) mv SSTL_18 V REF(DC) mv V OH Parity output LVCMOS 1.2 V Output low voltage V OL Parity output LVCMOS 0.5 V Input current I I All pins V I = V DD or V SS ±0.5 µa Static standby I DD All pins RESET# = V SSQ (I O = 0) 100 µa Static operating I DD All pins RESET# = V SS ; V I = V IH(AC) or V IL(DC) I O = 0 Dynamic operating (clock tree) Dynamic operating (per each input) Input capacitance (per device, per pin) Input capacitance (per device, per pin) I DDD N/A RESET# = V DD ; V I = V IH(DC) or V IL(AC), I O = 0; CK and CK# switching 50% duty cycle I DDD N/A RESET# = V DD ; V I = V IH(AC) or V IL(DC), I O = 0; CK and CK# switching 50% duty cycle; One data in/out switching at t CK/2, 50% duty cycle C IN All inputs except RESET# V I = V REF ±250mV; V DD = 1.8V C IN RESET# V I = V DD or V SS Varies by manufacturer 40 ma Varies by manufacturer Varies by manufacturer µa µa pf Varies by manufacturer pf Note: 1. Timing and switching specifications for the register listed are critical for proper operation of the DDR2 SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC standard JESD82. 15

16 Register and PLL Specifications Table 14: PLL Specifications CU877 device or equivalent Parameter Symbol Pins Condition Min Max Units DC high-level input voltage DC low-level input voltage Input voltage (limits) V IN RESET#, CK, CK# DC high-level input voltage DC low-level input voltage Input differential-pair cross voltage Input differential voltage Input differential voltage V IH RESET# LVCMOS 0.65 V DD V V IL RESET# LVCMOS 0.35 V DD V V DD V V IH CK, CK# Differential input 0.65 V DD V V IL CK, CK# Differential input 0.35 V DD V V IX CK, CK# Differential input (V D /2) (V DD /2) V V ID(DC) CK, CK# Differential input 0.3 V DD V V ID(AC) CK, CK# Differential input 0.6 V DD V Input current I I RESET# V I = V DD or V SS µa Output disabled current CK, CK# V I = V DD or V SS µa I ODL RESET# = V SS ; V I = V IH(AC) or V IL(DC) 100 µa Static supply current I DDLD CK = CK# = LOW 500 µa Dynamic supply I DD N/A CK, CK# = 270 MHz, all outputs open (not connected to PCB) 300 ma Input capacitance C IN Each input V I = V DD or V SS 2 3 pf Table 15: PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Symbol Min Max Units Stabilization time t L 15 μs Input clock slew rate slr(i) V/ns SSC modulation frequency khz SSC clock input frequency deviation % PLL loop bandwidth ( 3dB from unity gain) 2.0 MHz Note: 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information is available in JEDEC standard JESD82. 16

17 Serial Presence-Detect Table 16: SPD EEPROM Operating Conditions 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM Serial Presence-Detect For the latest SPD data, refer to Micron's SPD page: Parameter/Condition Symbol Min Max Units Supply voltage V DDSPD V Input high voltage: logic 1; All inputs V IH V DDSPD 0.7 V DDSPD V Input low voltage: logic 0; All inputs V IL 0.6 V DDSPD 0.3 V Output low voltage: I OUT = 3mA V OL 0.4 V Input leakage current: V IN = GND to V DD I LI µa Output leakage current: V OUT = GND to V DD I LO µa Standby current I SB µa Power supply current, READ: SCL clock frequency = 100 khz I CCR ma Power supply current, WRITE: SCL clock frequency = 100 khz I CCW 2 3 ma Table 17: SPD EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid t AA µs 1 Time bus must be free before a new transition can start t BUF 1.3 µs Data-out hold time t DH 200 ns SDA and SCL fall time t F 300 ns 2 SDA and SCL rise time t R 300 ns 2 Data-in hold time t HD:DAT 0 µs Start condition hold time t HD:STA 0.6 µs Clock HIGH period t HIGH 0.6 µs Noise suppression time constant at SCL, SDA inputs t I 50 ns Clock LOW period t LOW 1.3 µs SCL clock frequency t SCL 400 khz Data-in setup time t SU:DAT 100 ns Start condition setup time t SU:STA 0.6 µs 3 Stop condition setup time t SU:STO 0.6 µs WRITE cycle time t WRC 10 ms 4 Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time ( t WRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. 17

18 Module Dimensions Module Dimensions Figure 3: 240-Pin DDR2 VLP RDIMM Front view 4.0 (0.157) MAX (5.256) (5.244) 2.0 (0.079) R (4X) 2.5 (0.098) D (2X) 2.3 (0.091) TYP 2.2 (0.087) TYP 1.0 (0.039) TYP U1 U2 U3 U4 U5 Pin (0.039) TYP 0.8 (0.031) TYP U6 U7 U8 U9 U10 U (0.394) TYP 0.75 (0.029) R Pin 120 U (0.711) (0.699) 1.37 (0.054) 1.17 (0.046) (2.78) TYP (4.840) TYP Back view U13 U14 U15 U16 U18 U19 U20 U21 U22 U17 45 (2X) 3.05 (0.12) TYP Pin 240 Pin (0.197) TYP 55.0 (2.165) TYP 63.0 (2.48) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only S. Federal Way, P.O. Box 6, Boise, ID , Tel: Customer Comment Line: Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 18