1.35V DDR3L SDRAM LRDIMM

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1 .35V DDR3L SDRAM LRDIMM MT36KSZFG7LDZ 6GB Features Features 40-pin, load-reduced dual in-line memory module (LRDIMM) Memory buffer (MB) Fast data transfer rate: PC GB ( Gig x 7) V DD =.35V (.83.45V) Backward compatible to V DD =.5V ±0.075V V DDSPD = V Supports ECC error detection and correction Nominal and dynamic on-die termination (ODT) for data and strobe signals 8 internal device banks Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Two on-board temperature sensors Gold edge contacts Full module heat spreader Halogen-free Single load on and S Terminated control, command, and address bus Figure : 40-Pin LRDIMM (RC/B) MO-69 Module Height: 30.35mm (.95 in.) Options Marking Operating temperature Commercial (0 C T C +95 C) None Package 40-pin DIMM (halogen-free) Z Frequency/CAS CL = (DDR3-600) -G6 Table : Key Timing Parameters Speed Grade Industry Nomenclature Data Rate (MT/s) CL = CL = 0 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 -G6 PC G4 PC G PC G0 PC B PC t RCD (ns) t RP (ns) t RC (ns) 0 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

2 Features Table : Addressing Parameter 6GB Refresh count 8K Row address 64K A[5:0] Device bank address 8 BA[:0] Device configuration 4Gb (5 Meg x 8) Column address K A[9:0] Module rank address 4 S#[3:0] Table 3: Part s and Timing Parameters 6GB Modules Base device: MT4K5M8, 4Gb DDR3L SDRAM Part Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT36KSZFG7LDZ-G6 6GB Gig x 7.8 GB/s.5ns/600 MT/s -- Notes:. The data sheet for the base device can be found on Micron s web site.. All LRDIMM part numbers end with a two-place code (not shown) that designates component and PCB revisions, and a two-place code (also not shown) that indicates buffer vendor and revision. Consult factory for current revision codes. Example: MT36KSZFG7LDZ-G6PB3. 0 Micron Technology, Inc. All rights reserved.

3 Pin Assignments Pin Assignments Table 4: Pin Assignments 40-Pin DDR3 LRDIMM Front 40-Pin DDR3 LRDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol V REF A 9 4 V SS 5 V SS 8 A V SS V SS 3 V SS 6 V DD 9 V SS 4 5 S 8 V DD S S3# 63 NF 93 S5# S# 83 V DD 3 S4# 4 34 S3 64 NF 94 S5 4 V SS 54 V SS 84 CK0 4 V SS 5 V SS 35 V SS 65 V DD 95 V SS 5 S CK0# S0# V DD S9# V DD S V REFCA V SS 57 V SS 87 EVENT# 7 V SS 8 V SS 38 V SS 68 Par_In 98 V SS CB4 88 A CB0 69 V DD CB5 89 V DD CB 70 A0/AP V SS 60 V SS 90 BA 0 V SS V SS 4 V SS 7 BA0 0 V SS 3 6 S7 9 V DD S5 8 4 S8# 7 V DD 0 S6# S7# 9 RAS# S5# S8 73 WE# 03 S6 33 V SS 63 V SS 93 S0# 3 V SS 4 V SS 44 V SS 74 CAS# 04 V SS 34 S0 64 CB6 94 V DD S# 45 CB 75 V DD S0# 65 CB7 95 ODT S 46 CB3 76 S# V SS 66 V SS 96 A3 6 V SS 7 V SS 47 V SS 77 ODT 07 V SS NF 97 V DD V TT 78 V DD RESET# 98 S3# V TT 79 S# V SS 69 CKE 99 V SS 9 V SS 0 V SS 50 CKE0 80 V SS 0 V SS V DD S6 6 5 V DD 8 3 S7# 4 7 A S6# 7 5 BA 8 33 S7 4 V SS 7 A4 0 V SS 3 V SS 3 V SS 53 Err_Out# 83 V SS 3 V SS 43 S 73 V DD 03 S S# 54 V DD 84 S4# S# 74 A 04 S3# S 55 A 85 S V SS 75 A9 05 V SS 35 V SS 6 V SS 56 A7 86 V SS 6 V SS V DD V DDSPD V DD SA A SA A SCL 48 V SS 78 A6 08 V SS 38 SDA 9 V SS 59 A4 89 V SS 9 SA V DD V SS V DD V TT A V TT 3 0 Micron Technology, Inc. All rights reserved.

4 Pin Descriptions Table 5: Pin Descriptions Symbol Type Description The pin description table below is a comprehensive list of all possible pins for all DDR3 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A0) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A0 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A0 LOW, bank selected by BAx) or all banks (A0 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR, MR, or MR3) is loaded during the LOAD MODE command. CKx, CKx# Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the and S pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins:, S, S#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input (LVCMOS) Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed. Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the temperature sensor/spd EEPROM address range on the I C bus. SCL Input Serial clock for temperature sensor/spd EEPROM: Used to synchronize communication to and from the temperature sensor/spd EEPROM on the I C bus. CBx I/O Check bits: Used for system error detection and correction. x I/O Data input/output: Bidirectional data bus. Sx, Sx# I/O Pin Descriptions Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-aligned with write data. 4 0 Micron Technology, Inc. All rights reserved.

5 Pin Descriptions Table 5: Pin Descriptions (Continued) Symbol Type Description SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sensor/spd EEPROM on the I C bus. TSx, TSx# Err_Out# EVENT# Output Output (open drain) Output (open drain) Redundant data strobe (x8 devices only): TS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TS is enabled, DM is disabled and TS and TS# provide termination resistance; otherwise, TS# are no function. Parity error output: Parity error found on the command and address bus. Temperature event: The EVENT# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. V DD Supply Power supply:.5v ±0.075V. The component V DD and V D are connected to the module V DD. V DDSPD Supply Temperature sensor/spd EEPROM power supply: V. V REFCA Supply voltage: Control, command, and address V DD /. V REF Supply voltage:, DM V DD /. V SS Supply Ground. V TT Supply Termination voltage: Used for control, command, and address V DD /. NC No connect: These pins are not connected on the module. NF No function: These pins are connected within the module, but provide no functionality. 5 0 Micron Technology, Inc. All rights reserved.

8 Map Table 6: -to-module Map, Front (Continued) Module Module U U9 0 CB CB CB CB CB CB CB CB3 46 Table 7: -to-module Map, Back Module Module U 0 CB7 65 U CB CB CB CB CB CB CB U U Micron Technology, Inc. All rights reserved.

11 Functional Block Diagram Functional Block Diagram Figure : Functional Block Diagram 36 x8 DRAM, in 4 Module Rank Configuation Rank Rank Rank 0 Data and strobes Group A (Address/Command/Control/Clock) Group B (Address/Command/Control/Clock) Rank 3 Memory Buffer CS#, CKEA, ODT tied to V DD ODT tied to V DD, CKE3B, CS3# Configuration and Status Registers Temp Sensor CS0#, CKE0A, ODT0A ODTB, CKEB, CS# S[7:0] S#[7:0] [63:0] CB[7:0] S#[3:0] BA[:0] A[5:0] PAR_IN RAS# CAS# WE# CKE0 CKE ODT0 ODT CK0 CK0# RESET# ERROUT# EVENT# SPD/EEPROM Temp Sensor SMBus Data and strobes Address/Command/Control/Clock EVENT# 0 Micron Technology, Inc. All rights reserved.

12 General Description Memory Buffer Operation Control and Status Registers General Description The LRDIMM uses the same interface as the standard DDR3 RDIMM, but reduces the channel loading by buffering all signals that go to the DRAM. Like a standard RDIMM, the command, control, address, and clocks are redriven by the memory buffer and have similar characteristics to single-registered RDIMM. Additionally, the LRDIMM buffers all data and strobes through the memory buffer. This reduces the channel loading, as there is only a single load per signal, per module, for all and S nodes. The LRDIMM is a high-speed, CMOS dynamic random access memory module that uses internally configured 8-bank DDR3 SDRAM devices. DDR3 architecture is an 8nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and S signals can be easily accounted for by using the write-leveling feature of DDR3. LRDIMMs use two sets of differential signals: S/S# to capture data and CK/CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. The LRDIMM includes two temperature sensors: A temperature sensor located within the memory buffer monitors the temperature of that high-current device on the PCB. A temperature sensor integrated with the serial presence-detect (SPD) EEPROM monitors the temperature of the module PCB directly through a heat paddle under the EE- PROM. The DRAM temperature is related to these two indicators by a combination of heat spreader performance, ambient temperature, and air flow. LRDIMMs provide increased performance by presenting a single memory buffer to the system, rather than multiple DRAM. Additionally, increased capacity is achieved due to the well-defined topology and load that is achieved on the module because the memory buffer drives only the SDRAM. Four chip selects are possible at the edge connector; however, the memory buffer provides an address multiplication feature to increase the number of ranks accessible to the system. The memory buffer uses one or two of the upper chip selects not directly usable by the SDRAM to generate additional chip selects. This feature is configurable within the memory buffer. The memory buffer contains control and status registers. All control and status registers are accessible through the SMBus, as well as through in-band channel commands. The 0 Micron Technology, Inc. All rights reserved.

13 General Description registers can be read by software from the SMBus host any time the memory buffer is powered, except when the memory buffer is in clock-stopped power-down mode, or when the device RESET# pin is asserted. Temperature Sensor Parity Operations The memory buffer contains a class-c temperature sensor that can be configured to assert the EVENT# pin when temperature thresholds are exceeded. The temperature sensor is accessible through the SMBus. The memory buffer can accept a parity bit from the system s memory controller, providing even parity for the control, command, and address bus. Parity is calculated from all command and address signals (CKE, ODT, and S# are not included in parity). The last bit of the sum is compared to the parity signal provided by the system at the Par_In pin. Parity errors are flagged on the Err_Out# pin. Parity is also checked during control-word programming. Serial Presence-Detect EEPROM with Temperature Sensor Serial Presence-Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 56-byte EEPROM. The first 8 bytes are programmed by Micron to comply with JEDEC standard JC-45, Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules. These bytes identify module-specific timing parameters, configuration information, and physical attributes. User-specific information can be written into the remaining 8 bytes of storage. READ/WRITE operations between the system (master) and the EEPROM (slave) device occur via the SMBus. Write-protect (WP) is connected to V SS, permanently disabling hardware write-protect. For further information please refer to Micron technical note TN-04-4, "Memory Module Serial Presence-Detect." Temperature Sensor A class-b temperature sensor is integrated with the SPD EEPROM component on the module. The sensor temperature is monitored and converted into a digital word via the SMBus. System designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC standard No. -C page 4.7-, Definition of the TSE00av, Serial Presence Detect with Temperature Sensor. 3 0 Micron Technology, Inc. All rights reserved.

14 Electrical Specifications Table 8: Absolute Maximum Ratings Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Units V DD V DD supply voltage relative to V SS V V IN, V OUT Voltage on any pin relative to V SS V Table 9: Operating Conditions Symbol Parameter Min Nom Max Units Notes V DD V DD supply voltage V V REFCA(DC) Input reference voltage command/ address bus V 0.49 V DD 0.5 V DD 0.5 V DD V V REF(DC) I/O reference voltage bus 0.49 V DD 0.5 V DD 0.5 V DD V I VTT Termination reference current from ma V TT V TT Termination reference voltage (DC) command/address bus T A T C Module ambient operating temperature DDR3 SDRAM component case operating temperature 0.49 V DD - 0mV 0.5 V DD 0.5 V DD + 0mV V Commercial 0 70 C 3, 4 Commercial 0 95 C 3, 4, 5 Notes:. Module is backward compatible with.5v operation. Refer to device specification for details and operation guidance.. V TT termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins. 3. T A and T C are simultaneous requirements. 4. For further information, refer to technical note TN-00-08: Thermal Applications, available on Micron s web site. 5. The refresh rate is required to double when 85 C < T C 95 C. 4 0 Micron Technology, Inc. All rights reserved.

15 DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR3 component data sheets. specifications are available at micron.com. Module speed grades correlate with component speed grades, as shown below. Table 0: Module and Speed Grades DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Speed Grade -G G9-07 -G6-5 -G4-5E -G -87E -G C -5E -80B -5 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. 5 0 Micron Technology, Inc. All rights reserved.

16 I DD Specifications I DD Specifications Table : DDR3 I DD Specifications and Conditions 6GB (Die Revision E) Values are for the MT4K5M8 DDR3L SDRAM only and are computed from values specified in the.35v 4Gb (5 Meg x 8) component data sheet Parameter Symbol 600 Units Operating current 0: One bank ACTIVATE-to-PRECHARGE I DD0 98 ma Operating current : One bank ACTIVATE-to-READ-to-PRECHARGE I DD 080 ma Precharge power-down current: Slow exit I DDP0 648 ma Precharge power-down current: Fast exit I DDP 5 ma Precharge quiet standby current I D 5 ma Precharge standby current I DDN 5 ma Precharge standby ODT current I DDNT 837 ma Active power-down current I DD3P 368 ma Active standby current I DD3N 368 ma Burst read operating current I DD4R 899 ma Burst write operating current I DD4W 6 ma Refresh current I DD5B 60 ma Self refresh temperature current: MAX T C = 85 C I DD6 70 ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET 900 ma All banks interleaved read current I DD7 466 ma Reset current I DD8 70 ma Notes:. One module rank in the active I DD, the other ranks in I DDP0 (slow exit).. All ranks in this I DD condition. 6 0 Micron Technology, Inc. All rights reserved.

17 I DD Specifications Table : DDR3 I DD Specifications and Conditions 6GB (Die Revision P) Values are for the MT4K5M8 DDR3L SDRAM only and are computed from values specified in the.35v 4Gb (5 Meg x 8) component data sheet Parameter Symbol 600 Units Operating current 0: One bank ACTIVATE-to-PRECHARGE I DD0 5 ma Operating current : One bank ACTIVATE-to-READ-to-PRECHARGE I DD 657 ma Precharge power-down current: Slow exit I DDP0 360 ma Precharge power-down current: Fast exit I DDP 396 ma Precharge quiet standby current I D 540 ma Precharge standby current I DDN 576 ma Precharge standby ODT current I DDNT 450 ma Active power-down current I DD3P 540 ma Active standby current I DD3N 70 ma Burst read operating current I DD4R 080 ma Burst write operating current I DD4W 79 ma Refresh current I DD5B 638 ma Self refresh temperature current: MAX T C = 85 C I DD6 540 ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET 88 ma All banks interleaved read current I DD7 440 ma Reset current I DD8 468 ma Notes:. One module rank in the active I DD, the other ranks in I DDP0 (slow exit).. All ranks in this I DD condition. 7 0 Micron Technology, Inc. All rights reserved.

18 Temperature Sensor with Serial Presence-Detect EEPROM Serial Presence-Detect Temperature Sensor with Serial Presence-Detect EEPROM The temperature sensor continuously monitors the module s temperature and can be read back at any time over the SMBus bus shared with the SPD EEPROM and memory buffer. For the latest SPD data, refer to Micron's SPD page: Table 3: Temperature Sensor with SPD EEPROM Operating Conditions Parameter/Condition Symbol Min Max Units Supply voltage V DDSPD V Supply current: V DD = 3.3V I DD.0 ma Input high voltage: Logic ; SCL, SDA V IH V DDSPD x 0.7 V DDSPD + V Input low voltage: Logic 0; SCL, SDA V IL 0.5 V DDSPD x 0.3 V Output low voltage: I OUT =.ma V OL 0.4 V Input current I IN µa Temperature sensing range 40 5 C Temperature sensor accuracy (class B).0.0 C Table 4: Temperature Sensor and SPD EEPROM Serial Interface Timing Parameter/Condition Symbol Min Max Units Time bus must be free before a new transition can start t BUF 4.7 µs SDA fall time t F ns SDA rise time t R 000 ns Data hold time t HD:DAT ns Start condition hold time t H:STA 4.0 µs Clock HIGH period t HIGH µs Clock LOW period t LOW 4.7 µs SCL clock frequency t SCL 0 00 khz Data setup time t SU:DAT 50 ns Start condition setup time t SU:STA 4.7 µs Stop condition setup time t SU:STO 4.0 µs EVENT# Pin The temperature sensor also adds the EVENT# pin (open-drain). Although not used by the SPD EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor s configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. The open-drain output of EVENT# under the three separate operating modes is illustrated below. Event thresholds are programmed in the 0x0 reg- 8 0 Micron Technology, Inc. All rights reserved.

19 SMBus Slave Subaddress Decoding Serial Presence-Detect Data Temperature Sensor with Serial Presence-Detect EEPROM ister using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and returns to the logic HIGH state only when the temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. When the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical EVENT# cannot be cleared through software. The temperature sensor s physical address differs from the SPD EEPROM s physical address: binary 00 for A0, A, A, and RW#, where A, A, and A0 are the three slave subaddress pins and the RW# bit is the READ/WRITE flag. If the slave base address is fixed for the SPD EEPROM/temperature sensor, then the pins set the subaddress bits of the slave address, enabling the devices to be located anywhere within the eight slave address locations. For example, they could be set from 30h to 3Eh. For the latest serial presence-detect data, refer to Micron's SPD page: Micron Technology, Inc. All rights reserved.

20 Module Dimensions Module Dimensions Figure 3: 40-Pin DDR3 LRDIMM 0.9 (0.035) TYP Front view (5.56) 33.0 (5.44) 4.67(0.84) MAX 0.50 (0.0) R (4X) 0.75 (0.03) R (8X).50 (0.098) D (X) U U U3 U4 U5 U7 U8 U9 U0 U6 U U U3 U4 U5 U6 U7 U8 U9 7.3 (0.68) TYP 3.3 (0.9) TYP (.) 9.85 (.75).30 (0.09) TYP.0 (0.087) TYP.45 (0.057) TYP Pin (.5) TYP 0.75 (0.03) R 3.0 (4.84) TYP.0 (0.039) TYP 0.80 (0.03) TYP 9.5 (0.374) TYP Pin 0.37 (0.054).7 (0.046) 5.0 (0.59) TYP (4X) Back view.0 (0.039) R (8X) 45 4X 5.45 (0.5) TYP U U U3 U4 U0 U5 U6 U7 U8 U9 3. (0.) X TYP U30 U3 U3 U33 U34 U35 U36 U37 U (0.8) 4X TYP 3.05 (0.) TYP Pin (0.97) TYP Pin 7.0 (.79) 47.0 (.85) TYP TYP With heat spreader attached 7.55 (0.97) MAX U U U3 U4 U5 U7 U8 U9 U0 U U U3 U4 U5 U6 U7 U8 U9 U6 U U U3 U4 U0 U5 U6 U7 U8 U9 U30 U3 U3 U33 U34 U35 U36 U37 U38 Notes:. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.. The dimensional diagram is for reference only. 0 0 Micron Technology, Inc. All rights reserved.

21 Module Dimensions 8000 S. Federal Way, P.O. Box 6, Boise, ID , Tel: Sales inquiries: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 0 Micron Technology, Inc. All rights reserved.

1.35V DDR3L SDRAM LRDIMM

1.35V DDR3L SDRAM LRDIMM .35V DDR3L SDRAM LRDIMM MT36KSZFG7LDZ 8GB MT36KSZFG7LDZ 6GB 8GB, 6GB (x7, ECC, QR x8) 40-Pin DDR3L LRDIMM Features Features 40-pin, load-reduced dual in-line memory module (LRDIMM) Memory buffer (MB) Fast