DYNAMIC ENGINEERING 150 DuBois St. Suite C, Santa Cruz, Ca Fax Est.

Transcription

1 DYNAMIC ENGINEERING 150 DuBois St. Suite C, Santa Cruz, Ca Fax Est User Manual PC104p Biserial III NVY5 Digital Parallel Interface PCI-104 Module 16 bit Port Manual Revision: A1 Revised: 4/24/13 Corresponding Hardware: FLASH by Dynamic Engineering. Other trademarks and registered trademarks are owned by their respective manufacturers. Embedded Solutions Page 1 of 35

2 PC104p Biserial III NVY5 Digital Parallel Interface PCI-104 Module Dynamic Engineering 150 DuBois St. Suite C, Santa Cruz CA FAX This document contains information of proprietary interest to Dynamic Engineering. It has been supplied in confidence and the recipient, by accepting this material, agrees that the subject matter will not be copied or reproduced, in whole or in part, nor its contents revealed in any manner or to any person except to meet the purpose for which it was delivered. Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to make improvements or changes in the product described in this document at any time and without notice. Furthermore, Dynamic Engineering assumes no liability arising out of the application or use of the device described herein. The electronic equipment described herein generates, uses, and can radiate radio frequency energy. Operation of this equipment in a residential area is likely to cause radio interference, in which case the user, at his own expense, will be required to take whatever measures may be required to correct the interference. Dynamic Engineering s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Dynamic Engineering. This product has been designed to operate with PCI-104 Modules and compatible user-provided equipment. Connection of incompatible hardware is likely to cause serious damage. E m b e d d e d S o l u t i o n s P a g e 2 o f 3 5

3 Table of Contents PRODUCT DESCRIPTION 6 THEORY OF OPERATION 8 ADDRESS MAP 10 PROGRAMMING 12 Register Definitions 14 NVY5_BASE_BASE 14 NVY5_BASE_ID 15 NVY5_BASE_STATUS 16 NVY5_BASE_DATAEN 17 NVY5_BASE_DATAIO 17 NVY5_BASE_DATAREG 17 NVY5_CHAN_BASE 18 NVY5_CHAN_WR_DMA 23 NVY5_CHAN_RD_DMA 24 NVY5_CHAN_SW(R/W) 25 NVY5_CHAN_TX_AECNT 25 NVY5_CHAN_RX_AFCNT 25 NVY5_CHAN_TX_CNT 26 NVY5_CHAN_RX_CNT 26 NVY5_CHAN_TXSIZE 26 PCI-104 Notes 27 LOOP-BACK 28 PCI-104 MODULE LOGIC INTERFACE PIN ASSIGNMENT 29 PCI-104 MODULE FRONT PANEL IO INTERFACE PIN ASSIGNMENT 30 APPLICATIONS GUIDE 31 Interfacing 31 Construction and Reliability 32 Thermal Considerations 32 WARRANTY AND REPAIR 33 Embedded Solutions Page 3 of 35

4 Service Policy 33 Out of Warranty Repairs 33 SPECIFICATIONS 34 ORDER INFORMATION 35 E m b e d d e d S o l u t i o n s P a g e 4 o f 3 5

5 List of Figures FIGURE 1 PC104PBISERIAL-III BLOCK DIAGRAM 6 FIGURE 2 PC104PBISERIAL-III INTERNAL ADDRESS MAP BASE FUNCTIONS 10 FIGURE 3 PC104PBISERIAL-III CHANNEL ADDRESS MAP 11 FIGURE 4 PC104PBISERIAL-III CONTROL PORT 0 BIT MAP 14 FIGURE 5 PC104PBISERIAL-III ID AND SWITCH BIT MAP 15 FIGURE 6 PC104PBISERIAL-III STATUS PORT BIT MAP 16 FIGURE 7 PC104PBISERIAL-III DATA ENABLE BIT MAP 17 FIGURE 8 PC104PBISERIAL-III DATA REGISTER BIT MAP 17 FIGURE 9 PC104PBISERIAL-III DATA REGISTER READ BACK 17 FIGURE 10 PC104PBISERIAL-III CHANNEL CONTROL REGISTER 18 FIGURE 11 PC104PBISERIAL-III CHANNEL STATUS PORT 20 FIGURE 12 PC104PBISERIAL-III WRITE DMA POINTER REGISTER 23 FIGURE 13 PC104PBISERIAL-III READ DMA POINTER REGISTER 24 FIGURE 14 PC104PBISERIAL-III RX/TX FIFO PORT 25 FIGURE 15 PC104PBISERIAL-III TX ALMOST EMPTY LEVEL REGISTER 25 FIGURE 16 PC104PBISERIAL-III RX ALMOST FULL LEVEL REGISTER 25 FIGURE 17 PC104PBISERIAL-III TX FIFO DATA COUNT PORT 26 FIGURE 18 PC104PBISERIAL-III RX FIFO DATA COUNT PORT 26 FIGURE 19 PC104PBISERIAL-III TARGET CONTROL PORT 26 FIGURE 20 PC104PBISERIAL-III J3 INTERFACE 29 FIGURE 21 PC104PBISERIAL-III NVY5 IO INTERFACE 30 Embedded Solutions Page 5 of 35

6 Product Description In embedded systems many of the interconnections are made with single ended TTL or CMOS level signals. Depending on the system architecture PCI-104, IP, PMC etc. will be the right choice to make the connection. With most architectures you have a choice as there are carriers for cpci, PCI, VME, PC/104p and other buses for PCI-104, PMC and IP mezzanine modules. For example the NVY5 was tested on a PCIBPC104p carrier to adapt the PC104pBis3Nvy5 design into the PCI environment. Usually the choice is based on other system constraints as PC1-104, PMC and IP can provide the IO you require. Dynamic Engineering would be happy to assist in your decision regarding architecture, and other trade-offs with the module decision. Dynamic Engineering has carriers for many module types with conversion for most architectures, and is adding more as new solutions are requested and required by our customers. PCI-104 compatible Pc104pBiserial-III has 16 independent differential IO plus 8 TTL plus 4 each ADC and DAC. Figure 1 PC104pBiSerial-III Block Diagram Pc104pBiserial-III-NVY5 is a customized version of the standard Pc104pBiserial-III board. NVY5 has the differential IO converted to TTL with the M side used for signal and the P side as a ground reference. 8 TTL are used as well. The analog section and external FIFO s are not installed. Embedded Solutions Page 6 of 35

7 One channel is installed and is supported with 8kx32 transmit FIFO and 1Kx32 receive FIFO. The receive side is only used for loop-back [internal] testing. NVY5 supports DMA into and out of the card. All of the IO are routed through the FPGA to allow for custom applications that require hardware intervention or specific timing- for example an automatic address or data strobe to be generated. The registers are mapped as 32 bit words All registers are read-writeable. The Windows compatible drivers are available to provide the system level interface for this design. Use standard C/C++ to control your hardware or use the Hardware manual to make your own software interface. The software manual is also available on-line. Please contact Dynamic Engineering if you need a Linux, Windows 7 or VxWorks driver for this design. The standard PCI-104 bus interface is provided PCI 32/33. NVY5 can be a bus master to perform DMA reads and writes. The PCI interface is universal supporting both 5V and 3.3V operation. The 5V power rail is used to supply all internal voltages. The FPGA and other components use 3.3, 2.5, and 1.2V. The FPGA is a Spartan III 1500 for the NVY5 design. The FPGA is supported with FLASH memory. A programming header is provided to allow for field updates as needed. E m b e d d e d S o l u t i o n s P a g e 7 o f 3 5

8 Theory of Operation PC104pBiserial-III can be used for multiple purposes with applications in telecommunications, control, sensors, IO, test; anywhere multiple independent or coordinated IO are useful. PC104pBiserial-III features a Xilinx FPGA, driver devices and analog IO. The FPGA contains the PCI interface and control required for the parallel interface. NVY5 is a parallel data protocol. The differential data bus has been converted to single ended and used for the data bus. The lower 3 TTL IO are used for DataReady, ReadEnable[REN], and the clock reference. NVY5 is the transmitter side. Data is loaded into the local memory and transferred to the external device. When a programmable threshold is reached the DataReady signal is pulsed for a programmable length of time. When the external HW detects Data Ready asserted a data transfer can begin. REN is asserted causing data to be read from the local FIFO and presented at the IO pins. The Clock Reference is received from the external device. The external device uses the rising edge and NVY5 the falling edge. Within NVY5 a clock mux and DCM combination are used to allow the PCI clock to be substituted when the external clock is indeterminate. SW can select the source and reset the DCM to cause it to reacquire the new reference. NVY5 is outfit with a PLL, however the PLL is not used on the NVY5 design To set-up, the channel control registers are written to with the enable for the statemachine set, length of DataReady, and trigger level for DataReady. Data can be written as standard target accesses or using DMA. For messages more than a few LW long DMA is recommended. The data is read into the HW when DMA is utilized. When the FIFO has enough data to match the programmed depth the DataReady signal is asserted. External HW will then assert the REN signal and this will automatically transfer the data from the FIFO to the external device. The External device will assert REN on a rising edge. On the next falling edge the REN signal will be registered with an Edge FF. On the second falling edge the FIFO will detect the REN signal. On the Third falling edge of the reference clock the edge register will drive the first data word onto the cable. On the third rising edge after REN the external device will capture the first data word. The data continues pipelined until REN is deasserted. It is up to the system to coordinate the length of REN and the depth of data for the DataReady trigger. The data being transferred is 16 bits wide. Data loaded into the FIFO is 32 bits wide. The FIFO converts from 32 to 16 bit wide data. The upper half of the data <31-16> is transmitted first and the lower half<15-0> second. E m b e d d e d S o l u t i o n s P a g e 8 o f 3 5

9 Since data transferred is x16 and stored is by x32 an implied restriction is even numbers of words for Ready depth and REN length. The reference SW has loop tests using a NVY6 board as the external HW to transmit multiple 1K blocks of data. DMA 16K into the card, run a loop of 1K block transfers out of the card, DMA 16K from the NVY6 card back to host memory, compare and repeat. E m b e d d e d S o l u t i o n s P a g e 9 o f 3 5

10 Address Map Function Offset // PMC Parallel TTL BA21 definitions #define NVY5_BASE_BASE 0x0000 // 0 base control register offset #define NVY5_BASE_ID 0x0004 // 1 ID Register offset #define NVY5_BASE_STATUS 0x0008 // 2 status Register offset #define NVY5_BASE_DATAEN 0x0010 // 4 Data Output Enable Register offset #define NVY5_BASE_DATAIO 0x0014 // 5 Data IO Register, line data read #define NVY5_BASE_DATAREG 0x0018 // 6 Data Register Read Only Figure 2 PC104PBISERIAL-III Internal Address Map Base Functions The address map provided is for the local decoding performed within Pc104pBiserial-III- NVY5. The addresses are all offsets from a base address. The CPU board the PCI- 104 is installed into provides the base address. Dynamic Engineering prefers a longword oriented approach because it is more consistent across platforms. The map is presented with the #define style to allow cutting and pasting into many compilers include files. The host system will search the PCI bus to find the assets installed during power-on initialization. The VendorId = 0xDCBA and the CardId = 0x004E for the Pc104pBiserial- III-NVY5. E m b e d d e d S o l u t i o n s P a g e 1 0 o f 3 5

11 Function Offset // PMC Parallel TTL BA21 definitions #define NVY5_CHAN_BASE 0x0000 // 0 Chanel control register #define NVY5_CHAN_STATUS 0x0004 // 1 Channel status, interrupt clear #define NVY5_CHAN_WR_DMA 0x0008 // 2 Channel burst in control #define NVY5_CHAN_TX_CNT 0x0008 // 2 Channel Read TX FIFO Count #define NVY5_CHAN_RD_DMA 0x000C // 3 Channel burst out control #define NVY5_CHAN_RX_CNT 0x000C // 3 Channel Read Rx FIFO Count #define NVY5_CHAN_SW(R/W) 0x0010 // 4 Channel FIFO single read RX, single write TX FIFO #define NVY5_CHAN_tx_aecnt 0x0014 // 5 Channel almost empty count register and rd-bk #define NVY5_CHAN_rx_afcnt 0x0018 // 6 Channel almost full count register and rd-bk #define NVY5_CHAN_TXSIZE 0x002C // 11 Channel Transmit Size and Ready Width Register Figure 3 PC104PBISERIAL-III Channel Address Map There is 1 channel in the NVY5 design. The channel offset is added to the base offset. Channel 0 = 0x50 E m b e d d e d S o l u t i o n s P a g e 1 1 o f 3 5

12 Programming Programming the PC104pBiserial-III-NVY5 requires only the ability to read and write data in the host's memory space. Once the initialization process has occurred, and the system has assigned addresses to the Pc104pBiserial-III-NVY5 card, software will need to determine what the address space is for the PCI interface [BAR0]. The offsets in the address table are relative to the system assigned BAR0 base address. The next step is to initialize the Pc104pBiserial-III-NVY5. To use the parallel port, enable the bits intended to be outputs by writing a 1 to each bit position. Next write the output data to the IO port and / or read the input bits also from the IO port. The transmit bits are also present for IO read functions. To read the value of the transmit register read the DATAREG port. Please note the lower 3 bits are not available in this port as they are used for the NVY5 function To use the NVY5 function, select the external clock in the base register, reset the DCM, and program the channel control registers [base and Size as a minimum]. If interrupts will be used the master interrupt enable will need to be set. The Channel Control register is used to enable operation and to mask interrupts. The TxSize register lower 16 bits are used to program the amount of data required to be present before DataReady is pulsed. The Length of the pulse is programmed in the next byte. Data can be loaded into the FIFO. Once the trigger level is achieved a transfer can happen based on the external timing [When REN is asserted]. With NVY6 the delay is only a few clocks from DataReady asserted to REN asserted. The delay is from 2 levels of synchronization and the local SM recognizing the assertion. Interrupts can be enabled to happen at the end of each packet transfer and/or using the DMA interrupt at the end of the DMA transfer. Please note the DMA transfer size can be much larger than the packet size and off load the CPU a great deal. For example transfer 1 M x16 and get 1 interrupt instead of 1 per 1K so 1/1000 the interrupts to deal with. To use DMA, memory space from the system should be allocated and the link list stored into memory. The location of the link list is written to the NVY5 to start the DMA. Please refer to the Burst IN and Burst Out register discussions. For Windows, Linux, and VxWorks systems the Dynamic Driver can be used. The driver will take care of finding the hardware and provide an easy to use mechanism to program the hardware. The Driver comes with reference software showing how to use the card and reference frequency files to allow the user to duplicate the test set-up used E m b e d d e d S o l u t i o n s P a g e 1 2 o f 3 5

13 in manufacturing at Dynamic Engineering. Using simple, known to work routines is a good way to get acquainted with new hardware. Please note: as of 4/25/13 the Win32 driver package is completed and the others are planned. E m b e d d e d S o l u t i o n s P a g e 1 3 o f 3 5

14 Register Definitions NVY5_BASE_BASE [$00 Control Register Port read/write] DATA BIT DESCRIPTION spare 20 bit 19 read-back of pll_dat register bit 19 pll_dat [write to PLL, read-back from PLL] 18 pll_s2 17 pll_sclk 16 pll_en 15-7 spare 6 DCM Reset 5 DCM Source Select 4 SwitchSelEn 3-1 spare 0 Master Interrupt Enable Figure 4 PC104PBISERIAL-III Control port 0 Bit Map This is the base control register for the PMC Parallel TTL. The features common to all channels are controlled from this port. Unused bits are reserved for additional new features. Unused bits should be programmed 0 to allow for future commonality. Master Interrupt Enable when 1 gates active interrupt requesting conditions onto Interrupt Request A. When set to 0 the interrupting functions are available as status but no interrupt request is generated by the card to allow for polled operation. pll_en: When this bit is set to a one, the signals used to program and read the PLL are enabled. pll_sclk/pll_dat : These signals are used to program the PLL over the I 2 C serial interface. Sclk is always an output whereas Sdata is bi-directional. This register is where the Sdata output value is specified or read-back. pll_s2: This is an additional control line to the PLL that can be used to select additional pre-programmed frequencies. Set to 0 for most applications. The PLL is programmed with the output file generated by the Cypress PLL programming tool. [CY3672 R3.01 Programming Kit or CyberClocks R Cypress may update the revision from time to time.] The.JED file is used by the Dynamic Driver to program the PLL. Programming the PLL is fairly involved and beyond the scope of this manual. For clients writing their own drivers it is suggested to get the Engineering Kit for this board including software, and to E m b e d d e d S o l u t i o n s P a g e 1 4 o f 3 5

15 use the translation and programming files ported to your environment. This procedure will save you a lot of time. For those who want to do it themselves the Cypress PLL in use is the The output file from the Cypress tool can be passed directly to the Dynamic Driver [Linux or Windows] and used to program the PLL without user intervention. The reference frequency for the PLL is 50 MHz. DCM Source Select when 0 selects the PCI clock as the reference to use with the NVY5 IO function. This is the default selection to insure a clock is available at power up. When 1 the external clock from TTL(2) is used as the reference. After changing the selection use the reset function to cause the DCM to properly reacquire the new clock reference. DCM Reset when 1 resets the DCM used to generate the NVY5 IO reference clock. When 0 normal operation. SwitchSelEn when 0 uses the current switch settings for switches 1,0 to select the stack position. Switch 7 selects the location in memory of the device. See Switch definitions for more information. When SwitchSelEn is set 1 the value of the switch for the stack and memory are held to allow the switch settings to be changed without affecting the stack position etc. Useful for performing a switch test without changing interrupt levels and so forth. NVY5_BASE_ID [$04 Switch and Design number port read only] DATA BIT DESCRIPTION spare Design Number 15-8 Revision 7-0 DIP switch Figure 5 PC104PBISERIAL-III ID and Switch Bit Map The DIP Switch is labeled for bit number and 1 0 in the silk screen. The DIP Switch can be read from this port and used to determine which PC104p-BiSerial-III is which in a system with multiple cards installed. The DIPswitch can also be used for other purposes software revision etc. The switch shown would read back 0x The Design ID and Revision are defined by a 16 bit field allowing for 256 designs and E m b e d d e d S o l u t i o n s P a g e 1 5 o f 3 5

16 256 revisions of each. The NVY5 design is 0x05 the current revision is 0x01. The PCI revision is updated in HW to match the design revision. The board ID will be updated for major changes to allow drivers to differentiate between revisions and applications. The bits 1,0 are used to select the IDSEL, PCI Clock, Request / Grant and interrupt level. An external mux is used for the clock and IDSEL lines. The Request, Grant, and Interrupt logic is internal to the Xilinx. Bits 1,0 should be set to correspond to the level of the Biserial within the PC104p stack. The CPU would be the base level. Position 00 would be immediately above the CPU, position 01 would be the next position up etc. Bit 7 is used to select between the memory space and the IO space. For DOS programs it is useful to use the IO space. The footprint of this design is only 4K which also supports this requirement. It is important to have switch 7 = 0 at power up for normal Memory allocation. For DOS use 1. NVY5_BASE_STATUS [$08 Board level Status Port read only] DATA BIT DESCRIPTION 31-1 spare 0 Channel 0 Int Figure 6 PC104pBISERIAL-III Status Port Bit Map Channel XX Int This is the local masked interrupt from channel XX. This bit will tell the SW if any channel XX asset could be requesting an interrupt. If the master interrupt enable is set an interrupt will be generated if this condition is true. For this design the ISR can go direct to the channel status and skip reading this register as there is only one possible channel. E m b e d d e d S o l u t i o n s P a g e 1 6 o f 3 5

17 NVY5_BASE_DATAEN [$10 Enable Register bits 31-0 read write ] DATA BIT DESCRIPTION 31-0 DataEn7-0 Figure 7 PC104PBISERIAL-III Data Enable Bit Map The 32 bits of the parallel port direction are controlled with this port. When reset this port is cleared 0x All IO are set to read [inputs]. To use one or more of the IO for outputs; program the corresponding enable bit(s) to 1. Bits 7-0 are available and 7-3 active for this design. Bits 2-0 are used for NVY5 IO function. NVY5_BASE_DATAIO [$14 Data Register bits read write ] DATA BIT DESCRIPTION 31-0 DataIO 7-0 Figure 8 PC104PBISERIAL-III Data Register Bit Map If the corresponding Enable bit is set, the data bit is driven onto the IO line. When read the state of the IO lines is read. Use the DATAREG for read-back of the register value. NVY5_BASE_DATAREG [$18 Data Register bits read only ] DATA BIT DESCRIPTION 31-0 DataIO 7-0 Figure 9 PC104PBISERIAL-III Data Register Read Back Use DATAREG for read-back of the register value set in the output register. This value will always match what was written. The line value read back from the DATAIO register may not match as other devices may affect the IO values read. E m b e d d e d S o l u t i o n s P a g e 1 7 o f 3 5

18 NVY5_CHAN_BASE [0x50] Channel Control Register (read/write) Channel Control Register Data Bit Description 20 RxFfAFlIntEnLvl 19 TxFfAMtIntEnLvl 18 RxOvFlIntEn 17 TxUnFlIntEn 16 RxFfIntEn 15 TxFfIntEn 14 PacketIntEn 13 Spare 12 Enable 11-9 Spare 8 OutUrgent 7 InUrgent 6 Read DMA Interrupt Enable 5 Write DMA Interrupt Enable 4 Force Interrupt 3 Channel Interrupt Enable 2 Bypass Enable 1 Receiver Reset 0 Transmit Reset Figure 10 PC104PBISERIAL-III Channel Control Register Transmit Reset: When set to a one, the transmit FIFO will be reset. When 0 normal FIFO operation is enabled. In addition the TX and RX State Machine is reset. Receiver Reset: When set to a one, the receive and Packet FIFO s will be reset. When 0 normal FIFO operation is enabled. In addition the TX and RX State Machine is reset. Bypass Enable: When this bit is set to a one, any data written to the transmit FIFO will be transferred to the receive FIFO. This allows for fully testing the data FIFO s without using the I/O. When this bit is zero, normal FIFO operation is enabled. The rate at which the data is transferred depends on the IO clock selection [DCM Clock Select]. DMA can be used with Bypass mode. Write/Read DMA Interrupt Enable: These two bits, when set to one, enable the interrupts for DMA writes and reads respectively. The DMA interrupts are not affected by the Master Interrupt Enable at the channel level. Channel Interrupt Enable: When this bit is set to a one, all enabled interrupts (except the DMA interrupts) will be gated through to the Base interface level of the design; when this bit is a zero, the interrupts can be used for status without interrupting the host. The channel interrupt enable is for the channel level interrupt sources only. An additional board level master interrupt enable is located in the Base register. The board level master must also be enabled to gate the interrupt through to the host. Force Interrupt: When this bit is set to a one, a system interrupt will occur provided the E m b e d d e d S o l u t i o n s P a g e 1 8 o f 3 5

19 Channel Interrupt and master interrupt enables are set. This is useful for interrupt testing. Enable: When set 1 will start the NVY5 function. The External IO reference clock should be available and selected prior to enabling. PacketIntEn: When set 1 will enable an interrupt request when a Packet is completed. A packet is the programmed length of data having been read into the external hardware. TxFfIntEn: When set 1 will enable an interrupt request when the Tx FIFO has become Almost Empty. This version occurs when the condition of not almost empty transitions to almost empty. TxFfAMtIntEnLvl: When set 1 will enable an interrupt request when the Tx FIFO has become Almost Empty. This version occurs when the condition of almost empty is true. The effect is an interrupt that is continuous unless the condition is changed to be not almost empty. RxFfIntEn: When set 1 will enable an interrupt request when the Rx FIFO has become Almost Full. This version occurs when the condition of not almost full transitions to almost full. RxFfAFlIntEnLvl: When set 1 will enable an interrupt request when the Rx FIFO has become Almost Full. This version occurs when the condition of almost full is true. The effect is an interrupt that is continuous unless the condition is changed to be not almost full. If the SW is trying to keep the SM processing and using the AMT/AFL interrupt to refill / Empty the FIFO then the level version would be a good choice when the IO rate is high compared to the refill rate. With this design it is unlikely that the IO will outpace the load function. RxOvFlIntEn: When set 1 will enable an interrupt request when the Rx FIFO is full when it is time to load another word. NA this design. TxUnFlIntEn: When set 1 will enable an interrupt request when the Tx FIFO is empty when it is time to read another word. E m b e d d e d S o l u t i o n s P a g e 1 9 o f 3 5

20 NVY5_CHAN_STATUS [0x54] Channel Status Read/Clear Latch Write Port Channel Status Register Data Bit Description 31 Channel Interrupt Active 30 Local Int spare 25 Spare 24 Spare 23 BurstInIdle 22 BurstOutIdle 21 spare 20 SmIdleState 19 TxUnFlLat 18 RxFfOvFlLat (Spare) 17 Spare 16 PacketDoneLat 15 Read DMA Interrupt Occurred 14 Write DMA Interrupt Occurred 13 Read DMA Error Occurred 12 Write DMA Error Occurred 11 RxAFlIntLat 10 TxAMtIntLat 9 RxAFlIntLvl 8 TxAMtIntLvl 7 spare 6 Receive FIFO Full 5 Receive FIFO Almost Full 4 Receive FIFO Empty 3 spare 2 Transmit FIFO Full 1 Transmit FIFO Almost Empty 0 Transmit FIFO Empty Figure 11 Pc104pBiserial-III Channel STATUS PORT Transmit FIFO Empty: When a one is read, the transmit data FIFO contains no data; when a zero is read, there is at least one data word in the FIFO. Transmit FIFO Almost Empty: When a one is read, the number of data words in the transmit data FIFO is less than or equal to the value written to the TX_AMT_LVL register; when a zero is read, the FIFO level is more than that value. Transmit FIFO Full: When a one is read, the transmit data FIFO is full; when a zero is read, there is room for at least one more data word in the FIFO. E m b e d d e d S o l u t i o n s P a g e 2 0 o f 3 5

21 Please note with the Receive side status; the status reflects the state of the FIFO and does not take the 4 deep pipeline into account. For example the FIFO may be empty and there may be valid data within the pipeline. The data count is the combined FIFO and pipeline value and can be used for read size control. Receive FIFO Empty: When a one is read, the receive data FIFO contains no data; when a zero is read, there is at least one data word in the FIFO. Receive FIFO Almost Full: When a one is read, the number of data words in the receive data FIFO is greater or equal to the value written to the RX_AFL_LVL register; when a zero is read, the FIFO level is less than that value. Receive FIFO Full: When a one is read, the receive data FIFO is full; when a zero is read, there is room for at least one more data-word in the FIFO. TxAmtIntLvl: When a one is read, the transmit FIFO almost empty is asserted. This is a level based interrupt. The status is before the mask to allow for non-interrupt driven SW operation. When the FIFO level is below the programmed level this bit is asserted. TxAmtIntLat: When a one is read, the transmit FIFO almost empty has been asserted. This is a triggered interrupt. The status is before the mask to allow for non-interrupt driven SW operation. When the FIFO level has dipped below the programmed level the status is captured and held. Clear by writing back to this bit. RxAFlIntLvl: When a one is read, the receive FIFO almost full is asserted. This is a level based interrupt. The status is before the mask to allow for non-interrupt driven SW operation. When the FIFO level is above the programmed level this bit is asserted. RxAFlIntLat: When a one is read, the receive FIFO almost full has been asserted. This is a triggered interrupt. The status is before the mask to allow for non-interrupt driven SW operation. When the FIFO level has risen the programmed level the status is captured and held. Clear by writing back to this bit. TxFfUnFl Interrupt Occurred: When a one is read, it indicates that the Tx FIFO has suffered an underflow condition; defined as being empty when a read is attempted. A zero indicates proper operation. This bit is latched and can be cleared by writing back to the Status register with a one in this bit position. Write/Read DMA Error Occurred: When a one is read, a write or read DMA error has been detected. This will occur if there is a target or master abort or if the direction bit in the next pointer of one of the chaining descriptors is incorrect. A zero indicates that no write or read DMA error has occurred. These bits are latched and can be cleared by writing back to the Status register with a one in the appropriate bit position. BO and BI Idle are Burst Out and Burst In IDLE state status for the Receive and Transmit DMA actions. The bits will be 1 when in the IDLE state and 0 when processing a DMA. A new DMA should not be launched until the State machine is back E m b e d d e d S o l u t i o n s P a g e 2 1 o f 3 5

22 in the IDLE state. Please note that the direction implied in the name has to do with the DMA direction Burst data into the card for TX and burst data out of the card for Receive. SmIdleState is set when the I2C state-machine is in the idle state. If SW has cleared the enable bit SmIdleState can be used to determine the HW has completed its task and returned. Write/Read DMA Interrupt Occurred: When a one is read, a write/read DMA interrupt is latched. This indicates that the scatter-gather list for the current write or read DMA has completed, but the associated interrupt has yet to be processed. A zero indicates that no write or read DMA interrupt is pending. PacketDoneLat is set at the end of each programmed transfer. The bit is cleared by writing back with the corresponding bit set. When the interrupt is enabled an interrupt is generated each time the status is set. If the interrupt is not enabled the SW can poll this bit to see when the transfer has completed and more data can be written, Channel Interrupt Active: When a one is read, it indicates that a system interrupt is potentially asserted caused by an enabled channel interrupt condition. A zero indicates that no system interrupt is pending from an enabled channel interrupt condition. The Board level master interrupt enable will also need to be asserted to allow the active channel interrupt to become an interrupt request. Local Interrupt: When a one is read, it indicates that any of the masked conditions other than DMA are active and enabled. Local Interrupt is or d with the DMA interrupt sources to create the Channel Interrupt Active signal and to request the Interrupt. The channel interrupt(s) are masked with the Master Interrupt Enable and driven to INTA on the PCI bus. System routing may re-route INTA onto another level by the time the CPU sees it. Your discovery software should handle the interrupt assignment for this card as part of initialization. E m b e d d e d S o l u t i o n s P a g e 2 2 o f 3 5

23 NVY5_CHAN_WR_DMA [0x58] Write DMA Pointer (write only) DMA Pointer Address Register Data Bit Description 31-2 First Chaining Descriptor Physical Address 1 direction [0] 0 end of chain Figure 12 Pc104pBiserial-III Write DMA pointer register This write-only port is used to initiate a scatter-gather write [TX] DMA. When the address of the first chaining descriptor is written to this port, the DMA engine reads three successive long words beginning at that address. Essentially this data acts like a chaining descriptor value pointing to the next value in the chain. The first is the address of the first memory block of the DMA buffer containing the data to read into the device, the second is the length in bytes of that block, and the third is the address of the next chaining descriptor in the list of buffer memory blocks. This process is continued until the end-of-chain bit in one of the next pointer values read indicates that it is the last chaining descriptor in the list. All three values are on LW boundaries and are LW in size. Addresses for successive parameters are incremented. The addresses are physical addresses the HW will use on the PCI bus to access the Host memory for the next descriptor or to read the data to be transmitted. In most OS you will need to convert from virtual to physical. The length parameter is a number of bytes, and must be on a LW divisible number of bytes. Status for the DMA activity can be found in the channel control register and channel status register. Notes: 1. Writing a zero to this port will abort a write DMA in progress. 2. End of chain should not be set for the address written to the DMA Pointer Address Register. End of chain should be set when the descriptor follows the last length parameter. 3. The Direction should be set to 0 for Burst In DMA in all chaining descriptor locations. E m b e d d e d S o l u t i o n s P a g e 2 3 o f 3 5

24 NVY5_CHAN_RD_DMA [0x5C] Read DMA Pointer (write only) DMA Pointer Address Register Data Bit Description 31-2 First Chaining Descriptor Physical Address 1 direction [1] 0 end of chain Figure 13 Pc104pBiserial-III Read DMA pointer register This write-only port is used to initiate a scatter-gather read [RX] DMA. When the address of the first chaining descriptor is written to this port, the DMA engine reads three successive long words beginning at that address. Essentially this data acts like a chaining descriptor value pointing to the next value in the chain. The first is the address of the first memory block of the DMA buffer to write data from the device to, the second is the length in bytes of that block, and the third is the address of the next chaining descriptor in the list of buffer memory blocks. This process is continued until the end-of-chain bit in one of the next pointer values read indicates that it is the last chaining descriptor in the list. All three values are on LW boundaries and are LW in size. Addresses for successive parameters are incremented. The addresses are physical addresses the HW will use on the PCI bus to access the Host memory for the next descriptor or to read the data to be transmitted. In most OS you will need to convert from virtual to physical. The length parameter is a number of bytes, and must be on a LW divisible number of bytes. Status for the DMA activity can be found in the channel control register and channel status register. Notes: 1. Writing a zero to this port will abort a write DMA in progress. 2. End of chain should not be set for the address written to the DMA Pointer Address Register. End of chain should be set when the descriptor follows the last length parameter. 3. The Direction should be set to 1 for Burst Out DMA in all chaining descriptor locations. E m b e d d e d S o l u t i o n s P a g e 2 4 o f 3 5

25 NVY5_CHAN_SW(R/W) [0x60] Write TX/Read RX FIFO Port RX and TX FIFO Port Data Bit Description 31-0 FIFO data word Figure 14 Pc104pBiserial-III RX/TX FIFO Port This port is used to make single-word accesses into the TX and out of the RX FIFO. Please note that reading is from the RX FIFO and writing is to the TX FIFO. Unless Bypass mode is established the data will not match. NVY5_CHAN_TX_AECNT [0x64] TX almost-empty level (read/write) TX Almost-Empty Level Register Data Bit Description Spare 15-0 TX FIFO Almost-Empty Level Figure 15 Pc104pBiserial-III TX ALMOST EMPTY LEVEL register This read/write port accesses the transmitter almost-empty level register. When the number of data words in the transmit data FIFO is less than this value, the almostempty status bit will be set. The register is R/W for 16 bits. The mask is valid for a size matching the depth of the FIFO. 8k x32 is the TX FIFO for a 13 bit valid count range [12-0]. NVY5_CHAN_RX_AFCNT [0x68] RX almost-full level (read/write) RX Almost-Full Level Register Data Bit Description Spare 15-0 RX FIFO Almost-Full Level Figure 16 Pc104pBiserial-III RX ALMOST FULL LEVEL register This read/write port accesses the receiver almost-full level register. When the number of data words in the receive data FIFO is greater than this value, the almost-full status bit will be set. The register is R/W for 16 bits. The mask is valid for a size matching the depth of the FIFO. 1k x32 is the RX FIFO for a 10 bit valid count range [9-0]. E m b e d d e d S o l u t i o n s P a g e 2 5 o f 3 5

26 NVY5_CHAN_TX_CNT [0x58] TX FIFO data count (read only) TX FIFO Data Count Port Data Bit Description Spare 15-0 TX Data Words Stored Figure 17 Pc104pBiserial-III TX FIFO data count Port This read-only register port reports the number of 32-bit data words in the transmit FIFO. The TX FIFO has a maximum of x1fff locations. NVY5_CHAN_RX_CNT [0x5C] RX FIFO data count (read only) RX FIFO Data Count Port Data Bit Description Spare 15-0 RX Data Words Stored Figure 18 Pc104pBiserial-III RX FIFO data count Port This read-only register port reports the number of 32-bit data words in the receive FIFO. The channel status register contains the combined pipeline and FIFO count. This design has 1027 locations possible in the FIFO + pipeline. NVY5_CHAN_TXSIZE [0x7C] Target Control Register R/W RX Address Port Data Bit Description Spare Width of DataReady 15-0 FIFO Count for DataReady Figure 19 Pc104pBiserial-III Target Control Port The TX FIFO count on the IO side [x16] is compared with the bottom word to determine E m b e d d e d S o l u t i o n s P a g e 2 6 o f 3 5

27 when enough data is in the FIFO to trigger sending a DataReady pulse. The Enable must also be set to trigger sending the pulse. The count should be an even quantity since it is the result of 32 data writes [2:1]. The width of the asserted pulse is controlled with the next byte. The period of 1 bit is the same as the IO clock received. It is a system issue to have that rate known. With a 10 MHz clock each bit is 100 ns and it takes 30 to make 3 us if that is your target. The counter starts from 0 so the actual value programmed is N-1. PCI-104 Notes PC104 is a stack oriented module system. PCI-104 uses the PCI interconnection and does not supply the ISA connector system. The PCI bus has separate CLOCK, IDSEL, RQST, GNT, and Interrupt for each of the 4 stack positions available. The dipswitch has 8 switches. Switches 2,1 are used to select the effective stack position. 00 selects the first position, 01 the second 11 the last. The hardware selects the corresponding set of signals to operate with. It is important to have unique settings for the boards in the stack. Once the configuration is selected and the OS in operation it is possible to freeze the switch choices [see base register definition] to allow the switch settings to be changed on the fly and see the result. E m b e d d e d S o l u t i o n s P a g e 2 7 o f 3 5

28 Loop-back The Engineering kit has reference software, which includes external loop-back tests. The Pc104pBiserial-III has a 50 pin ribbon cable connector. The tests require an external cable with the following pins connected. External NVY5 NVY6 function Loop-Back 1:1 cable The same pins are used on both sides of the interface to provide a simple ribbon cable interconnection between the NVY5 and NVY6 designs. For additional debugging support the IP-DEBUG-IO card can be used two ribbon cables are used to connect each of the NVY5/6 pair to the IP-Debug-IO card which has a header available to serve as testpoints. Both cards are supported with Win32 drivers and a combined userap that loads the NVY5 and reads from the NVY6 card using DMA. E m b e d d e d S o l u t i o n s P a g e 2 8 o f 3 5

29 PCI-104 Module Logic Interface Pin Assignment The figure below gives the pin assignments for thepci-104 Module PCI J3 Interface on the Pc104pBiserial-III. Pins may be assigned by the specification and not needed by this design. J3 A9 SERR* B10 PERR* C9 rsvd2 D9 PAR D10 rsvd1 D12 DEVSEL* C11 LOCK* A11 STOP* B12 TRDY* C13 IRDY* D28 RST* A13 FRAME* B30 REQ*3 B24 REQ*2 C23 REQ*1 A23 REQ*0 C30 GNT*3 C25 GNT*2 A25 GNT*1 D24 GNT*0 B28 INTD* D29 INTC* C29 INTB* B29 INTA* C27 CLK3 A27 CLK2 D26 CLK1 B26 CLK0 D19 IDSEL3 D18 IDSEL2 C18 IDSEL1 A18 IDSEL0 B19 CBE3 D14 CBE2 B8 CBE1 A4 CBE0 D22 AD31 B22 AD30 A21 AD29 C21 AD28 D21 AD27 B20 AD26 C20 AD25 A19 AD24 B17 AD23 C17 AD22 A16 AD21 B16 AD20 D16 AD19 A15 AD18 C15 AD17 B14 AD16 C8 AD15 A7 AD14 B7 AD13 D7 AD12 A6 AD11 C6 AD10 B5 AD9 C5 AD8 B4 AD7 D4 AD6 A3 AD5 C3 AD4 D3 AD3 B2 AD2 C2 AD1 D1 AD0 D6 M66EN M H 1 M H 2 A29 +12V VIO5 VIO4 VIO3 VIO2 VIO1 +5V8 +5V7 +5V6 +5V5 +5V4 +5V3 +5V2 +5V1 +3.3V V9 +3.3V8 +3.3V7 +3.3V6 +3.3V5 +3.3V4 +3.3V3 +3.3V2 +3.3V1 GND25 GND24 GND23 GND22 GND21 GND20 GND19 GND18 GND17 GND16 GND15 GND14 GND13 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 D23 C19 B25 B6 A2 A26 A22 B27 B21 C28 C24 D2 C1 D17 A17 B15 C14 D13 A12 B11 C10 D8 A8 D30 A1 A28 D27 C26 D25 A24 B23 C22 D20 A20 B18 C16 D15 A14 B13 C12 D11 A10 B9 C7 D5 A5 B3 C4 A30-12V J3 connector PC104 Figure 20 PC104pBiserial-III J3 Interface E m b e d d e d S o l u t i o n s P a g e 2 9 o f 3 5

30 PCI-104 Module Front Panel IO Interface Pin Assignment The figure below gives the pin assignments for the PC104p Module IO Interface on the Pc104pBiserial-III-NVY5. IO_0P GND* IO_0m Data0 1 2 IO_1P GND* IO_1m Data1 3 4 IO_2P GND* IO_2m Data2 5 6 IO_3P GND* IO_3m Data3 7 8 IO_4P GND* IO_4m Data IO_5P GND* IO_5m Data IO_6p GND* IO_6m Data IO_7p GND* IO_7m Data IO_8p GND* IO_8m Data IO_9p GND* IO_9m Data IO_10p GND* IO_10m Data IO_11p GND* IO_11m Data IO_12p GND* IO_12m Data IO_13p GND* IO_13m Data IO_14p GND* IO_14m Data IO_15p GND* IO_15m Data GND* GND* ADC0 TTL0 DataReady ADC1 TTL1 ReadEnable ADC2 TTL2 ClockIn ADC3 TTL3 Spare DAC0 TTL4 Spare DAC1 TTL5 Spare DAC2 TTL6 Spare DAC3 TTL7 Spare Figure 21 PC104PBISERIAL-III NVY5 IO Interface Analog IO are not implemented on this design GND* are tied together on rear of card for current version M side of IO is used for single ended TTL output E m b e d d e d S o l u t i o n s P a g e 3 0 o f 3 5

31 Applications Guide Interfacing The pin-out tables are displayed with the pins in the same relative order as the actual connectors. Some general interfacing guidelines are presented below. Do not hesitate to contact the factory if you need more assistance. Watch the system grounds. All electrically connected equipment should have a fail-safe common ground that is large enough to handle all current loads without affecting noise immunity. Power supplies and power-consuming loads should all have their own ground wires back to a common point. Power all system power supplies from one switch. Open Drain interface devices provide some immunity from, and allow operation when part of the circuit is powered on and part is not. It is better to avoid the issue of going past the safe operating areas by powering the equipment together and by having a good ground reference. Keep cables short. Flat cables, even with alternate ground lines, are not suitable for long distances. The Pc104pBiserial-III has optional transorbs for input protection. In addition series resistors are used and can be specified to be something other than the 22 ohm standard value. The connector is pinned out for a standard SCSI II/III cable to be used. It is suggested that this standard cable be used for most of the cable run. Terminal Block. We offer a high quality 50 screw terminal block that directly connects to the ribbon cable. The terminal block can mount on standard DIN rails. HDRterm50 [ ] We provide the components. You provide the system. Safety and reliability can be achieved only by careful planning and practice. Inputs can be damaged by static discharge, or by applying voltage outside of the particular device s rated voltages. E m b e d d e d S o l u t i o n s P a g e 3 1 o f 3 5

32 Construction and Reliability PC104 Modules were conceived and engineered for rugged industrial environments. Pc104pBiserial-III is constructed out of inch thick high temperature ROHS compliant material. The traces are matched length from the FPGA ball to the IO pin. Traces are tear dropped to provide the necessary strength in a compression mount connector system. Planes are designed to carry the rated current with minimal temperature rise. Surface mounted components are used. PCI-104 Module connectors are shrouded with Gold plated pins on both plugs and receptacles. They are rated at 1+ Amp per pin, 100 insertion cycles minimum. These connectors make consistent, correct insertion easy and reliable. To remove, gently rock the module to walk the connectors apart without excessive angles between the modules. The PCI-104 module is secured into the stack with standard PC104 stand-off s. The module is supplied with a set of 4 stand-off s. More are available for purchase if needed. The mounting holes for the stand-off s are grounded to help with stack cooling. The PCI-104 Module provides a low temperature coefficient of ~2.17 W/ o C for uniform heat. This is based upon the temperature coefficient of the base FR4 material of 0.31 W/m- o C, and taking into account the thickness and area of the PMC. The coefficient means that if ~2.17 Watts are applied uniformly on the component side, then the temperature difference between the component side and solder side is one degree Celsius. Thermal Considerations The PC104PBISERIAL-III design consists of CMOS circuits. The power dissipation due to internal circuitry is very low. It is possible to create higher power dissipation with the externally connected logic. If more than one Watt is required to be dissipated due to external loading; forced air cooling is recommended. With the one degree differential temperature to the solder side of the board external cooling is easily accomplished. PC104p-Cool and PC104p-RPP are available to provide cooling and reverse power protection should your system need those functions. E m b e d d e d S o l u t i o n s P a g e 3 2 o f 3 5

33 Warranty and Repair Please refer to the warranty page on our website for the current warranty offered and options. Service Policy Before returning a product for repair, verify as well as possible that the suspected unit is at fault. Then call the Customer Service Department for a RETURN MATERIAL AUTHORIZATION (RMA) number. Carefully package the unit, in the original shipping carton if this is available, and ship prepaid and insured with the RMA number clearly written on the outside of the package. Include a return address and the telephone number of a technical contact. For out-of-warranty repairs, a purchase order for repair charges must accompany the return. Dynamic Engineering will not be responsible for damages due to improper packaging of returned items. For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty. Out of Warranty Repairs Out of warranty repairs will be billed on a material and labor basis. The current minimum repair charge is $150. Customer approval will be obtained before repairing any item if the repair charges will exceed one half of the quantity one list price for that unit. Return transportation and insurance will be billed as part of the repair and is in addition to the minimum charge. For Service Contact: Customer Service Department Dynamic Engineering 150 DuBois St. Suite C Santa Cruz, CA fax support@dyneng.com E m b e d d e d S o l u t i o n s P a g e 3 3 o f 3 5

34 Specifications Logic Interface: PCI-104 Logic Interface [PCI] 32/33 Digital Parallel IO: CLK rates supported: Software Interface: Initialization: Access Modes: Access Time: Interrupt: Onboard Options: Interface Options: Dimensions: Construction: Temperature Coefficient: NVY5 interface: 16 bit parallel port transmit, Data Ready with programmable threshold, programmable width. Receive Read Enable and reference clock from external source [can use NVY6]. External Clock supplies system IO reference. Internal reference selected as default to allow stand-alone operation and testing. Control Registers, IO registers, IO Read-Back registers Programming procedure documented in this manual LW to registers, read-write to most registers Frame to TRDY 121 ns [4 PCI clocks] or burst mode DMA 1 word per PCI clock transferred. DMA interrupts, NVY5 function support All Options are Software Programmable 50 Pin box header Standard Single PCI-104 Module. Multi-Layer Printed Circuit, Through Hole and Surface Mount Components W/ o C for uniform heat across PCI-104 Power: 5V. Local supplies for 3.3, 2.5, 1.2 no +12/-12 E m b e d d e d S o l u t i o n s P a g e 3 4 o f 3 5

35 Order Information standard temperature range 0-70 ø C Pc104pBiserial-III-NVY6 PCI-104 Module with NVY5 interface, DMA support, 8Kx32 FIFO TX, 1Kx32 FIFO RX Order Options: -CC to add conformal coating -ET to add Industrial Temp [ ] -ROHS to add ROHS processing Related: PCIBPC104p: PCI to PCP104p adapter to allow installation of Pc104pBiserial-III into a PCI system. Bridged to allow a full stack of PC104p devices in a single PCI slot. HDRterm50: 50 position terminal block with two Ribbon cable connectors. Pc104pBiserial-III compatible. HDRribn50: 50 conductor Ribbon cable compatible with Pc104pBiserial-III. Pc104pBiserial-III-NVY6 : Receives data from NVY5 design, stores into FIFO, DMA to host. PLL for clock frequency selection. Receives Ready, generates clock and REN. IP-Debug-IO : Incorporates two ribbon cable connectors, and header can be used for testpoints between cards. Pc104p-Cool :Add 1 or 2 fans to your PC104 stack in a single height module. Pc104p-RPP :Add 1 fan and Reverse Power Protection to your PC104 stack in a single height module. All information provided is Copyright Dynamic Engineering E m b e d d e d S o l u t i o n s P a g e 3 5 o f 3 5