PCI Express Application Software

Transcription

1 PCI Express Application Software PCE3 and PCE Data Sheet PCE (Supports Gen 1/2) PCI Express 1.0 and 2.0 Characterization, Debug, and Compliance Testing Automated Measurements for PCI Express 1.x and 2.0 Base and CEM Measurements Jitter Decomposition of Random from Deterministic Jitter to give Better Insight into Critical PCI Express Design Challenges Up to 6.25 Gb/s Hardware Serial Triggering allows Triggering on Protocol Errors and Other Signal Anomalies (Requires Opt. PTD) Supports Dual-port Measurements (Clock and Data) Features & Benefits PCE3 PCI Express 3.0 (Supports Gen 1/2/3) Characterization, Debug, and Compliance Testing (also includes PCE Features and Benefits) Automated Support for PCI Express 3.0 Base and CEM Measurements within DPOJET Q-scale Extrapolation Support for Base Jitter Measurements Flexible Channel Modeling enables Measurements Comparison with Different Channels (Requires Opt. SLA Serial Data Link Analysis) Preconfigured Setups to Determine the Optimal Receiver Equalization Settingsasdefined in the PCI Express 3.0 PCE3 and PCE Quickly Validate Test Status with Comprehensive Reports including Detailed Pass/Fail Results Easily Reconfigure Existing Measurements to Create User-specified Test Parameters or Test Limits Flexible Probing Saves Time and Money by enabling the Acquisition of Multiple Measurement Types (Differential, Single Ended, and Common Mode) with the P7500 Series TriMode Probes Support for Multiple Plots and Measurement Configurations enables a Quick Comparison of the Same Acquired Data with Different Settings Applications PCI Express Electrical Testing for: PCI Express Silicon (Root Complexes, Endpoints, Switches, Bridges) Add-in Expansion Cards Motherboards Embedded Systems Express Module Express Card Mobile PCI Express Module (MXM) Manufacturing Test

2 Data Sheet PCE3 Base Measurement Suite. Tektronix provides the most comprehensive solutions to serve the needs of engineers designing PCI Express silicon and embedded systems as well as those validating the physical-layer compliance of PCI Express devices to the PCI Express Compliance Test. The Tektronix PCE3 and PCE applications and selected Tektronix oscilloscopes provide one-button testing for PCI Express measurements as specified by the PCI Express. PCE3 and PCE automate the measurements allowing engineers to perform the required tests efficiently and reliably right on their bench. Customers working on PCI Express 3.0 are provided with all features and capabilities of PCE when using PCE3. The Tektronix DPO/DSA/MSO70000 Series oscilloscopes with the PTD Protocol Decode and Analysis Software offers automated trigger and decode for PCI Express 1.x and 2.0. Serial Data Link Analysis (SDLA) software enables users to de-embed test fixtures for base specification measurements that are defined at the transmitter pins. For customers working on PCI Express compliance testing, SDLA provides complete support for channel modeling and receiver equalization. The DPO/DSA/MSO70000 Series oscilloscopes are designed to meet the challenges of the next generation of serial data standards such as PCI Express. These oscilloscopes provide the industry's leading vertical noise performance with the highest number of effective bits (ENOB) and flattest frequency response among oscilloscopes in their class. PCE3 PCI Express 3.0 Physical Layer Testing PCI Express 3.0 introduces new automated measurements for the base specification. New jitter measurements have been introduced which provide separate limits for data dependent (DDJ) and uncorrelated deterministic jitter (UDJDD). The data rate increase from 5 GT/s to 8 GT/s has lead to the PCE3 CEM Measurement Analysis before channel, after channel, after CTLE, and DFE. introduction of more advanced methods of compensating for channel loss with transmitter and receiver equalization. It is now important to separate DDJ which can be compensated with transmitter and receiver equalization and uncorrelated deterministic jitter which can be caused by effects such as crosstalk and power supply noise. PCE3 provides the complete set of PCI Express 3.0 jitter measurements enabling silicon designers to verify that their silicon meets the base specification requirements. Pulse Width Jitter (PWJ) is a new measurement that addresses the increased channel loss at 8 Gb/s. The purpose of the PWJ measurement is to ensure that lone bits meet minimum pulse width requirements. All new jitter measurement implement Q-scale extrapolation as defined in the base specification. Furthermore, the base specification requirements are defined at the pins of the transmitter. Before the measurements are computed the test channel must be de-embedded. De-embed filters can be easily created using Serial Data Link Analysis software (SDLA) and then quickly entered into the PCE3 base specification measurement setup and saved for future use. In addition to jitter, PCE3 also provides voltage, package loss, and transmitter equalization measurements. For compliance testing, PCE3 leverages the channel modeling and receiver equalization functionality of SDLA to support CEM measurements. Unlike other solutions, PCE3 provides full visibility to the signal as it has been modified to embed the compliance channel and provide receiver equalization. Eye diagrams and measurements can be set up to visually see the results of channel embedding, CTLE application, and DFE. For example when determining the optimal RX Equalization settings (CTLE setting and DFE tap value) the customer can quickly view the resulting eye diagrams and measurements to see the effects of post processing the acquired signal. Compliance measurements can then be taken on the waveform. 2

3 PCI Express Application Software PCE3 and PCE PCI Express 2.0 CEM System Measurements. PCE PCI Express 1.x/2.0 Physical Layer Testing PCE accelerates the analysis, validation, and precompliance testing of designs based on PCI Express 1.x and 2.0. PCE provides the flexibility to check devices for precompliance or perform device characterization or debug in a single software package. Multiple measurement test points are available providing the broadest range of testing for PCI Express. Silicon can quickly be verified at the Tx pins to ensure base specification compliance, add-in cards and systems can be measured to support precompliance testing, and other form factors including Mobile PCI Express Module (MXM) and Express Card can be verified to meet the requirements of those specifications. These specifications are critical to provide higher margins to meet the requirements of all versions of PCI Express and provide the most accurate measurement results for design characterization. PCIe compliance pattern decoded with Protocol Trigger and Decode (PTD). PTD PCI Express Triggering and Analysis (8b/10b) Fast Isolation of Protocol Events with Protocol Triggering and Decode Highlight Character or Disparity Errors Real-time hardware-based trigger up to 6.25 Gb/s PCI Express Serial Triggering and Analysis Protocol errors, for example disparity and character errors, can be quickly identified in real time at full speed (up to 6.25 Gb/s) with the Protocol Triggering and Decode (PTD) software. Real-time event isolation ensures the point of interest can be easily located without trial and error to capture the event of interest. Additionally, PTD can be used to trigger on the compliance pattern to ensure that the device under test is in Compliance mode before beginning the compliance test. In many cases the root cause of protocol errors is due to electrical-layer problems. For example, a character error caused by a glitch can be easily identified with PTD because the 8b/10b decoded signals are correlated in time with the analog waveform. Refer to the Protocol Trigger and Decode application data sheet for additional details. 3

4 Data Sheet Complete Visibility of the Physical and Logic Layers The comprehensive, integrated Tektronix tool set combines oscilloscopes with the TLA7S00 logic analyzer modules to provide complete visibility of the PCIe physical and logical layers. The combination of the two solutions allows for PCI Express digital debug and validation, analog validation, compliance testing, and device characterization. Together, they enable the designer to resolve PCI Express design challenges quickly and efficiently. Comprehensive Measurements for PCIe Validation, Debug, and Precompliance Option PCE provides measurements that span multiple test points and versions of the PCIe specification. All PCIe specifications, test points, and measurements supported are listed below. Option PCE Provides Coverage for a Broad Set of PCIe s and Test Points Test Method Spec Revision PCI Express Title Rev 1.1 Rev 3.0 Test Points Defined Rev 1.1 Base Transmitter and Receiver Rev 1.1 CEM System and Add-in Card Reference Clock Rev 1.0 Express Module Transmitter Path and System Board Rev 1.0 Ver. 3.0 Rev 1.1 Rev 1.0 PCMCIA Express Card Standard Mobile PCI Express Module (MXM) Electromechanical External Cabling Host System Transmitter Express Card Transmitter PCI Express Transmitter and Receiver Path Base Transmitter and Receiver Mobile Low-power Transmitter CEM System and Add-in Card(3.5and6dB de-emphasis) Ver. 3.0 Rev 1.1 Mobile PCI PCI Express Express Module (MXM) Electromechanical Rev 1.0 Base Transmitter Rev 0.7 CEM System and Add-in Card 4

5 PCI Express Application Software PCE3 and PCE Characteristics Supported Base Measurements Differential 8 GT/s Transmitter (Tx) Output Measurements (PCE3 Only) Parameter Symbol TxVoltagewithNoTx PCIe V-TX-NO-EQ Equalization Minimum Swing during EIEOS PCIe V-TX-EIEOS Pseudo Package Loss PCIe ps21tx Data-dependent Jitter PCIe T-TX-DDJ Tx Uncorrelated Deterministic PCIe T-TX-UDJDD Jitter Tx Uncorrelated Total Jitter PCIe T-TX-UTJ Deterministic DjDD PCIe T-TX-UPW-DJDD Uncorrelated Pulse Width Jitter Total Uncorrelated Pulse Width PCIe T-Tx-TX-UPW-TJ Jitter Differential Transmitter (Tx) Output Measurements Parameter Symbol(s) 2.5 GT/s 5GT/s Specified Specified Differential p-p Tx Voltage Swing Low-power Differential p-p Tx Voltage Swing De-emphasized Output Voltage Ratio Instantaneous Lane Pulse Width Transmitter Eye including All Jitter Sources Maximum Time between the Jitter Median and Maximum Deviation from the Median V TX-DIFF-P-P V TX-SWING V TX-EYE-FULL Specified Specified V TX-SWING-LOW Specified Specified V TX-EYE-HALF V TX-DE-RATIO Not Specified Specified T MIN-PULSE Not Specified Specified T TX-EYE Specified Specified T TX-EYE-TJ T TX-EYEMEDIAN-to-MAXJITTER Specified Specified Deterministic Jitter T TX-DJ-DD Not Specified Specified Tx RMS Jitter T TX-LF-RMS Not Specified Specified <1.5 MHz D+/D Tx Output T TX-RISE Specified Specified Rise/Fall Time T TX-FALL Tx Rise/Fall T RF-MISMATCH Not Specified Specified Mismatch AC Common Mode V TX-CM-AC-PP Not Specified Specified Output Voltage AC Common Mode V TX-CM-AC-P Specified Specified Output Voltage Absolute Delta of DC Common Mode Voltage between D+ and D V TX-CM-DC-LINE-DELTA Specified Specified Differential Receiver (Rx) Input Measurements Parameter Symbol(s) 2.5 GT/s 5GT/s Not Specified Specified Minimum Receiver V RX_EYE Specified Specified Eye Height Minimum Receiver V RX_EYE Specified Specified Eye Width Receiver T RX_DJ_DD Not Specified Specified Deterministic Jitter DJ Minimum Width T RX-MIN-PULSE Not Specified Specified Pulse at Rx Maximum Time T TX-EYEMEDIAN-to-MAXJITTER Specified Not Specified between the Jitter Median and Maximum Deviation from the Median Rx AC Common Mode Voltage V RX-CM-AC-P Specified Specified Supported CEM Measurements Add-in Card Transmitter Path Compliance Measurements (PCE3 Only) Parameter Symbol Transition Eye Voltage Nontransition Eye Voltage Eye Width PCIe V-TXA PCIe V-TXA-d PCIe T-TXA Add-in Card Transmitter Path Compliance Measurements Parameter Symbol(s) 2.5 GT/s 5GT/s Specified Specified Eye Height of V TXA Specified Specified Transition Bits Eye Height of V TXA_d Specified Specified Nontransition Bits Eye Width with T TXA in Rev 1.1 Specified Not Specified Sample Size of 10 6 UI Jitter Eye Opening T TXA in Specified Specified at BER Maximum J TXA-MEDIAN-to-MAX-JITTER Specified Not Specified Median-Max Jitter Outlier with Sample Size of 10 6 UI Total Jitter at TJ at BER Not Specified Specified BER Deterministic Jitter at BER Max DJ Not Specified Specified 5

6 Data Sheet System Board Transmitter Path Measurements Parameter Symbol(s) 2.5 GT/s 5GT/s Specified Specified Eye Height of V TXS Specified Specified Transition Bits Eye Height of V TXS_d Specified Specified Nontransition Bits Eye Width with T TXS in Rev 1.1 Specified Not Specified Sample Size of 10 6 UI Jitter Eye Opening T TXS in Specified Specified at BER Maximum J TXA-MEDIAN-to-MAX-JITTER Specified Not Specified Median-Max Jitter Outlier with Sample Size of 10 6 UI Total Jitter at TJ at BER Not Specified Specified BER Deterministic Jitter at BER Max DJ Not Specified Specified Reference Clock Measurements Parameter Symbol 2.5 GT/s Reference Clock Phase Jitter at BER 10 6 NA Specified PCI ExpressModule Measurements ExpressModule Add-in Card Transmitter Path Measurements Parameter Symbol Rev 1.0 EyeHeightofTransitionBits V TXA Specified Eye Height of Nontransition Bits V TXA_d Specified Eye Width with Sample Size of 10 6 UI T TXA Specified in Rev 1.1 Jitter Eye Opening at BER NA Specified Maximum Median-Max Jitter Outlier with Sample Size of 10 6 UI J TXA-MEDIAN-to-MAX-JITTER Specified ExpressModule System Board Transmitter Path Measurements Parameter Symbol Gen1 Rev 1.0 EyeHeightofTransitionBits V TXS Specified Eye Height of Nontransition Bits V TXS_d Specified Eye Width with Sample Size of 10 6 UI T TXS Specified Jitter Eye Opening at BER NA Specified Maximum Median-Max Jitter Outlier with Sample Size of 10 6 UI J TXA-MEDIAN-to-MAX-JITTER Specified PCI Express External Cabling Measurements External Cabling Transmitter Path Measurements Parameter Symbol Rev 1.0 EyeHeightofTransitionBits V TXA Specified Eye Height of Nontransition Bits V TXA_d Specified Jitter Eye Opening at BER TrxA at BER Specified Eye Width with Sample Size of 10 6 UI TrxA at 10 6 Samples Specified External Cabling Receiver Path Measurements Parameter Symbol Gen1 Rev 1.0 EyeHeightofTransitionBits V RXA Specified Eye Height of Nontransition Bits V RXA_d Specified Jitter Eye Opening at BER TrxA at BER Specified Eye Width with Sample Size of 10 6 UI TrxA at 10 6 Samples Specified PCMCIA ExpressCard Measurements ExpressCard Module Transmitter Path Measurements Parameter Symbol Release 1.0 EyeHeightofTransitionBits V TXA Specified Eye Height of Nontransition Bits V TXA_d Specified Eye Width across Any 250 UIs T TXA Specified ExpressCard Host System Transmitter Path Measurements Parameter Symbol Release 1.0 EyeHeightofTransitionBits V txs Specified Eye Height of Nontransition Bits V txs_d Specified Eye Width across Any 250 UIs T TxS Specified MXM Measurements PCI Express Measurements* 1 Parameter Symbol Release 1.1 EyeHeightofTransitionBits V TXS Specified Eye Height of Nontransition Bits V TXS_d Specified Width at BER T TXS Specified Deterministic Jitter DJ Specified Total Jitter TJ Specified * 1 All de-emphasis levels supported. 6

7 PCI Express Application Software PCE3 and PCE Ordering Information Recommended DPO/DSA/MSO70000 Series oscilloscopes 2.5 Gb/s (PCI Express 1.0/1.1): DPO/DSA/MSO70000 Series (6 GHz or higher bandwidth models) 5.0 Gb/s (PCI Express 2.0): DPO/DSA/MSO70000 Series (12.5 GHz or higher bandwidth models) 8.0 Gb/s (PCI Express 3.0): DPO/DSA/MSO70000 Series (16 GHz or higher bandwidth models, minimum of 12.5 GHz is recommended) PCE3* 2 PCI Express 3.0/2.0/1.x Physical-layer Test Application. Model New Instrument Orders Product Upgrades Floating Licenses DPO/DSA/MSO70K Series Opt. PCE3 Opt. DPO-UP PCE3 Opt. DPOFL-PCE3 * 2 Requires Option DJA (DPOJET Jitter and Eye Diagram Analysis) and SLA (Serial Data Link Analysis Advanced). DJA is standard on DSA70K Series oscilloscopes. PCE* 3 PCI Express 2.0/1.x Physical-layer Test Application. Model New Instrument Orders Product Upgrades Floating Licenses DPO/DSA/MSO70K Series Opt. PCE Opt. DPO-UP PCE Opt. DPOFL-PCE * 3 Requires Option DJA. DJA is standard on DSA70K Series oscilloscopes. Recommended Accessories Order Opt. ST6G P7500 Series Description Protocol Triggering and Decoding for 8b/10b-encoded Serial Signals up to 6.25 Gb/s. Includes hardware clock recovery and pattern lock triggering TriMode Differential Probe Recommended Test Fixtures Order Description CLB1* 4 CBB1* 4 CLB2* 4 CLB2* 4 Matched SMA Cables SMP-SMA Cables* 5 CLB2/CBB2 Terminators* 5 PCI Express Compliance Load Board (CLB) for testing PCI Express platforms Rev 1.1 of the PCI Express Compliance Base Board (CBB) for testing PCI Express Add-in Cards of the PCI Express Compliance Base Board (CBB) for testing PCI Express Add-in Cards (Supports testing of ) PCI Express Compliance Load Board (CLB) for testing PCI Express platforms (Supports testing of ) xx 71M-19K1-32S A 19K15R-001E4 * 4 Available from PCI-SIG ( * 5 Available from Rosenberger ( Additional Information Tektronix offers a range of solutions for PCI Express testing. To see a comprehensive listing, including the BERTScope BSA Series for Receiver Testing and the DSA8300 for Channel De-embedding, visit PCE and PCE3 solution updates and up-to-date instrument software upgrades are available at Tektronix is registered to ISO 9001 and ISO by SRI Quality System Registrar. Product(s) complies with IEEE Standard , RS-232-C, and with Tektronix Standard Codes and Formats. 7

8 Data Sheet Contact Tektronix: ASEAN / Australasia (65) Austria * Balkans, Israel, South Africa and other ISE Countries Belgium * Brazil +55(11) Canada Central East Europe and the Baltics Central Europe & Greece Denmark Finland France * Germany * Hong Kong India Italy * Japan 81 (3) Luxembourg Mexico, Central/South America & Caribbean 52 (55) Middle East, Asia, and North Africa The Netherlands * Norway People s Republic of China Poland Portugal Republic of Korea Russia & CIS +7 (495) South Africa Spain * Sweden * Switzerland * Taiwan 886 (2) United Kingdom & Ireland * USA * European toll-free number. If not accessible, call: Updated 10 February 2011 For Further Information. Tektronix maintains a comprehensive, constantly expanding collection of application notes, technical briefs and other resources to help engineers working on the cutting edge of technology. Please visit Copyright Tektronix, Inc. All rights reserved. Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material. and price change privileges reserved. TEKTRONIX and TEK are registered trademarks of Tektronix, Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies. 08 Feb W