Mask Set Errata for Mask 1N87P

Transcription

1 NXP Semiconductors SAC57D54H_1N87P Mask Set Errata Rev. 3, Apr 2017 Mask Set Errata for Mask 1N87P This report applies to mask 1N87P for these products: SAC57D54H Table 1. Errata and Information Summary Erratum ID e10835 e8962 e9629 e10327 e9656 e10755 e8004 e7991 e8341 e9265 e8951 e10526 e9156 e7274 e10379 e10377 e10265 e9250 Erratum Title 2D-ACE: Incorrect values may be read while reading Heads Up Display registers 2D-ACE: Layers using RLE 16bpp compressed data require a byte swap 2D-ACE: Spurious generation of writeback underrun flag with HUD operation ADC: Incorrect channel under measure is indicated after sampling phase of conversion until conversion completes DSPI: Frame transfer does not restart in case of SPI parity error in master mode DSPI: Transmit and Receive FIFO fill flags in status register is not cleared when DMA is improperly configured FLASH: Array Integrity with Breakpoints enabled may skip addresses for certain RWSC and APC combinations FLASH: Rapid Program or Erase Suspend fail status FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating. FTM: Incorrect match may be generated if intermediate load feature is used in toggle mode I2C: Attempting a start cycle while the bus is busy may generate a short clock pulse IOP_modes: IOP Modes and related mode transition features are not supported. LDB: OpenLDI 18-bit SPWG mode does not work correctly LINFlexD: Consecutive headers received by LIN Slave triggers the LIN FSM to an unexpected state MC_ME: Mode transition from DRUN/RUN mode to STANDBY may not complete if any Low Voltage Detect or Power-On Reset event is asserted during a susceptibility window MC_ME: Mode transition from DRUN/RUN mode to STANDBY will not complete if a wakeup event is triggered in a 50ns window MC_ME: Wakeup event while transitioning to a low power mode may cause the Mode Transition Status bit to remain asserted PASS: JTAG password not working during reset Table continues on the next page...

2 Table 1. Errata and Information Summary (continued) Erratum ID e10590 e10170 e9461 e8950 e10202 e8799 e9658 e9214 e9892 e9114 Erratum Title PLL: Might remain unlocked when enabled after Standby or power on QuadSPI: Insufficient read data may be received in the RX Data Buffer register QuadSPI: Read data errors may occur with data learning in 4x sampling method RLE_DEC: edma transaction may not finish correctly on certain conditions RTC: Software update of Time of Day register (RTC_TOD) might cause the internal counters to sample invalid values SGM: 8-bit writes to FIFORP register incorrectly clears/flushes all channels SPI: Inconsistent loading of shift register data into the receive FIFO following an overflow event SPI: Only 16 bits are accessible on the SPI_PUSHR_SLAVE register STCU: System not able to handle PLL Loss of Lock event during offline/online selftest XRDC:Illegal values written to MRGD_W2[SNUM] and PDAC_W0[SNUM] will result is undefined behavior. Table 2. Revision History Revision 0 Initial revision 1 The following errata were added. e10202 e10170 e10377 e10379 e10265 e The following errata were removed. e8759 e9386 Changes The following errata were added. e10590 e , Apr 2017 The following errata were removed. e10542 The following errata were added. e10526 e10755 e NXP Semiconductors

3 e10835: 2D-ACE: Incorrect values may be read while reading Heads Up Display registers Description: The 2D ACE block has a functionality of supporting Heads up display. There are registers related to Heads up display functionality (0x5000 0x5020) integrated within the IP. Reading these registers might return incorrect values. Workaround: Software must not rely on read back values from these registers. e8962: 2D-ACE: Layers using RLE 16bpp compressed data require a byte swap Description: When using Run Length Encoding (RLE) mode on a layer from the Display Controller (2D- ACE) with a 16bpp format (RGB565, ARGB1555, ARGB4444, APAL8), the pixel values will appear incorrect because the compressed data requires a byte swap before compression, compared to uncompressed 16bpp formats. Workaround: The RLE compression of images is usually performed on a computer or external host. If the RLE compressed images will be used on 2D-ACE layers, perform a byte swap operation for each 16bit pixel value on the image before performing the RLE compression. For example, when not using RLE (raw data) a pixel value may be 0x00,0xFF. When using RLE mode on a layer, that pixel needs to be reordered to 0xFF,0x00 and then RLE compression can be applied to obtain the same output as in raw mode. e9629: 2D-ACE: Spurious generation of writeback underrun flag with HUD operation Description: When writeback operation is enabled with HUD operation, a false writeback underrun event is generated if the HUD descriptor has a different segment for last pixel of the last HUD line in comparison to the penultimate pixel. In such a case, the image is correctly written back to the system memory but writeback done flag is not set while writeback underrun is generated. Workaround: The tool used to generate the HUD descriptor should ensure that the last pixel of the last line is in the same segment as the penultimate pixel. e10327: ADC: Incorrect channel under measure is indicated after sampling phase of conversion until conversion completes Description: The Main Status Register Channel under measure address field (ADC_MSR[CHADDR]) indicates which ADC channel is currently performing a conversion. This field indicates the correct channel during the sampling phase of conversion, but will display an incorrect value in the subsequent phases until conversion is complete. Workaround: User must only consider ADC_MSR[CHADDR] to be valid when the ADC is in the sample phase of conversion. The Main Status Register Status of the ADC field shows when the ADC is in the sample phase (ADC_MSR[ADCSTATUS] = 0b100). NXP Semiconductors 3

4 e9656: DSPI: Frame transfer does not restart in case of SPI parity error in master mode Description: In the Deserial Serial Peripheral Interface (DSPI) module, in the scenario when: 1. Master/slave mode select bit (MTSR) of Module Configuration register (MCR) is set (MCR[MSTR]=0b1) to configure the module in master mode 2. SPI communication is selected via DSPI Configuration field (DCONF) in MCR (MCR[DCONF] = 0b00) 3. Parity reception check on received frame is enabled by setting the Parity Enable or Mask tasc delay (PE_MASC) bit of DSPI PUSH FIFO Register In Master Mode (PUSHR), i.e. PUSHR[PE]=0b1. 4. Parity Error Stop bit (PES) of MCR is set (MCR[PES]=0b1) which stops SPI frame transfer in case of parity error 5. Parity error is detected on received frame. Then the next frame transfer is stopped, the SPI Parity Error Flag bit (SPEF) of the DSPI Status Register (DSPI_SR) is set (SR[SPEF] =0b1) and the corresponding SPI parity error interrupt is asserted. Even after the interrupt is serviced and SR[SPEF] is reset, the frame transfer does not restart. Workaround: Do not use SPI frame transfer stop in case of parity error detection for SPI transmission in master mode. For this, keep the Parity Error Stop bit of Module Configuration Register deasserted (MCR[PES] = 0b0). e10755: DSPI: Transmit and Receive FIFO fill flags in status register is not cleared when DMA is improperly configured Description: The Deserial/Serial Peripheral Interface Transmit and Receive First In/First Out (FIFO) buffers can request additional information to be transferred via the Direct Memory Access (DMA) module when either the Transmit or Receive FIFO Fill/Drain Flags are set in the DSPI Status Register (SR[TFFF/RFDF]). However, the Transmit Fill Flag indicates that at least 1 location each (2 bytes each) in the Transmit and Command FIFOs is available to be written. It does not indicate that the FIFO is empty. Similarly, Receive FIFO fill flag only indicates at least 1 location (2 bytes) of the FIFO is available to be read. It does not indicate that the FIFO is full. If the DMA is configured to transfer more than 1 FIFO location size of data, the FIFO Fill/Drain Flags may not be properly cleared indicating that the FIFO is not full even when the FIFO is actually full (for Transmit FIFO) and not empty when the FIFO is actually empty (for Receive FIFO). Workaround: Properly configure the DMA to fill/drain only 2 bytes to Transmit, Command and Receive FIFOs. Use the DMA loop to transfer more data if needed. e8004: FLASH: Array Integrity with Breakpoints enabled may skip addresses for certain RWSC and APC combinations Description: For certain combinations of the Flash Read Wait State Control (RWSC) and Address Pipeline Control (APC) settings in the Platform Flash Configuration Register (PFLASH_PCFR1) the Flash s array integrity (AI) check when run with breakpoints enabled may skip addresses 4 NXP Semiconductors

5 resulting in an incorrect Multiple Input Signature Register (MISR) value or in the case of back to back ECC event errors (EER) or Single Bit Correction (SBC) events, a skipped breakpoint. This occurs for the following combinations: RWSC=1 and APC=1 RWSC=3 and APC=2 RWSC=5 and APC=3 If breakpoints are enabled and an EER or SBC cause a breakpoint to occur the address after the breakpoint will be skipped, and the resulting MISR will not match expectations. Likewise, if there are back to back errors (EER or SBC) during AI with the above RWSC/APC combinations the 2nd error (and breakpoint) will be missed. Margin Read (which by specification is a self timed event and is independent of wait states selected) is not affected by this erratum. This erratum only applies to Array Integrity. Workaround: One workaround is to follow the recommended RWSC and APC combinations for given frequencies. If this is done, Array Integrity with Breakpoints feature works as expected. Valid RWSC/APC combinations listed in the specification are: Flash Operating Frequency RWSC APC 30 MHz MHz MHz MHz MHz 5 2 A second workaround is if the above RWSC and APC combinations (listed in the description) are desired to be checked, do so without enabling breakpoints. In this case, the first EER or SBC event will be logged, and the MISR will correctly reflect the result of all reads being executed. e7991: FLASH: Rapid Program or Erase Suspend fail status Description: If a flash suspend operation occurs during a 5us window during a verify operation being executed by the internal flash program and erase state machine, and the suspend rate continues at a consistent 20us rate after that, it is possible that the flash will not exit the program or erase operation. A single suspend during a single program or erase event will not cause this issue to occur. Per the flash specification, a flash program or erase operation should not be suspended more than once every 20 us, therefore, if this requirement is met, no issue will be seen. IF the suspend rate is faster than 20 us continuously, a failure to program/erase could occur. Workaround: When doing repeated suspends during program or erase ensure that suspend period is greater than 20us. NXP Semiconductors 5

6 e8341: FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating. Description: In the Flexible Controller Area Network (FlexCAN) module, if the Freeze Enable bit (FRZ) in the Module Configuration Register (MCR) is asserted and the Freeze Mode is requested by asserting the Halt bit (HALT) in MCR, in some cases, the Freeze Mode Acknowledge bit (FRZACK) in the MCR may never be asserted. In addition, the Low-Power Mode Acknowledge bit (LPMACK) in the MCR may never be asserted in some cases when the Low-Power Mode is requested. Under the two scenarios described above, the loss of ACK assertion (FRZACK, LPMACK) causes a lock condition. A soft reset action is required in order to remove the lock condition. The change from Normal Mode to Low-Power Mode cannot be done directly. Instead, first change mode from Normal to Freeze Mode, and then from Freeze to Low-Power Mode. Workaround: To avoid the lock condition, the following procedures must be used: A) Procedure to enter in Freeze Mode: 1. Set both the Freeze Enable bit (FRZ) and the Halt bit (HALT) in the Module Control Register (MCR). 2. Check if the Module Disable bit (MDIS) in MCR register is set. If yes, clear the MDIS bit. 3. Poll the MCR register until the Freeze Mode Acknowledge bit (FRZACK) in MCR is set or the timeout is reached (see NOTE below). 4. If the Freeze Mode Acknowledge bit (FRZACK) is set, no further action is required. Skip steps 5 to If the timeout is reached because the Freeze Mode Acknowledge bit (FRZACK) is still cleared, then set the Soft Reset bit (SOFTRST) in MCR. 6. Poll the MCR register until the Soft Reset bit (SOFTRST) bit is cleared. 7. Reconfigure the Module Control Register (MCR) 8. Reconfigure all the Interrupt Mask Registers (IMASKn). After Step 8, the module will be in Freeze Mode. NOTE: The minimum timeout duration must be equivalent to: a) 730 CAN bits if the CAN FD Operation Enable bit (FDEN) in MCR is set (CAN bits calculated at arbitration bit rate), b) 180 CAN bits if the FDEN bit is cleared. B) Procedure to enter in Low-Power Mode: 1. Enter in Freeze Mode (execute the procedure A). 2. Request the Low-Power Mode. 3. Poll the MCR register until the Low-Power Mode Acknowledge (LPMACK) bit in MCR is set. 6 NXP Semiconductors

7 e9265: FTM: Incorrect match may be generated if intermediate load feature is used in toggle mode Description: When a channel (n) match is used as an intermediate reload, an incorrect second match may occur immediately following the correct match. The issue is problematic only if channel (n) is configured for output compare with the output configured to toggle mode. In this scenario, channel (n) toggles on the correct match and again on the incorrect match. The issue may also occur if a certain channel has a match which is coincident with an intermediate reload point of any other channel. Workaround: If any channel is configured for output compare mode with the output set for toggle mode, the intermediate reload feature must not be used. e8951: I2C: Attempting a start cycle while the bus is busy may generate a short clock pulse Description: When the I2C (Inter-Integrated Circuit) is operating in a multi-master network and a start cycle is attempted by the I2C device when the bus is busy, the attempting master will lose arbitration as expected but a short extra clock cycle is generated in the bus. After losing arbitration, the master switches to slave mode but it does not detect the short clock pulse. The acknowledge signal is expected at the ninth clock by the current bus master but it is not sent as expected due to the undetected short clock pulse. Workaround: Software must ensure that the I2C BUS is idle by checking the bus busy bit in the I2C Bus Status Register (I2C_IBSR.IBB) before switching to master mode and attempting a Start cycle. e10526: IOP_modes: IOP Modes and related mode transition features are not supported. Description: IOP Modes and related mode transition features are not supported. Workaround: The user must not use the IOP mode and related mode transitions. Any reference to IOP mode(s) and related mode transition must be ignored. Please contact your NXP representative for further details. e9156: LDB: OpenLDI 18-bit SPWG mode does not work correctly Description: When the device is configured to work in 18 bit SPWG Mode, the LVDS Display Bridge (LDB) incorrectly selects the least significant 18 bits of the output bus rather than the 6 most significant bits from each color component. Workaround: Configure the Module in 24 bit JEIDA mode and do not use the last line (TX3) from the OpenLDI module. By doing this the module behaves exactly as required in SPWG 18-bit mode. NXP Semiconductors 7

8 e7274: LINFlexD: Consecutive headers received by LIN Slave triggers the LIN FSM to an unexpected state Description: As per the Local Interconnect Network (LIN) specification, the processing of one frame should be aborted by the detection of a new header sequence and the LIN Finite State Machine (FSM) should move to the protected identifier (PID) state. In the PID state, the LIN FSM waits for the detection of an eight bit frame identifier value. In LINFlexD, if the LIN Slave receives a new header instead of data response corresponding to a previous header received, it triggers a framing error during the new header s reception and returns to IDLE state. Workaround: The following three steps should be followed - 1) Configure slave to Set the MODE bit in the LIN Time-Out Control Status Register (LINTCSR[MODE]) to 0. 2) Configure slave to Set Idle on Timeout in the LINTCSR[IOT] register to 1. This causes the LIN Slave to go to an IDLE state before the next header arrives, which will be accepted without any framing error. 3) Configure master to wait for Frame maximum time (T Frame_Maximum as per LIN specifications) before sending the next header. Note: THeader_Nominal = 34 * TBit TResponse_Nominal = 10 * (NData + 1) * TBit THeader_Maximum = 1.4 * THeader_Nominal TResponse_Maximum = 1.4 * TResponse_Nominal TFrame_Maximum = THeader_Maximum + TResponse_Maximum where TBit is the nominal time required to transmit a bit and NData is number of bits sent. e10379: MC_ME: Mode transition from DRUN/RUN mode to STANDBY may not complete if any Low Voltage Detect or Power-On Reset event is asserted during a susceptibility window Description: Power-On Reset (PORST) will NOT cause this issue if masked (UTEST_MISC[MASK_PORST] = 1, default: masked) From power-up to DRUN there is a window (50 ns typical) at which time if any of the Low Voltage Detects (LVDs) are asserted, the mode transition will not complete. (Window #1) From DRUN/RUNx to STANDBY transition there is a window (50 ns typical) at which time if the External Reset (EXR) is asserted, the mode transition will not complete. The window occurs in the STANDBY entry transition period (60 µs typical) - this period is from the mode transition request at the Mode Control Register (MC_ME_MCTL) to a toggle of the External Regulator Control pin (EXTREGC). The EXTREG pin signals the low power transition is complete. (Window #2) Upon wake-up at exit from STANDBY there is a single window (50 ns typical) at which time if any of the LVDs are asserted, the mode transition will not complete. This window occurs in the STANDBY exit transition period (12 µs typical) immediately after assertion of the wake-up signal. (Window #3) 8 NXP Semiconductors

9 For the case the mode transition does not complete the MCU will be stuck in reset (Window #1) or stuck in STANDBY (Window #2 and #3) and will only recover via a power-cycle of VDDE_A. Workaround: Ensure that any Low Voltage Detect or Power-On Reset (LVD / PORST) is not triggered during the windows of susceptibility at Power-up, at the entry to STANDBY mode or at the exit of STANDBY (window #1, window #2 and window #3 respectively). e10377: MC_ME: Mode transition from DRUN/RUN mode to STANDBY will not complete if a wakeup event is triggered in a 50ns window Description: While transitioning from DRUN/RUNx to STANDBY there is a susceptibility window (50 ns typical) at which if a wake-up event occurs the mode transition will not complete. The window occurs in the STANDBY entry transition period (60 µs typical) - this period is from the mode transition request at the Mode Control Register (MC_ME_MCTL) to a toggle of the External Regulator Control pin (EXTREGC). The EXTREGC pin signals the low power transition is complete. For the case the mode transition does not complete the MCU will be stuck in STANDBY and will only recover via a power-cycle of VDDE_A. Workaround: Ensure wake-ups are not triggered in the STANDBY entry transition period during the DRUN to STANDBY mode transition by adhering to all of the following guidelines: 1. If the application cannot guarantee to avoid triggering a wake-up event during the STANDBY entry transition period, prior to entering STANDBY mode all external wake-ups must be disabled. 2. Application SW should use a periodic wake-up (e.g. Real Time Clock Autonomous Periodic Interrupt) and poll the Wake-up Status register (WKPU_WISR). If a wake-up is recorded at WKPU_WISR this signals to the application SW that an external wake-up has occurred whilst in STANDBY mode. 3. The RTC-API timer must not timeout during the STANDBY entry transition period. e10265: MC_ME: Wakeup event while transitioning to a low power mode may cause the Mode Transition Status bit to remain asserted Description: While transitioning to a low power mode, if a wakeup interrupt event occurs between writing the Mode Control Register (MC_ME_MCTL) and executing a Wait For Interrupt (WFI) instruction, the low power mode transition will abort but the Mode Transition Status bit in the Global Status Register (MC_ME_GS[S_MTRANS]) will remain asserted. The Mode Transition Status bit signals when a mode transition is ongoing. If the application software is polling this bit, it can cause an indefinite stall of the application. Workaround: Workaround 1: To avoid stalling of the application while waiting on the Mode Transition Status bit to be cleared, the Software Watchdog (SWT) should be enabled before starting the mode transition, this is achieved by setting the Watchdog Enable bit in the Software Watchdog Control Register (SWT_CR[WEN]). The SWT will issue a reset in case the device stalls waiting for the Mode Transition Status bit to be cleared. NXP Semiconductors 9

10 Once in low power mode, If an interrupt by the SWT event is not desired, the Slow Internal RC Oscillator (SWT clock source) can be disabled in the target low power mode. In case the target mode is StandBy0 disabling the Slow Internal RC Oscillator is not required since the SWT is disabled in this mode. Workaround 2: If a reset is not desired, a timer can be configured to generate a timeout interrupt event, inside the interrupt service routine (ISR),a wait for interrupt (WFI) instruction needs to be executed again, the system will now enter the desired low power mode and the mode transition bit will be cleared. If the previous wake-up event was to abort low power mode entry, a dummy timeout interrupt can be set prior to second WFI execution to exit low power mode. e9250: PASS: JTAG password not working during reset Description: The Debug Interface Access cannot be enabled by supplying the JTAG password during reset. Workaround: To enable the Debug Interface Access, supply the JTAG password after reset. e10590: PLL: Might remain unlocked when enabled after Standby or power on Description: When enabled after an event where the following conditions are met, the PLL might fail to lock: 1.- VDD_LV (1.2 V) was disabled 2.- A Pre-divider of 1 (PLLDIG_PLLDV[PREDIV] = 0 or 1) is used 3.- The PLL is clocked from the fast internal oscillator (FXOSC) Common situations in which VDD_LV might be disabled are Standby and power-off of the device. Workaround: There are three ways to avoid this: 1.- Avoid using a pre-divider of 1 (PLLDIG_PLLDV[PREDIV] = 0 or 1) and instead use a value of During Standby leave the supply to VDD_LV enabled. 3.- Initialize the PLL using the fast internal oscillator (FIRC) as source clock and then switch to use the fast external oscillator (FXOSC). e10170: QuadSPI: Insufficient read data may be received in the RX Data Buffer register Description: Data read from flash through QuadSPI using Peripheral Bus Interface (IPS) may return insufficient data in the RX Buffer Data register (QuadSPI_RBDRn) when the read data size of a flash transaction is programmed to be greater than 32 bytes. Workaround: For data size greater than 32 bytes, program the IP data transfer size in the IP configuration register (QuadSPI_IPCR[IDATSZ]) to be in multiples of 8 bytes. 10 NXP Semiconductors

11 e9461: QuadSPI: Read data errors may occur with data learning in 4x sampling method Description: Data learning using 4x Sampling method may select a sampling point which is marginal. A marginal sampling point occurs when the sampling point is located on the edge of the valid sampling window. A marginal sampling point may return a positive comparison of the data learning pattern but small variations in voltage and temperature during the same read transaction may result in data errors, since the sampling point is not properly located inside the valid sampling window. Workaround: There are two options: Internal DQS method allows to perform data learning as described on the Reference Manual. If 4x Sampling method is used, data learning should not be used and a fixed sampling point must be selected. e8950: RLE_DEC: edma transaction may not finish correctly on certain conditions Description: The following programming scenarios of Run Length Encoding Decoder (RLE_DEC) and edma may result in improper transactions: Case 1: When edma.tcd[nbytes] is equal to edma.tcd[ssize] (in bytes), the RLE_DEC will trigger the first request but subsequent edma requests will not occur and the decoder will hang. Case 2: When THRESHOLD is equal to NBYTES, the RLE_DEC will trigger extra DMA request at the end of edma transaction which might set RXFIF or TXEIF flags for receiver RX and transmitter TX channels respectively. Workaround: The following 2 conditions should be maintained on the RLE_DEC and edma configuration: Condition 1: edma.tcd[nbytes] >= 2 x edma.tcd[ssize] (in bytes) For example: edma.tcd[nbytes] = 4 and edma.tcd[ssize] = 1 (16-bit) is a correct configuration. Condition 2: RLE_DEC.MCR[RX/TX_FIFO_THRESHOLD] >= edma.tcd[nbytes] + edma.tcd[ssize] (in bytes) For example: RLE_DEC.MCR[THRESHOLD] = 6 and edma.tcd[nbytes] = 4 and edma.tcd[ssize] = 1 (16-bit) is a correct configuration. NXP Semiconductors 11

12 e10202: RTC: Software update of Time of Day register (RTC_TOD) might cause the internal counters to sample invalid values Description: A software write of the Real Time Clock Time of Day register (RTC_TOD) might cause the internal RTC counters (hour, minutes, seconds) to sample invalid values when the write coincides with the RTC counter clock edge. These invalid values are reflected in the RTC_TOD register only on the subsequent second interrupt. Workaround: This errata can be handled in two ways: 1. Update RTC_TOD with RTC disabled Disable the RTC to reduce the likelihood of the issue happening and verify if the written value is reflected on the TOD register at the next second interrupt, if not perform the write again. 2. Mimic RTC_TOD register on software Create a variable to keep track of an offset with respect the Time of Day register. This offset will depend on the desired Time of Day value, for instance if the TOD register holds a value of 1:30:30 and the Time of Day is 2:00:30 an offset of 0:30:00 will be required to adjust the value in the TOD register with respect the actual time. Updates to the Time of Day are performed by adjusting the offset. The issue will never occur since the register will never be written, only the offset variable will be modified.. e8799: SGM: 8-bit writes to FIFORP register incorrectly clears/flushes all channels Description: When 8-bit writes are made to to any of the channels (FRPCHn) of the FIFO read pointer register (FIFORP), all 4 channels have their FIFO, read/write pointers and flags cleared instead of just affecting the single channel that was written. Workaround: To clear the FIFO, read/write pointers and flags of a single channel an 8-bit write to the relevant channel (FWPCHn) field in the FIFO write pointer register (FIFOWP) should be used. e9658: SPI: Inconsistent loading of shift register data into the receive FIFO following an overflow event Description: In the Serial Peripheral Interface (SPI) module, when both the receive FIFO and shift register are full (Receive FIFO Overflow Flag bit in Status Register is set (SR [RFOF] = 0b1)) and then the Clear Rx FIFO bit in Module Configuration Register (MCR [CLR_RXF]) is asserted to clear the receive FIFO, shift register data is sometimes loaded into the receive FIFO after the clear operation completes. Workaround: 1. Avoid a receive FIFO overflow condition (SR[RFOF] should never be 0b1). To do this, monitor the RX FIFO Counter field of the Status Register (SR[RXCTR]) which indicates the number of entries in receive FIFO and clear before the counter equals the FIFO depth. 2. Alternatively, after every receive FIFO clear operation (MCR[CLR_RXF] = 0b1) following a receive FIFO overflow (SR[RFOF] = 0b1) scenario, perform a single read from receive FIFO and discard the read data. 12 NXP Semiconductors

13 e9214: SPI: Only 16 bits are accessible on the SPI_PUSHR_SLAVE register Description: In the Serial Peripheral Interface module, the PUSH TX FIFO register in Slave Mode (SPI_PUSHR_SLAVE.TXDATA) all [31:0] bits are shown as accessible but actually only [15:0] bits are valid. Bits [31:16] are reserved and will always read as zero. Data written to SPI_PUSHR_SLAVE.TXDATA[15:0] will be directly transferred to TX FIFO. Reading from the SPI_PUSHR_SLAVE.TXDATA register will return the topmost entry of the TX FIFO. Workaround: Only read or write the SPI_PUSHR_SLAVE.TXDATA[15:0] for valid data. e9892: STCU: System not able to handle PLL Loss of Lock event during offline/online selftest Description: PLL Loss of Lock event during STCU offline/online selftest mode, where selftest is configured to run on PLL can cause the system to hang. Workaround: It is recommended to run system on IRC for both offline/online selftest execution. e9114: XRDC:Illegal values written to MRGD_W2[SNUM] and PDAC_W0[SNUM] will result is undefined behavior. Description: Writes to the reserved bits above the most significant bits of MRGD_W2[SNUM] and PDAC_W0[SNUM] will result in undefined behavior. Workaround: Avoid writing illegal values to MRGD_W2[SNUM] and PDAC_W0[SNUM]. NXP Semiconductors 13

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