Technical Information Manual

Transcription

1 Technical Information Manual Revision n. 0 MOD. V551 C-RAMS SEQUENCER

2 TABLE OF CONTENTS TABLE OF CONTENTS... i LIST OF FIGURES... i LIST OF TABLES... i 1. DESCRIPTION FUNCTIONAL DESCRIPTION SPECIFICATIONS PACKAGING EXTERNAL COMPONENTS INTERNAL COMPONENTS CHARACTERISTICS OF THE SIGNALS POWER REQUIREMENTS OPERATING MODES GENERAL INFORMATION CONNECTION SCHEMES USING MOD. V550 AND V551 WITH JAUX DATAWAY USING MOD. V550 AND V551 WITHOUT JAUX DATAWAY OPERATION SEQUENCE INTERRUPT GENERATION VME INTERFACE ADDRESSING CAPABILITY DATA TRANSFER CAPABILITY MODULE IDENTIFIER WORDS STATUS REGISTER NUMBER OF CHANNELS INTERRUPT REGISTER REFERENCES APPENDIX A: ELECTRICAL DIAGRAMS... A.1 APPENDIX B: COMPONENTS LOCATIONS... A.2 LIST OF FIGURES Fig. 1.1: Mod. V551 Block Diagram... 2 Fig. 2.1: Mod. V551 Front Panel...6 Fig. 2.2: Mod. V551 Components Locations... 7 Fig. 3.1: Mod. V551 System Layout with connections via Auxiliary VME bus Fig. 3.2: Mod. V551 Operation Sequence Fig. 4.1: Mod. V551 Base Address Setting Fig. 4.2: Module Identifier Words Fig. 4.3: Mod. V551 Control Register Fig. 4.4: Mod. V551 Control Register Fig. 4.5: Mod. V551 Interrupt Register LIST OF TABLES Table 4.1: Address Map for the Mod. V i

3 1. DESCRIPTION 1.1. FUNCTIONAL DESCRIPTION The Model V551 CAEN C-RAMS Sequencer is a 1-unit wide VME module that controls both the C-RAMS (CAEN Readout for Analog Multiplexed Signals) boards Mod. V550, and the multiplexer boards housing some of the well known front-end chips (Amplex, Gasplex, Viking etc.). A single V551 can control up to 19 C-RAMS modules in a complete VME crate, thus enabling the readout of 19 * (2 * 2016) = multiplexed detector channels. The Mod. V551 doesn't need the VME control to work: by switching the module in Manual mode, it is able to perform the basic functions on its own. On the contrary, switching the board in Remote mode, it is possible to have a remote control of the module via VME bus. The number N of detector channels to be read out by the C-RAMS can be programmed via VME (remote mode) or via DIP switches (manual mode) up to The mode selection is performed via an internal switch. The multiplexing frequency can be set from 0.5 to 5 MHz by means of a trimmer housed on the front panel. The phase between the multiplexing Clock signal and the Convert signal of the acquisition cards can be adjusted to wait for the settlement of the analog signal coming from the multiplexers. The module houses a VME RORA INTERRUPTER[1]: via VME it is possible to program the interrupt generation on the condition that the DRDY signal is asserted, signaling that at least one channel in a system has data to be read out. The V551 Model uses the P1 and P2 connectors of VME and, optionally, the auxiliary connector for the CERN V430 VMEbus crate (Jaux Dataway)[1, 2] in order to handle, if desired, the CONV, DRDY and CLOUT signals via the Jaux connector. The module works in A24/A32 mode; the recognized Address Modifier codes are: AM = %3D standard supervisor data access; AM = %39 standard user data access; AM = %0D extended supervisor data access; AM = %09 extended user data access. The module's Base Address is fixed by 4 internal rotary switches housed on two piggy-back boards plugged into the main printed circuit board. The Base Address can be selected in the range: % <--> 0000 A24 mode; % <--> %FFFF 0000 A32 mode. The data transfer occurs in D16 mode. 1

4 Frequency adjust Phase adjust LOCAL OSCILLATOR Front panel 4-digit frequency meter CLOCK CONVERT Frequency Test Point IDENTIFIER Phase Test Point DRDY VME INTERFACE RDEVN CONV CLOCK GATE LOGIC INTERRUPTER IRQ INT. LEVEL CLIN CLOUT STATUS /ID Manual/Remote MUX Ch Nr. Nr. of Channels (manual selection) Fig. 1.1: Mod. V551 Block DiagramErrore. Il segnalibro non è definito. 2

5 2. SPECIFICATIONS 2.1. PACKAGING 1-unit wide VME unit. Height: 6U EXTERNAL COMPONENTS (refer to fig. 2.1) CONNECTORS - N. 2, "CONV", LEMO 00 type; provide the CONV output signal for the C-RAMS. - N. 2, "DRDY", LEMO 00 type; two bridged connectors (for daisy chaining) for the DRDY input signal. - N. 2, "RDEVN", LEMO 00 type; two bridged connectors (for daisy chaining) for the RDEVN input signal. - N. 2, "CLOCK", LEMO 00 type; provide the CLOCK output signal for the Multiplexers. - N. 2, "BUSY", LEMO 00 type; two bridged connectors (for daisy chaining) for the BUSY output signal. - N. 2, "CLIN", LEMO 00 type; two bridged connectors (for daisy chaining) for the CLEAR input signal. - N. 2, "CLOUT", LEMO 00 type; provide the CLOUT output signal for the C-RAMS. The connectors providing the CLOUT, CLOCK and CONVERT output signals are doubled on the front panel in order to give a fan out of 2. DISPLAYS - N. 1, "DTACK", green LED, VME Selected. It lights up during a VME access. - N. 1, "CONV", green LED. It lights up when the CONV signal is present, that's to say during a Convert cycle. - N. 1, "DRDY", green LED. It lights up when the DRDY signal is present. - N. 1, "CLOCK", green LED. It lights up when the CLOCK signal is present, that's to say during a multiplexer readout cycle. - N. 1, "BUSY", red LED. It lights up when the BUSY signal is present. - N. 1, "FREQUENCY", 4-digit red LED display. For the readout of the multiplexing frequency. 3

6 TRIMMERS, TEST POINTS - N. 1, "FREQUENCY", Trimmer+Test Point, for the multiplexing frequency setting and monitoring. - N. 1, "PHASE", Trimmer+Test Point, for the Convert Phase adjustment and monitoring INTERNAL COMPONENTS (refer to fig. 2.2) SWITCHES - N. 1, jumper "JP1"; for the -5 V power selection: by setting the jumper named JP1 it is possible to choose the -5 V power supply coming from the -12 V VME power supply (VEE position) or directly from the -5 V Jaux power supply (AUX position). - N. 1, DIP switch "SW1"; to enable/disable the DRDY detection on the Jaux backplane line SG. - N. 2, DIP switches "SW2"; to enable/disable the CONV generation via the Jaux backplane lines CK and CK*. - N. 2, DIP switches "SW3"; to enable/disable the CLOUT generation via the Jaux backplane lines CL and CL*. By putting the three DIP switches SW1, SW2 and SW3 in the OFF position, is possible to disable the CONV, CLOUT and DRDY signals handling via Jaux backplane. In this case the CK, CK*, CL, CL* and SG Jaux lines are disconnected. - N. 11, DIP switches "SW4+SW5"; for the manual selection of the number of channels (11-bits binary word, i.e channels). - N. 1, DIP switch "SW4"; for the manual/remote selection of the number of channels. - N. 4, rotary switches for the module's VME Base Address selection CHARACTERISTICS OF THE SIGNALS - CONVERT: std. NIM level on 50 Ω impedance; differential ECL on Jaux connector. - CLIN (1) : std. NM level, high impedance; min. width: 50 ns. - CLOUT: std. NM level on 50 Ω impedance; differential ECL on Jaux connector. - DRDY: std. TTL. level, high impedance (also on Jaux). 4

7 - BUSY: std. TTL positive open collector, active high on 50 Ω impedance. - CLOCK: std. NIM level on 50 Ω impedance. - RDEVN (1) : std. NIM input, high impedance; min. width: 50 ns. N.B.: The CLOCK and CONV output signals on test points are std. TTL level. (1) This is a high impedance input and is provided with two bridged connectors for daisy chaining. Note that the high impedance makes this input sensitive to noise, so the chain has to be terminated on 50 Ω on the last module; the same is needed also if one module only is used, whose input has thus to be properly matched POWER REQUIREMENTS + 12 V 100 ma 12 V 250 ma (50 ma when Jaux is used) + 5 V 1.5 A 5 V 200 ma (only if Jaux is used) 5

8 Mod. V560E Mod. V551 DTACK VME selected LED Frequency setting Phase adjust FREQUENCY (KHz) PHASE Clock signal test point Convert signal test point CONVERT output C O N V DATA READY input D R D Y READ EVENT input R D E V N CLOCK output C L O C K BUSY output B U S Y CLEAR input C L I N CLEAR output C L O U T 16 CH C - RAMS SEQUENCER Fig. 2.1: Mod. V551 Front PanelErrore. Il segnalibro non è definito. 6

9 VME P1 connector Rotary switches for Base Address selection OFF SW1 ON DRDY SW2 SW3 VEE AUX CONV CLOUT Paux connector for CERN VMEbus crate type V430 VME P2 connector REMOTE MANUAL Nr. of channels selection (11 bit binary word) 1 0 Component side of the board Fig. 2.2: Mod. V551 Components LocationsErrore. Il segnalibro non è definito. 7

10 3. OPERATING MODES 3.1. GENERAL INFORMATION The module handles the following signals: INPUT SIGNALS: - READ EVENT (RDEVN). It is a pulse (NIM level, provided via front panel connectors) whose leading edge indicates that the analog data are ready to be read out and starts the conversion sequence. - DATA READY (DRDY). It is a signal (TTL level) that indicates, by means of a wired-or of the DRDY signals coming from the acquisition cards, that at least one of such modules is in DATA READY state and so has data to be read out. If the same value of N (number of detector channels) has been programmed in all the acquisition channels, the DRDY signals will be asserted at the same time by all the modules. Since each DRDY goes low when the output FIFO has been read, the low level of DRDY indicates that all the channels have been read and the system is ready for another event. The DRDY signal is provided via front panel or via SG pin of the Jaux connector of the V430 crate. - CLEAR IN (CLIN). It is a pulse (NIM level) that resets the sequencer board and causes an output pulse on the CLEAR OUT connectors. It can be used as a Fast Clear to abort the current multiplexer readout cycle. OUTPUT SIGNALS: - CONVERT (CONV). It is the start of conversion pulse available on a front panel connector (NIM level), or via CK and CK* pins of the Jaux backplane connector of the V430 VME crate (ECL level), that goes to all the channels. - CLOCK (CLOCK). It is a pulse available on a front panel connector (NIM level) that causes the detector channel switching in the multiplexers. - BUSY (BUSY). It is a positive open collector signal available on a front panel connector that indicates that the system cannot accept new events. In this case the READ EVENT signal is ignored. Such a condition occurs in the following cases: - when the channels are in the conversion phase. - when the wired-or of the DRDY signals is high (VME reading phase in progress). - when CLEAR is asserted. - CLEAR OUT (CLOUT). It is a pulse available on a front panel connector (NIM level) or via CL and CL* pins of the Jaux backplane connector, (ECL level). It is asserted when a software CLEAR is performed or when CLEAR IN is asserted. It can be used to reset the acquisition cards and/or the multiplexer boards. N.B.: The Jaux signals can be disabled via internal DIP switches. 8

11 3.2. CONNECTION SCHEMES (refer to fig. 3.1) The Model V551 CAEN C-RAMS Sequencer has been designed in order to control more C-RAMS (CAEN Readout for Analog Multiplexed Signals) Mod. V550 in single acquisition systems. When a Mod. V551 C-RAMS Sequencer controls more than one V550 channel, the CONVERT signal is the same for each channel, so that each multiplexer is controlled by a single CLOCK. Some connections must be made among the C-RAMS modules and the Sequencer module to let them work properly: the V551 CONVERT and CLEAR OUT signals must be distributed towards the C-RAMS acquisition cards and the V550 and V551 DATA READY signals must be connected together to perform a wired-or. All this involves the use of a large number of 50 Ω cables, especially if there are a lot of V550 modules to be controlled; the Mod. V551 uses the P1 and P2 VME connectors and optionally the auxiliary connector for the CERN V430 VME bus crate (Jaux Dataway), thus, if the VME auxiliary bus is available, it is possible to send via backplane the CONVERT, CLEAR OUT and DRDY signals and all the connections mentioned above can be avoided USING MOD. V550 AND V551 WITH JAUX DATAWAY By means of DIP switches, either on the V550 boards or V551 board, it is possible to enable the Jaux Dataway (see 2.3), so that: 1.) The CONVERT signal coming from the V551 module is distributed to the V550 channels. 2.) The CLEAR OUT signal coming from the V551 module is distributed to the V550 channels (CLEAR connector of the C-RAMS modules). 3.) The wired-or of the V550 DATA READY signals is performed and received by the DRDY input of the Mod. V551. If on the backplane there is no termination on the CK, CK*, CL and CL* auxiliary VME bus lines, it is possible to insert it on the last C-RAMS module of the system. For this purpose, on the V550 board, a removable termination package (50 Ω to VTT) can be installed for the CLEAR and CONVERT signals termination. As the DATA READY signal is TTL, if there is a termination on the SG auxiliary VME bus line, it must be removed from the backplane. N.B.: With the layout shown in Fig. 3.1, it is convenient to set the -5 V power supply selection jumper to AUX. This allows to reduce the power consumption ony the -12 V power supply USING MOD. V550 AND V551 WITHOUT JAUX DATAWAY If the auxiliary VME bus is not available or you don't want to use it (in this case the Jaux Dataway DIP switches must be disabled), the following connections must be made: -Convert signal: CONV(V551 ) CONV(V550) CONV(V550)... CONV(V550) 50 Ω termination. 9

12 -Clear signal: CLOUT(V551) CLEAR(V550) CLEAR(V550)... CLEAR(V550) 50 Ω termination. -Data Ready signal: DRDY(V550) DRDY(V550)... DRDY(V550) DRDY(V551) 50 Ω termination. N.B.: Without the V430 crate, the -5 V power supply selection jumper must be set to VEE. This allows to obtain the -5 V from the -12 V power supply. 10

13 VME CRATE CH0 CH0 CH0 IN+ IN+ IN+ CONV IN- IN- IN- V T T DRDY 50 Ohm RDEVN READ EVENT 50 Ohm CH1 IN+ IN- Last C-RAMS of the system CH1 IN+ IN- Auxiliary CERN VME bus CH1 IN+ IN- CONV CLEAR DRDY CLOCK BUSY CLIN CLOCK BUSY CLEAR IN From/To Front-end Logic 50 Ohm CLEAR CLEAR CLEAR CLOUT CLEAR OUT C - RAMS SEQUENCER From Multiplexers Fig. 3.1: Mod. V551 System Layout with connections via Auxiliary VME bus.errore. Il segnalibro non è definito. 11

14 3.3. OPERATION SEQUENCE (refer to fig. 3.2) When a READ EVENT signal is sent to the Sequencer, the BUSY signal is asserted (indicating to the external world that the system is handling an acquisition) and N CLOCK pulses are generated. The number N of detector channels (between 1 and 2047) can be programmed via VME (remote mode) or via DIP switches (manual mode). The mode can be selected by an internal DIP switch. Each CLOCK pulse is followed by a CONVERT pulse after a delay of DELTA ns. The purpose of this delay is to wait for the settlement of the analog signal coming from the multiplexers. The width of the CLOCK and CONVERT pulses is 100 ns. The repetition period Ts of the CLOCK and CONVERT pulses (and consequently the multiplexing frequency) can be adjusted from 2 μs down to 200 ns by means of a trimmer housed on the front panel (adjustable frequency from 0.5 to 5 MHz). Also the ratio DELTA / Ts (Phase of CONVERT signal) can be adjusted by means of a front panel trimmer. The range of DELTA covers a period of the selected multiplexing frequency. N.B.: Since the CLOCK and CONVERT pulses are generated by an internal free running oscillator, the occurrence of the first pulse of CLOCK may be delayed (up to the repetition period Ts) with respect to the assertion of READ EVENT signal. The CLOCK and CONVERT signals coming from the free running oscillator are available on two test points ("FREQUENCY" and "PHASE") placed on the front panel. In addition, the multiplexing frequency can be read out by means of a 4-digit LED display placed on the front panel. After the generation of the last CONVERT pulse, it is necessary to wait for another interval Ts in order to process the last detector channel and allow the acquisition cards to raise the DRDY signal. When the DRDY has been raised (at least one channel has data ready), the BUSY signal remains high until all the FIFOs have been read out, that's to say until the DRDY goes low. When the CLEAR IN (or software Clear) is asserted, a CLEAR OUT pulse is generated and the Sequencer is cleared. If CLEAR IN is asserted during the acquisition phase, the generation of pulses is stopped, in addition, it can be used as a Fast Clear of the whole system. 12

15 READ EVENT CLOCK Ts...N pulses... Ts CONVERT DELTA BUSY DRDY INTREQ Fig. 3.2: Mod. V551 Operation SequenceErrore. Il segnalibro non è definito INTERRUPT GENERATION The operations of the V551 VME RORA INTERRUPTER are fully programmable; via VME it is possible: to set the VME Interrupt level; to program the VME Interrupt Vector (STATUS/ID); The interrupt is generated on the DRDY input signal of the Mod. V551, which is the logical wired-or of all DRDY signals coming from the acquisition cards. Thus, the interrupt is requested when at least one channel in the system has ended the programmed N conversion cycles and its FIFO is not empty, and is released when all the FIFOs have been completely read out. 13

16 4. VME INTERFACE 4.1. ADDRESSING CAPABILITY The module works in A24/A32 mode. This implies that the module's address must be specified in a field of 24 or 32 bits. The Address Modifiers code recognized by the module are: AM = %3D: AM = %39: AM = %0D AM = %09: standard supervisor data access; standard user data access; extended supervisor program access; extended user data access; The module's Base Address is fixed by 4 internal rotary switches housed on two piggy-back boards plugged into the main printed circuit board. The Base Address can be selected in the range: % <-> % FF 0000 A24 mode % <-> % FFFF 0000 A32 mode The Address Map of the page is shown in Table 4.1 on the following page DATA TRANSFER CAPABILITY The internal registers are accessible in D16 mode. 14

17 Base address bit <23..20> Base address bit <19..16> Base address bit <31..28> Base address bit <27..24> Fig. 4.1: Mod. V551 Base Address SettingErrore. Il segnalibro non è definito. 15

18 ADDRESS REGISTER/CONTENT TYPE Base + %FE Base + %FC Base + %FA Base + %08 Base + %06 Base + %04 Base + %02 Base + %00 Version & Series Manufacturer & module type Fixed code Module clear Read event Status register Number of channels Interrupt Register read only read only read only write only write only read only read/write write only Table 4.1: Address Map for the Mod. V551Errore. Il segnalibro non è definito MODULE IDENTIFIER WORDS (Base address + %FA,+ %FC, + %FE, read only) The three words located at the highest address of the page are used to identify the module as shown in figure 4.2: V e r s i o n M o d u l e ' s s e r i a l n u m b e r Base + % FE Manufacturer number M o d u l e t y p e % F A F i x e d c o d e % F 5 F i x e d c o d e Address Base + % FC Base + % FA Fig. 4.2: Module Identifier WordsErrore. Il segnalibro non è definito. At the address Base + %FA, the two particular bytes allow the automatic localization of the module. For the Mod. V551 the word at address Base + %FC has the following configuration: Manufacturer N = Type of module = b b The word located at the address Base + %FE identifies the single module via a serial number, and any change in the hardware (for example the use of faster Conversion Logic) will be shown by the Version number. 16

19 4.4. STATUS REGISTER (Base address + %04, read only) R B DY DRDY BUSY REMOTE Fig. 4.3: Mod. V551 Control RegisterErrore. Il segnalibro non è definito. D B R DRDY: = 0 no DRDY state; = 1 DRDY state. BUSY = 0 BUSY ; = 1 not BUSY. REMOTE. = 0 normal mode; = 1 remote mode NUMBER OF CHANNELS (Base address + %02, read/write ) N u m b e r o f c h a n n e l s Fig. 4.4: Mod. V551 Control RegisterErrore. Il segnalibro non è definito INTERRUPT REGISTER (Base address + %00, write only) This register contains the value of the Interrupt Level and the STATUS/ID that the V551 INTERRUPTER places on the VME data bus during the Interrupt Acknowledge cycle INT. LEV. S T A T U S / I D Interrupt STATUS/ID Interrupt level Fig. 4.5: Mod. V551 Interrupt RegisterErrore. Il segnalibro non è definito. 17

20 5. REFERENCES [1] VMEbus Specification Manual Revision C.1, October [2] G. Bianchetti et al., "Specification for VMEbus CRATE Type V430", CERN-EP, January

21 APPENDIX A: ELECTRICAL DIAGRAMS A.1

22 APPENDIX B: COMPONENTS LOCATIONS A.2