TOF Electronics. J. Schambach University of Texas Review, BNL, 2 Aug 2007

Transcription

1 TOF Electronics J. Schambach University of Texas Review, BNL, 2 Aug

2 Outline Electronics Overview Trigger & DAQ Interfaces Board Status, Tests & Plans 2

3 Electronics for One Side 3

4 Tray Level Electronics 4

5 Front-End Electronics TINO 5 TDIG Interface TDIG Interface TDIG Interface MRPC Interface MRPC Interface MRPC Interface 8 per tray 960 total MRPC Interface

6 PMT Input Board TPMD 4 per Start Detector 8 total 8 6

7 Digitizer Board TDIG 8 per tray 4 per start side 968 total 7

8 Tray Controller TCPU 1 per tray 1 per Start Detector 122 total 8

9 DAQ/Trigger Interface THUB CYCLONE FPGA 672 pin 0.5M RAM CYCLONE FPGA 672 pin 0.5M RAM CYCLONE FPGA 672 pin 0.5M RAM CPLD SIU DDL Components DRORC CYCLONE FPGA 672 pin 0.5M RAM 36 CYCLONE FPGA 672 pin uc TCD CAN CYCLONE FPGA 672 pin 0.5M RAM 36 SIU SIU 8-11 CYCLONE FPGA 672 pin 0.5M RAM 36 RESET IN 4-7 CYCLONE FPGA 672 pin 0.5M RAM 36 RESET OUT(3) CYCLONE FPGA 672 pin 0.5M RAM 36 CLOCKS Power supplies Clocks OUT(3) Clock IN Nationals SerDes Chip 9

10 Interface to L0 trigger Provides multiplicity at 9.4 MHz with <~700 ns latency. The multiplicity range is 0-24 for each tray, where one is added to the sum if any of the 8 TOF channels in a NINO chip is above threshold. We are currently considering two possible solutions to send these data to L0 trigger, one digital, the other analog. In the digital solution, TDIG receives the multiplicity information from the NINO, synchronizes it to the local 40 MHz clock, sums it digitally and passes it to TCPU. Each TCPU sums the information from all TDIGs, and sends the resulting multiplicity over 5 cable pairs to the Level 0 DSMI on the south platform. These cables all need to be the same length to within 1ns. Each DSMI can handle 20 trays. A total of 6 DSMIs are needed for this solution to handle TOF Multiplicity trigger information As an alternative approach, we are considering to sum the Multiplicity signals analog on a separate board (housed on the tray under TCPU) and send the analog sum over existing (CTB) coax cables to CDB boards that digitize these data. Neither solution has been tested so far, but provisions have been made on TINO, TDIG, and TCPU boards for these solutions. We plan to test the digital solution initially in Run 8, and if it does not succeed, go to the analog solution that is similar to what is currently being used to get multiplicity information from the CTB trays to trigger. 10

11 Interface to Level-2 Trigger Physical Interface is the identical DDL link that will be used to connect TOF to DAQ. The second DDL link will originate from the THUBs for a total of four dual fibers going to the Level-2 computer system. TOF will provide a 23k bit map of the TOF hits to Level-2 for each L0 trigger, 192 bits per tray, where each bit represents a hit channel. 11

12 Interface to DAQ The TOF system needs to be faster than the upgraded TPC so as not to introduce any additional dead time. The TOF information is only useful in a STAR event if the TPC is also readout in that event (for tracking). The system is able to handle L0 accept commands at >10 khz. The system will not process L2-accept or Abort commands, but rather pass those on to DAQ (as separate events) over the fiber for DAQ to process. The current system design foresees sending all events to DAQ independent of any higher level trigger decisions for each Level-0 trigger. This design does not require much memory on THUB other than a small amount (arranged as a FIFO) to decouple the clock domain on the TCPU () side from the clock domain of the DAQ (SIU) interface. 12

13 Overall Specifications DAQ Data Rates Trigger Level-0 Input Rate Input Rate into Level-2 10,000 Hz 10,000 Hz Number of Fiber pairs to DAQ 4 Number of channels per MRPC 6 Number of MRPCs per tray 32 Number of Channels per tray 192 Number of trays 120 Total Number of MRPC channels 23,040 Number of Start Detector Channels 19 Number of Start Detectors 2 Tray Specifications Data Volume per (black) Event per Tray in bits 12,448 (192*2*32 + 3*32 header + 2*32 geographical) THUB Specifications Number of TCPU-THUB Interfaces 31 L0-rate per in bits/sec ( black event ) 124,480,000 ( Black ) Event Size per THUB (31 trays) in bits 385,888 L0-rate assuming < 20% occupancy (bits/sec) 771,780,000 DDL Fiber 66MHz DDL Fiber 40 MHz (* 40/66) 20 MHz (assuming 16bit payload 250MB/s = 2Gb/s 150MB/s = 1.2Gb/s 320 Mbit/s 13

14 Current Status 14

15 TINO 15

16 TINO Status Motivation: Replace Maxim Amplifier & Comparator of TAMP with custom ASIC NINO incorporating both functions: Lower Cost Power (no negative supply & lower power, fewer power supplies) Fully differential: better match to HPTDC Pulse stretching: one TDC can measure both leading & trailing edge Decision to use TINO instead of TAMP was reached in Feb 2006 based on cosmic ray testing (see following slide) with both TAMP and TINO giving similar timing resolutions Automated TINO prototype production has been achieved, one company fabricated 35 circuit boards, all boards successfully assembled Minor revisions made to design and layout for part availability and assembly reasons Mechanical compatibility with tray design verified Cable delay data digitized with the current TDIG shows expected timing resolution (sigma ~ 1 time bin ~ 24ps) 16

17 TINO Status (continued) Due to the possibility of significant cost savings, a second company was asked to assemble 50 TINOs. Although they successfully assembled the NINO chips (only 1 NINO chip had problems), the majority of the received boards had minor Q/A problems. The problems were easily fixed, however, the concern remains if they can overcome these Q/A problems, so they were asked to assemble another 50 boards. As a backup, a third company was asked for a turnkey quote for building a trial of 50 boards. Their initial quote for the assembly of 250 boards was comparable to the second company. We currently have 250 bare boards and parts for 250 more boards available. Once a decision has been made about the assembly companies, the rest of the bare boards will be ordered. 17

18 UT Cosmic Ray Test Setup Readout through TAMP or TINO, TDIG, and TCPU dt = t3 (t1+t2+t4)/3 Result: Timing resolution from TINO and TAMP is comparable (~90 ps)

19 TINO-TDIG Cable Delay Data sigma = sigma = sigma = sigma = sigma = sigma = TDC 1 TDC 2 TDC 3 19

20 TINO Test Plan NINO chips were fully CERN after packaging Confirm timing & crosstalk performance of TINO design in TDIG RFI environment Verify input to output integrity of each PCB assembly Verify PCB assembly, current drain Measure, with TDIG readout, for each channel: Threshold voltage which sets discrimination to 0 (noise) Overall Gain, (input level for Full & nominal threshold, verify integrity of both differential input legs) Output count rate vs. Input rate under mild mechanical stress Output pulse width ( Stretch ) at threshold + 20% input level 20

21 TPMD (start side FEE) Replacement for TPMT to match start detector electronics to tray electronics Design considerations: Map 4 channels max. per HPTDC to minimize crosstalk effect Outputs provided for ( fast ) Z-vertex FEE (not part of the TOF project) Status: Due to a mapping inconsistency with TDIG-E, only 5 of the 8 possible channels are usable, so we need 4 TPMD & TDIG per start side All necessary boards are in hand 21

22 THUB 22

23 THUB Status Needed to concentrate data before sending to DAQ in order to reduce the number of DAQ-fiber interfaces & to provide interface to Level-2 trigger Prototype UT, 3 THUB boards with 4 channels each assembled, two of which were installed during Run 7 TCPU-THUB interfaces implemented as on daughter cards; distributes trigger, and resets to TCPU, receives data from TCPU All THUB interfaces were verified on the bench. Trigger and DAQ interfaces were tested and verified in STAR during Run 7. link works reliably on shielded CAT-6 cables up to ~25 40MHz, > MHz. Need about 30 feet for start detector cable run Tests showed that the recovered clock is not usable for system clock distribution. Although the jitter performance was good enough to give timing resolution from TDIG comparable to the Run 5 electronics, the phase of the recovered clock jumps in discreet steps on each power cycle by as much as 30 ps As an alternative clock distribution scheme, we decided to use one of the two unused differential pairs in the CAT-6 cable to distribute the 40 MHz clock to the TCPUs. This was tested with the prototype THUBs with a modification of the boards. 23

24 THUB Clock Distribution 24

25 Global System Clock Distribution Master Clock 25

26 THUB Status (continued) To test the clock distribution scheme, the following setup was measured on the bench: The clock was sent from the (master) THUB through 100 coax to a slave THUB The slave THUB sent the clock over 30 CAT-6 to a TCPU. The TCPU sent the clock over a 4 ribbon cable to 4 TDIG chained together A delta time measurement between the master THUB clock and the last TDIG clock was made with a digital scope (Tektronics TDS 7154B): With both the slave THUB PLL & TCPU PLL: sigma = 11ps Bypassing the PLL on the slave THUB: sigma = 8ps Bypassing both the (slave) THUB & TCPU PLLs: sigma = 6ps Unfortunately, the SiLab 5310 PLL showed changing delays by as much as 50ps in steps of 10ps on each power-cycle Alternatively, the SiLab 5321 PLL does not show this behavior in our tests. This device also has selectable jitter attenuation bandwidths from 12 khz down to 800 Hz Possibly, no PLL at all is needed, as indicated in our jitter measurement tests 26

27 THUB Plans Need another revision for final THUB Add Level-2 interface (SIU) Correct minor issues with prototype Change clock distribution scheme Add possibility to bypass PLL and possibly different PLL Need about 3 weeks of circuit design work and about 4 weeks for layout of final revision Production and assembly takes about 4 weeks (only 4 boards plus spares are needed) Board locations on the STAR magnet have been documented within STAR Cable runs were discussed with R. Brown 27

28 TDIG-E 28

29 TCPU-B 29

30 TDIG & TCPU Status Latest design for TDIG includes possibility to readout TDCs while bypassing the on board PLDs. This would reduce the number of PLDs susceptible to radiation damage (SEU s) by a factor of 9 (1 PLD versus 9 PLDs per tray). A pulser distribution board TCAL has been designed to allow test pulses to be distributed to all 24 channels on TDIG, 12 of those boards were assembled for use at Blue Sky and the universities Major functionalities of both TDIG and TCPU have been verified in bench tests. Cable delay tests show that the timing resolution meets expectations. Remaining work is mostly firmware Both TDIG & TCPU need one more (minor) revision to correct a schematic error on TDIG and to replace the PLL with the new SiLabs part as well as the capability to bypass it on TCPU The INL correction tables for each TDIG will be obtained during production with the TDIGs and TCPU connected with final tray cables in a tray configuration, which also tests the full readout chain Details & production plans presented in Lloyds talk 30

31 Cable Delay Tests: INL Correction Red = channel-by-channel Black = common INL Channel-by-channel INL correction will be necessary! 31

32 Cable Delay Tests with different clock distributions: 1) Clock from TCPU Clock Distribution TCPU TDIG 32

33 2) Clock from THUB Clock Distribution THUB 30 CAT-6 TCPU TDIG 33

34 3) Clock distributed from Master THUB Master THUB to Slave THUB 100 Coax Slave THUB 30 CAT-6 TCPU TDIG 34

35 4) THUB to 2 TCPU & 2 TDIG THUB 30 CAT-6 TCPU TCPU TDIG TDIG 35

36 5) 2 THUB to 2 TCPU & 2 TDIG Master THUB 100 Coax Slave THUB 30 CAT6 TCPU TCPU TDIG TDIG Note: PLL on Slave THUB bypassed 36

37 Cable Delay Tests: Summary Above tests show that the clock distribution scheme works and gives reasonable timing resolution results of about 1 time bin (~ 25ps) for stop-start time difference measurements 37

38 Additional Slides 38

39 CERN/LAA NINO Chip developed for ALICE Parameter Peaking time Signal Range Noise (with detector) Front edge time jitter Power consumption Discriminator threshold Differential Input impedance Output interface Value 1ns 100fC 2pC < 5000 e- rms <25ps rms 30 mw/ch 10fC to 100fC 40Ω< Zin < 75Ω LVDS 39

40 HPTDC Time Measurement HPTDC is fed by a 40 MHz clock giving us a basic 25 ns period (coarse count). A PLL (Phase Locked Loop) device inside the chip does clock multiplication by a factor 8 (3 bits) to 320 MHz (3.125 ns period). A DLL (Delay Locked Loop) done by 32 cells fed by the PLL clock acts as a 5 bit hit register for each PLL clock (98 ps width LSB = ns/32). MSB 4 R-C delay lines divide each DLL bin in 4 parts (R-C interpolation) LSB Coarse time (bin width 25 ns, 11 bits) PLL bits (bin width ns) DLL bits (bin width 98 ps) R-C bits (bin width 24.4 ps) 40

41 HPTDC Buffering & Readout 8 25ps or ps Level-0 Trigger Bunch Crossing Hit Buffer Level-0 Buffering 41

42 ALICE DDL Link Front-end electronics Read Out Receiver Card Source Interface Unit Destination Interface Unit DDL DDL SIU SIU DDL DDL DIU DIU RORC RORC Optical Fibre ~200 meters Detector Data Link Data Acquisition PC PC PC 42

43 Crosstalk measurements START Signal Noise signal Ch. 0 Ch. 1-7 HPTDC 1 Δs Cross Talk check: Analyzing shifts of T start -T stop while varying Δs STOP Signal T start -T stop Ch. 23 HPTDC 2 43

44 ALICE & CAEN Cross Talk LSB XTalk: ch 1 over ch Start disturbed Start-Disturb delay (ns) Stop disturbed Stop Start Measurement Start = Channel 0, Stop = Channel 7 Disturbing Channel on Channel 1 44

45 Crosstalk Results Disturbing Signal On Channel: Ch 1 Ch 2 Ch 3 Ch 4-10ns Ch 5 Ch 6 Ch 7 Ch 12 Ch 1 Ch 7 = Same chip Different chip 45

46 Crosstalk in Run 5 Data all 1 hit 2 hits 3 hits 46

47 Electronics Installation 47

48 Electronics Items To Install THUB: 4 boxes, 2 on each magnet face, about 30inx15inx10in, 180 degrees apart from each other Box design and exact location still need to be determined Installation by STSG THUB-TCPU Interconnects: 120 CAT5/6 cables Installation by TOF CANbus cables: 4 cables from South platform to 4 THUB cards 4 cables from THUB to trays 120 cables from tray to tray Installation by TOF/STSG Fibers: 4 dual fibers from THUB to DAQ 4 fibers to Trigger-L2 boxes 48

49 Electronics Items to Install (continued) Low Voltage Supplies: 12 Wiener Mainframes in 2 racks Installation by STSG Low Voltage cables: 2 voltages plus 2 sense wires per tray, already attached to tray at time of installation; 120 wire assemblies total Cut to correct length and terminated at time of installation Installation by STSG TCD cables: 4 cable assemblies from TCD distribution crate to 4 THUBs Installation by TOF? Multiplicity cables: 120 ribbon cables from trays to trigger DSMs Installation by Trigger 49