Application Report. 1 Introduction. Device Applications...

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1 Application Report SPRAAT4 February 2008 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification Device Applications... ABSTRACT This application report describes the TMS320DM6467 electrical compliance of a high-speed (HS) universal serial bus (USB) operation conforming to the USB 2.0 specification. The non-otg controller supports the USB 2.0 device-mode operation at HS and FS full-speed (FS) and the USB 2.0 host-mode operation at HS, FS and low-speed (LS). Contents 1 Introduction Test Items Required Instruments Test Condition References List of Figures 1 USB Functional Block Diagram Eye Diagram/Signal Eye Waveform Plot Rise Time Fall Time Duty Cycle Distortion (DCD) Random Jitter/Deterministic Jitter/Total Jitter Setup Diagram for Performing HS Upstream Signal Quality Test Setup Diagram for Performing HS Test_J/K/SE0_NAK Tests Setup Diagram for Performing Receiver Sensitivity Level Test List of Tables 1 Device Electrical Tests Result Summary Test Categories Required Instruments Power Supply Voltage and Temperature Conditions Overall Result of the Signal Quality Test Overall Results of 12-Bit SYNC Field Introduction The device high-speed electrical test procedure is comprised of a series of tests and related procedures developed by the USB 2.0 compliance committee to verify electrical requirements of high-speed USB operations designed to meet USB 2.0 specification. This document outlines the test setup and captures the results of the series tests performed on the DM6467 device. All trademarks are the property of their respective owners. SPRAAT4 February 2008 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification 1

2 Introduction The DM6467 device high-speed electrical test of the USB is performed on a VDB, a board that is used to validate the device feature and is not optimized for USB characterization. Better results are expected when using test boards that are optimized for characterization purposes. Figure 1 shows the USB functional block diagram. Endpoint Control DMA Requests EP0 Control -Host EP0 Control -Function EP1-4 Control Transmit Receive CPU Interface Interrupt Control Interrupts Combine Endpoints Host Transaction Scheduler EP Reg. Decoder UTM Synchronization Data Sync Packet Encode/Decode Packet Encode RAM Controller Rx Buff Rx Buff Common Regs. Cycle Control VBUS -Slave Mode Timers Packet Decode CRCGen/Check Tx Buff Tx Buff Cycle Control FIFO Decoder Tx/Rx Macrocell (UTMI+ Level 3 Compliant) Optional ULP1 Link Wrapper RAM DMA Controller (Optional) VBUS -Master Mode Figure 1. USB Functional Block Diagram 2 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification SPRAAT4 February 2008

3 2 Test Items Test Items Table 1 captures the series of compliance tests and the summary of results for each test. Details on the tests and specific results are discussed in the following sections. Table 1. Device Electrical Tests Result Summary Test# Test Items Result USB_EL_2 HS Transmitter data rate 480 Mb/s ± 0.05% PASS USB_EL_4 Signal quality test measured at the near end PASS USB_EL_6 10% to 90% differential rise and fall time > 500ps PASS USB_EL_7 Monotonic data transitions over the vertical openings in the appropriate EYE PASS pattern template USB_EL_21 Synchronization (SYNC) field (packet originating from DM6467) PASS USB_EL_22 Inter-packet gap (delay between Host and device packet) PASS USB_EL_25 End of packet (EOP) field (packet originating from DM6467) PASS USB_EL_28 Chirp reset time PASS USB_EL_29 Chirp-K duration PASS USB_EL_31 Delay between last Host chirp and device disconnect 1.5 K pull-up resistor and PASS enable termination USB_EL_27 Chirp handshake generation while Host performing reset in the middle of idle PASS (non-suspend HS mode) USB_EL_28 Chirp-K duration when reset is invoked from a suspended state PASS USB_EL_38 Chirp reset time when reset is applied from a suspend state PASS USB_EL_39 Device support for suspend state PASS USB_EL_40 Device transitioning from suspend state to HS operation due to reaching the EOF PASS USB_EL_8 Test J/K (controller transmits continuous J) PASS USB_EL_8 Test K (controller transmits continuous K) PASS USB_EL_9 Test_SE0_NAK (controller responds to any valid IN token with a NAK) PASS USB_EL_16 Device receiver level PASS USB_EL_17 Device squelch level PASS USB_EL_18 Device capability for locking PLL with 12-bit SYNC field PASS Table 2 lists the categorized series of tests outlined in the electrical test procedure in the USB2.0 compliance test. HS transmitter data rate 480 Mb/s ± 0.05% Signal quality test measured at the near end Test Items 10% to 90% differential rise and fall time > 500 ps Table 2. Test Categories Monotonic data transitions over the vertical openings in the appropriate EYE pattern template SYNC field (packet originating from DM6467) Inter-packet gap (delay between Host and device packet) EOP field (packet originating from DM6467) Chirp reset time Chirp-K duration Delay between the last Host chirp and the device disconnect 1.5 K pull-up resistor and enable termination Categories HS Upstream Signal Quality Test Device Packet Parameters Device Chirp Timing SPRAAT4 February 2008 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification 3

4 Required Instruments Table 2. Test Categories (continued) Test Items Chirp handshake generation while Host is performing reset in the middle of idle (non-suspend HS mode) Chirp-K duration when reset is invoked from a suspended state Chirp reset time when reset is applied from a suspended state Device support for suspend state Device transitioning from suspend state to high-speed operation when resume signaling is issued by the Host (from a suspend state) Test J (controller transmits continuous J) Test K (controller transmits continuous K) Test_SE0_NAK (controller responds to any valid IN token with a NAK) Device receiver level Device squelch level Device capability for locking PLL with 12-bit SYNC Field Categories Device Suspend/Resume/Reset Timing Device Test_J/K and Test_SE0_NAK Device Receiver Sensitivity 3 Required Instruments Table 3 lists the test instruments used to perform the outlined series of tests. These instruments are not all identical to the ones outlined in the test document and are mentioned here since test setup, equipment, and cables have a large influence on the test outcome. Table 3. Required Instruments Type Manufacturer Product Use USB high-speed electrical test tool to be USB-IF USBHSET To enumerate and send command loaded on a test bed computer Oscilloscope Tektronix DSA71604 To measure USB signals Differential probe (1) Tektronix P7313 Signal quality/receiver sensitivity tests Single-ended FET probe (2) Tektronix P6215 Packet parameters/chrip timings Measurement application (USB test Tektronix TDSUSB USB compliance test software software that is part of the scope specifically used for USB application) Test fixture Tektronix TDSUSBF For USB test Power supply V power supply for TDSUSBF Arbitrary waveform generator Tektronix AWG5002 To generate serial test data for receiver sensitivity test Digital multimeter Fluke Fluke 87 Series Measure voltage and current DP and DM lines Test board (VDB) TI EVM Like Board Non-optimized test board used for DM6467 Device validation 4 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification SPRAAT4 February 2008

5 4 Test Condition Test Condition 4.1 Power Supply Voltage/Temperature Table 4 shows power supply voltage and temperature conditions. Table 4. Power Supply Voltage and Temperature Conditions Parameter Min Typ Max Unit USB_V DDA1P2LDO V USB_V DDA3P V Operating Temperature C 4.2 HS Upstream Signal Quality Test The HS upstream signal quality test uses the TEST_PACKET command to place the DM6467 device in test mode where the controller continuously transmits a fixed format test packet, which is defined in the USB 2.0 specification, Section The test bed computer uses the electrical test tools to issue the TEST_PACKET command to the DM6467. Upon receiving this command, the DM6467 device enters the test packet test mode and begins continually sending a test packet. Using the test packet, this test measures the signal quality sent from the DM6467 device. The oscilloscope, along the embedded software, automatically analyzes the test packet signal quality as observed on the USB bus. For detailed procedures, see the Device High Speed Electrical Test Procedure document issued by the USB Implementers Forum ( EL_2: Signal Rate A USB 2.0 high-speed transmitter data rate must be 480 Mb/s ± 0.05% EL_4: Signal Quality/Eye Diagram Test An eye diagram provides an intuitive view of jitter. It is a composite view of all the bit periods of a captured waveform superimposed upon each other. A USB 2.0 upstream port on a device, without a captive cable, must meet Template 1 transform waveform requirements measured at a test point close to the port EL_6: Rise and Fall Time A USB 2.0 high-speed driver must have 10% to 90% differential rise and fall times of greater than 500 ps. SPRAAT4 February 2008 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification 5

6 Test Condition EL_7: Monotonic Data Transitions A USB 2.0 driver must have monotonic data transitions over the vertical openings specified in the appropriate EYE pattern template. Table 5. Overall Result of the Signal Quality Test Standard Measurement Min. Max. Mean pk-pk Deviation RMS Pop. Status Eye Diagram Test PASS Signal Rate Mbps bps 512 PASS Mbps Mbps Mbps Mbps EOP Width ns PASS EOP Width (Bits) PASS Rise Time ns ns ps ns ps ps 107 PASS Fall Time ps ns ps ns ps ps 107 PASS Additional Information Consecutive Jitter Range: ps to ps RMS Jitter ps KJ Paired Jitter Range: ps to ps RMS Jitter ps JK Paired Jitter Range: ps to ps RMS Jitter ps Differential Signal, V Time (x 10^ 9) s Figure 2. Eye Diagram/Signal Eye 6 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification SPRAAT4 February 2008

7 Test Condition Differential Signal, V Time (x 10^ 6) s Figure 3. Waveform Plot 10% Rise Time 10% Pattern Figure 4. Rise Time 10% Pattern Fall Time 10% Figure 5. Fall Time SPRAAT4 February 2008 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification 7

8 Test Condition Pattern Data Rate Duty Cycle Distortion Figure 6. Duty Cycle Distortion (DCD) DJ Histogram RJ TJ RJ RJ: Random jitter (Normal distribution / dependent on the Bit error rate) DJ: Deterministic jitter (Non-normal distribution) TJ: Total jitter ( = RJ + DJ ) Figure 7. Random Jitter/Deterministic Jitter/Total Jitter DM6467 VDB USB Cable Test Fixture USB Cable Host PC (Electrical Test Tools) Differential Probe Oscilloscope Figure 8. Setup Diagram for Performing HS Upstream Signal Quality Test Figure 8 is also used for other sets of tests: Device Packet Parameters Device CHIRP Timing Device Suspend/Resume/Reset Timing 4.3 Device Packet Parameters The device packet parameter tests are comprised of a set of tests related to fields pertaining to a USB transfer. Unlike the signal quality test, the device does not need to enter into a test mode. Instead, the test bed computer invokes a set feature control transaction by pausing in between transfers. The single step set feature command requires a setup stage and a status stage. The test bed computer invokes the setup stage transaction then pauses until told to continue. The packet delimiter fields, SYNC and EOP, are measured from the handshake packet during the setup stage in the transaction. The STEP button of the electrical test tool is used to continue/finish the set feature command. The inter packet gap, the delay between the token packet originating from the Host and the data packet (zero length) originating from the device, is measured from the second half of the transfer. The same setup file used for the signal quality testing is used to perform device packet parameters tests. Three device parameters are tested from this setup: SYNC, EOP, and inter-packet-gap 8 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification SPRAAT4 February 2008

9 Test Condition EL_21: SYNC (Synchronization) Field The SYNC field for all transmitted packets (not repeated packets) must begin with a 32-bit SYNC field. Handshake packet SYNC field: PASS Measured value: 66.5 ns => 66.5 ns / (1/480*10^6) = bits EL_22: Inter-Packet-Gap Field When transmitting after receiving a packet, hosts and devices must provide an inter-packet-gap of at least 8 bit times and not more than 192 bit times. Packet gap between Host token packet and device data packet: PASS Measured value: ns => ns / (1/480*10^6) = 103 bits EL_25: EOP (End-of-Packet) Field The EOP for all transmitted packets (except state of finish (SOF)) must be an 8-bit nonreturn to zero inverted (NRZI) byte without bit stuffing. Handshake packet EOP field: PASS. Measured value: ns => ns / (1/480*10^6) = bits 4.4 Device CHIRP Timing The device chirp timing is used to validate a high-speed detection handshake and occurs during the time of reset. Some time after the Host resets a high-speed device, the device should indicate its high-speed capability by generating a chirp-k signal. The Host will follow up by generating three sets of chirp-kj signals in a full-speed signaling environment. The device should disconnect its 1.5KΩ pull-up resistor and enable the 45 Ω termination resistors right after the last chirp-j from the Host. You can invoke this test using the same setup as the signal quality testing shown in Figure 8, with the two probes replacing the differential probe; however, in this case use the Host test bed computer to enumerate the DM6467 device only. You can also invoke the Enumerate Bus single-endedfrom the high-speed electrical test tool to perform the same test. Make sure your scope is configured and ready for capturing/triggering the enumeration process. Start by disconnecting the USB cable connection between the Host and USB fixture (TDSUSB2F). Have the device side code ready and running. When connecting the USB cable from the Host onto the USB test fixture, the enumeration process takes place and is captured on the scope. Figure 8 displays the setup used for performing these set of tests. In place of the differential probe, two single-ended FET probes are used. SPRAAT4 February 2008 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification 9

10 Test Condition EL_28: CHIRP Reset Time Devices must transmit a chirp handshake no sooner than 2.5 µs and no later than 3 ms when being reset from suspend or a full-speed state. CHIRP reset time: PASS Measured value: ns EL_29: CHIRP-K Duration The chirp handshake generated by a device must be at least 1ms and not more than 7 ms in duration. CHIRP-K duration: PASS Measured value: ms EL_31: 1.5 K Pull-Up Resistor Disconnection When a device detects a valid set of chirp-kj sequences during device speed detection, the device must disconnect its 1.5 K pull-up resistor and enable its high-speed terminations within 500 µs. 1.5K pull-up resistor disconnect: PASS Measured value: 4.4 µs 4.5 Device Suspend/Resume/Reset Timing A device must support suspend state. It is supposed to go through a suspend state when it is forced to go to suspend state by the host or when there is no activity for 3 ms. A high-speed device indicates its high-speed operation capability when the Host invokes a reset on the device by generating a chirp-k sequence signal. Figure 8 displays the setup used for performing these set of tests with the two single-ended probes replacing the differential probe EL_27: CHIRP Handshake Generation From Non-Suspended State A device must transmit a chirp handshake no sooner than 3.1 ms and no later than 6 ms when being reset from a non-suspended high-speed mode. The timing is measured from the beginning of the last SOF transmitted and before the reset begins. Chirp handshake generation when reset from a non-suspended state: PASS Measured value: µs EL_28: CHIRP-K Duration From a Suspended State A device must transmit a chirp handshake (chirp-k) no sooner than 2.5 µs and no later than 3 ms when being reset from suspend or a full-speed mode. Chirp-K duration from a suspend state: PASS Measured value: 354 µs 10 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification SPRAAT4 February 2008

11 4.5.3 EL_38: CHIRP Reset Time From a Suspended State Test Condition A device must revert to full-speed termination no later than 125 µs after there is a 3 ms idle period on the bus. Chirp reset time when reset is applied from a suspended state. PASS Measured value: ms EL_39: Device Support for Suspend State A device must support suspend state. The device should go into suspend state when forced by the Host. Device support for suspend state: PASS No value to measure. Make sure SOF is not present EL_40: Device Resuming With High-Speed Operation After Resume Signaling From a Suspend State A device must transition its operating to a high-speed operation after receiving the resume signal. This is with the assumption that the device was operating at high-speed prior to being suspended. Device resumes to HS operation at the end of resume signaling: PASS No value to measure. SOF at a HS signal level is observed. 4.6 Device Test_J/K/SE0_NAK A USB controller that is USB 2.0 specification compliant requires that the controller support four tests: Test_SE0_NAK, Test_J, Test_K, and Test_Packet. A digital Multimeter is used for the DC voltage level of D+ and D- data lines. Test_SE0_NAK places the controller to remain in high-speed mode but respond to any valid IN token with a NAK. Test_J places the controller to transmit a continuous J on the bus. Test_K places the controller to transmit a continuous K on the bus. Figure 9 displays the setup used for performing the tests mentioned in Section 4.6. DM6467 USB Cable Test Fixture USB Cable Host PC (Electrical Test Tools) DM Two Single Ended FET Probes Oscilloscope Figure 9. Setup Diagram for Performing HS Test_J/K/SE0_NAK Tests SPRAAT4 February 2008 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification 11

12 Test Condition EL_8: Test_J When the D+ is driven high, the output voltage must be 400 mv ± 10% when terminated with precision 45 Ω resistor. D+ data line DC voltage level: PASS Measured value: V D- data line DC voltage level: PASS Measured value: V EL_8: Test_K When the D- is driven high, the output voltage must be 400 mv ±- 10% when terminated with precision 45 Ω resistor. D- data line DC voltage level: PASS Measured value: V D+ data line DC voltage level: PASS Measured value: V EL_9: Test_SE0_NAK When either D+ and D- are not being driven, the output voltage must be 0 V ± 10% when terminated with precision 45 Ω resistors to ground. D+ data line DC voltage level: PASS Measured value: V D- data line DC voltage level: PASS Measured value: V 12 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification SPRAAT4 February 2008

13 4.7 Receiver Sensitivity Level Test Condition The HS receiver sensitivity and squelch test uses the TEST_SE0_NAK command. The electrical test tool invokes the TEST_SE0_NAK command from the test bed computer to the DM6467. Upon receiving this command from the host, the DM6467 device enters into a test mode where it continually responds with a NAK upon receiving an IN token. Once the test setup is done by the host on the test bed computer, the arbitrary waveform replaces the host generating an IN token waveform which forces the device to respond with a NAK. The test fixture has a switch that establishes a link between the device and the Host or the device and the arbitrary waveform generator. Two waveforms, one with a 32-bit SYNC field and another with a 12-bit SYNC field are used in constructing the IN token to be sent to the device. The waveform with 32-bit SYNC field is used for the receiver and squelch test. The 12-bit field is used for testing device capability on detecting the data transmission. Figure 10 displays the setup used for performing a receiver sensitivity level test. SMA Cable Arbitrary Waveform Generator (AWG5002) DM6467 USB Cable Test Fixture USB Cable Host PC (Electrical Test Tools) Differential Probe Oscilloscope Figure 10. Setup Diagram for Performing Receiver Sensitivity Level Test EL_16: Squelch Level. A high-speed capable device must implement a transmission envelope detector that indicates squelch (i.e., never receives packet) when a receiver s input falls below 100 mv differential amplitude EL_17: Receiver Level A high-speed capable device must implement a transmission envelope detector that does not indicate squelch (i.e., reliably receives packets) when a receiver exceeds 150 mv differential amplitude. SPRAAT4 February 2008 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification 13

14 References EL_18: 12-Bit SYNC Field The SYNC pattern used for high-speed transmission is required to be 15 KJ pairs followed by 2 K s, for a total of 32 symbols. Hubs are allowed to drop up to 4 bits from the start of the SYNC pattern when repeating packets; however, hubs must not corrupt any repeated bits of the SYNC field. Therefore, after being repeated by five hubs, a packet s SYNC field may be as short as 12 bits. The device attached to the fifth hub should be able to detect the SYNC. Table 6. Overall Results of 12-Bit SYNC Field Measurement Name Positive Peak Negative Peak USB Limits Status Receiver Level mv mv Must receive 150 mv Must receive 200 mv PASS Squelch Level mv mv Must not respond < 100 Must not respond < 50 PASS mv mv EL_18 Level - - Device should respond - PASS with minimum 12 bit SYNC field 4.8 USB Checklist A standard USB checklist from the USB Implementers Forum has been populated with information pertaining to the DM6467 device. For more information, see the TMS320DM64xx USB Compliance Checklist (SPRAAT5). 5 References Device High Speed Electrical Test Procedure - USB Implementers Forum ( 14 TMS320DM6467 Electrical Compliance to the USB 2.0 Specification SPRAAT4 February 2008

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