EVAL6474H. Stepper motor driver mounting the L6474. Description. Features
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1 Stepper motor driver mounting the L6474 Description Data brief The EVAL6474H demonstration board is a microstepping motor driver. In combination with the STEVAL-PCC009V communication board and the SPIN evaluation software, the board allows the user to investigate all the features of the L6474 device. The EVAL6474H supports the daisy chain configuration making it suitable for the evaluation of the L6474 in multi motor applications. EVAL6474H Features Voltage range from 8 V to 45 V Phase current up to 3 A rms SPI with daisy chain feature Socket for external resonator or crystal FLAG LED indicator Suitable for use in combination with the STEVAL-PCC009V March 05 DocID0766 Rev /0 For further information contact your local STMicroelectronics sales office.
2 Board description EVAL6474H Board description Table. EVAL6474H specifications Parameter Value Supply voltage (VS) 8 to 45 V Maximum output current (each phase) 3 A rms Logic supply voltage (VREG) Externally supplied: 3.3 V internally supplied: 3 V typical Logic interface voltage () Externally supplied: 3.3 V or 5 V internally supplied: VREG Low level logic input voltage 0 V High level logic input voltage () Operating temperature -5 to +5 C L6474H thermal resistance junction to ambient C/W typical. All logic inputs are 5 V tolerant. Figure. Jumper and connector location FLAG LED (Red) Application reference area Power supply connector (8 V - 45 V) SYNC output Master SPI connector JP: supply from master SPI connector JP3: Daisy chain termination Slave SPI connector JP4: STCK to slave SPI connector JP5: DIR to slave SPI connector ADCIN input regulation JP: to VREG connection OSCIN/OSCOUT connector Phase A connector Phase B connector AM069V /0 DocID0766 Rev
3 Board description Table. Jumpers and connectors description Name Type Function J Power supply Motor supply voltage J5 Power output Bridge A outputs J6 Power output Bridge B outputs J SPI connector Master SPI J3 SPI connector Slave SPI J4 NM connector OSCIN and OSCOUT pins J7 NM connector SYNC output TP (VS) Test point Motor supply voltage test point TP4 () Test point Logic interface supply voltage test point TP5 (VREG) Test point Logic supply voltage/l6474 internal regulator test point TP6 (GND) Test point Ground test point TP (STCK) Test point Step clock input test point TP8 (DIR) Test point DIR output test point TP3 (STBY/RES) Test point STBY/RES input test point TP7 (FLAG) Test point FLAG output test point Table 3. Slave SPI connector pinout (J) Pin number Type Description Digital input L6474 direction input Open drain output L6474 FLAG output 3 Ground Ground 4 Supply EXT_ (can be used as external logic power supply) 5 Digital output SPI Master In Slave Out signal (connected to the L6474 SDO output through daisy chain termination jumper JP) 6 Digital input SPI serial clock signal (connected to L6474 CK input) 7 Digital input SPI Master Out Slave In signal (connected to the L6474 SDI input) 8 Digital input SPI slave select signal (connected to the L6474 CS input) 9 Digital input L6474 step-clock input 0 Digital input L6474 standby/reset input DocID0766 Rev 3/0 0
4 Board description EVAL6474H Figure. EVAL6474H schematic EXT_ VREG SDO MISO VS DIR TP8 EXT_ DIR EXT_ VS VS TP VS + C9 00uF/63V OPTION MORSV-508-P VS J GND A A J5 MORSV-508-P B B J6 MORSV-508-P JP3 C 0nF/6V D C6 C7 C8 C0 00nF/50V 00nF/50V 00nF/50V 00nF/50V JP BAV99 C 0nF/50V VSB VSB VSA VSA CP VBOOT OUTA OUTA 8 + C9A 00uF/63V JP 3 L6474 OUTB 4 OUTB 5 PGND PGND 7 AGND 3 9 EPAD 9 TP6 JP5 J3 FLAG J DIR FLAG CK ncs STBY_RESET MISO SDO CK ncs STBY_RESET MISO SDI STCK SPI_OUT JP4 CON-FLAT-5X-80M STCK SPI_IN STCK STBY/RES TP TP3 Application reference TP4 TP5 VREG VREG VREG R 50k C5 00nF/4V + C4 0uF/4V C3 00nF/6.3V + C 47uF/6.3V VREG 3 ADCIN FLAG TP7 7 6 STBY_RESET FLAG U STCK DIR ncs CK SDI SDO SYNC VREG GND J4 N.M. OSCIN 7 R4 39k R3 39k R 39k OSCOUT 8 R5 470 ADCIN 5 STBY_RES FLAG SYNC C3 3.3nF/4V RED 3 4 STCK DIR CS CK SDI SDO 5 DL DGND C6 nf/4v C5 nf/4v C4 nf/4v R6 39k J7 N.M. AM076V 4/0 DocID0766 Rev
5 Board description Table 4. Bill of material Item Quantity Reference Value Package C 0 nf/6 V CAPC-0603 C 47 µf/6.3 V CAPC-36 3 C3 00 nf/6.3 V CAPC C4 0 µf/4 V CAPC-36 5 C5 00 nf/4 V CAPC C6, C7, C8, C0 00 nf/50 V CAPC C9A 00 µf/63 V CAPE-R8H-P35 8 C9 00 µf/63 V CAPES-R0HXX 9 C 0 nf/50 V CAPC C3 3.3 nf/4 V CAPC C4, C5, C6 nf/4 V CAPC-0603 DL LED diode (red) LEDC D BAV99 SOT-3 4 JP Jumper - open JPSO 5 4 JP, JP3, JP4, JP5 Jumper - closed JPSO 6 3 J, J5,J 6 Screw connector poles MORSV-508-P 7 J, J3 Pol. IDC male header vertical 0 poles CON-FLAT-5 x - 80 M 8 J4 N.M. STRIP54P-M- 9 J7 N.M. TPTH-44SQ R, R3, R4, R6 39 k RESC-0603 R 50 k TRIMM-00 x 50 x 0-64 W R5 470 RESC TP, TP, TP3, TP4, TP5, TP6, TP7,TP8 Test point TH 4 U L6474H HTSSOP8 DocID0766 Rev 5/0 0
6 Board description EVAL6474H Figure 3. EVAL6474H - layout (top layer) AM07V Figure 4. EVAL6474H - layout (inner layer ) AM07V 6/0 DocID0766 Rev
7 Board description Figure 5. EVAL6474H - layout (inner layer 3) AM073V Figure 6. EVAL6474H - layout (bottom layer) AM074V DocID0766 Rev 7/0 0
8 Board description EVAL6474H Thermal data Figure 7. Thermal impedance graph 5 0 Zth ( C/W) Time (s) AM075V 8/0 DocID0766 Rev
9 Revision history Revision history Table 5. Document revision history Date Revision Changes 0-Feb-0 Initial release. 8-Mar-05 Replaced easyspin by SPIN in Section : Description on page. Removed Figure 3. EVAL6474H - layout (silk screen) from page 6. Minor modifications throughout document. DocID0766 Rev 9/0 0
10 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 05 STMicroelectronics All rights reserved 0/0 DocID0766 Rev
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