Declarative semantics for concurrency. 28 August 2017

Transcription

1 Declarative semantics for concurrency Ori Lahav Viktor Vafeiadis 28 August 2017

2 An alternative way of defining the semantics 2 Declarative/axiomatic concurrency semantics Define the notion of a program execution (generalization of an execution trace) Map a program to a set of executions Define a consistency predicate on executions Semantics = set of consistent executions of a program Exception: catch-fire semantics Existence of at least one bad consistent execution implies undefined behavior.

3 Executions 3 Events Reads, Writes, Updates, Fences Relations Program order, po (also called sequenced-before, sb) Reads-from, rf W x 0 W y 0 W x 1 R x 1 rf po R y 0 rf R y 1 R x 0 rf W y 1

4 Executions 4 Definition (Label) A label has one of of the following forms: R x v r W x v w U(x v r v w ) F where x Loc and v r, v w Val. Definition (Event) An event is a triple id, i, l where id N is an event identifier, i Tid {0} is a thread identifier, and l is a label.

5 Executions 5 Definition (Execution graph) An execution graph is a tuple E, po, rf where: E is a finite set of events po ( program order ) is a partial order on E rf ( reads-from ) is a binary relation on E such that: For every w, r rf typ(w) {W, U} typ(r) {R, U} loc(w) = loc(r) valw (w) = val r (r) rf 1 is a function (that is: if w 1, r, w 2, r rf then w 1 = w 2 )

6 Some notations 6 Let G = E, po, rf be an execution graph. G.E = E G.po = po G.rf = rf G.R = {r E typ(r) = R typ(r) = U} G.W = {w E typ(w) = W typ(w) = U} G.RMW = {u E typ(u) = U} G.F = {f E typ(f ) = F} G.R x = G.R {r E loc(r) = x}...

7 Mapping programs to executions: Example 7 Store buffering (SB) x := 1 a := y x = y = 0 y := 1 b := x W x 0 W y 0 W x 0 W y 0 W x 0 W y 0 W x 1 W y 1 W x 1 W y 1 W x 1 W y 1 R y 0 R x 0 R y 1 R x 1 R y 0 R x 42

8 Mapping programs to executions: Definition 8 The thread subsystem associates a sequential execution graph to every command. A program execution is obtained by joining the sequential execution graphs of the constituent threads. Definition An execution graph G is called sequential if the following hold: tid(a) = 0 for every a G.E G.po is a total order on G.E G.rf =

9 From commands to sequential execution graphs 9 Initial execution graph: G - the empty graph silent c, s ε c, s c, s, G = c, s, G non-silent c, s l c, s l ε a = n, 0, l n {id(b) b G.E} c, s, G = c, s, Add(G, a) where Add(G, a) is the execution graph G given by: G.E = G.E {a} G.po = G.po (G.E {a}) G.rf = G.rf Definition (Execution graph of a command) G is a an execution graph of a command c with a final store s if c, s 0, G = skip, s, G.

10 Mapping programs to executions: Definition 10 Definition (Thread restriction) Given i Tid and an execution graph G, G i denotes the sequential execution graph obtained by restricting G to the events {a G.E tid(a) = i}, modifying their thread identifiers to 0, and discarding all rf-edges. Definition (Execution graph of a program) G is an execution graph of a program P (with an outcome O) if G i is an execution of P(i) (with final store O(i)) for every i Tid.

11 Consistency predicate 11 Let X be some consistency predicate (on execution graphs) Definition (Allowed outcome under a declarative model) An outcome O is allowed for a program P under X if there exists an execution graph G such that: G is an execution graph of P with outcome O. G is X-consistent. Exception: catch-fire semantics... or if there exists an execution graph G such that: G is an execution graph of P. G is X-consistent. G is bad.

12 Completeness 12 The most basic consistency condition: Definition (Completeness) An execution graph G is called complete if codom(g.rf) = G.R i.e., every read reads from some write.

13 Sequential consistency 13 the result of any execution is the same as if the operations of all the processors were executed in some sequential order, respecting the order specified by the program [Lamport, 1979]

14 Sequential consistency [Lamport] 14 Definition Let sc be a total order on G.E. G is called SC-consistent wrt sc if the following hold: If a, b G.po then a, b sc. If a, b G.rf then a, b sc and there does not exist c G.W loc(b) such that a, c sc and c, b sc. Definition An execution graph G is called SC-consistent if the following hold: G is complete. G is SC-consistent wrt some total order sc on G.E.

15 SB example 15 Store buffering (SB) x := 1 a := y x = y = 0 y := 1 b := x Allowed W x 0 W y 0 Forbidden W x 0 W y 0 W x 1 W y 1 W x 1 W y 1 R y 0 R x 1 R y 0 R x 0

16 Sequential consistency (Alternative) 16 Definition (Modification order (aka coherence order)) mo is called a modification order for an execution graph G if mo = x Loc mo x where each mo x is a total order on G.W x. Definition (Alternative SC definition) An execution graph G is called SC-consistent if the following hold: G is complete There exists a modification order mo for G such that G.po G.rf mo rb is acyclic where: rb = G.rf 1 ; mo \ id (from-reads / reads-before)

17 SB example 17 Store buffering (SB) x := 1 a := y x = y = 0 y := 1 b := x Allowed W x 0 W y 0 Forbidden W x 0 W y 0 W x 1 W y 1 W x 1 W y 1 R y 0 R x 1 R y 0 R x 0

18 Equivalence 18 Theorem The two SC definitions are equivalent. Proof (sketch). Lamport SC alternative SC: Take mo x = [W x ]; sc; [W x ]. Then, G.po G.rf mo rb sc. Alternative SC Lamport SC: Take sc to be any total order extending G.po G.rf mo rb.

19 Relaxing sequential consistency 19 SC is very expensive to implement in hardware. It also forbids various optimizations that are sound for sequential code. What most hardware guarantee and compilers preserve is SC-per-location (aka coherence). Definition An execution graph G is called coherent if the following hold: G is complete For every location x, there exists a total order sc x on all accesses to x such that: If a, b [RWx ]; G.po; [RW x ] then a, b sc x If a, b [Wx ]; G.rf; [R x ] then a, b sc x and there does not exist c G.W x such that a, c sc x and c, b sc x.

20 Alternative definition of coherence I 20 SC: po rf mo rb is acyclic COH: po loc rf mo rb is acyclic Definition Let mo be a modification order for an execution graph G. G is called coherent wrt mo if G.po loc G.rf mo rb is acyclic (where rb = G.rf 1 ; mo \ id). Theorem An execution graph G is coherent iff the following hold: G is complete G is coherent wrt some modification order mo for G.

21 Bad patterns I 21 R x rf po W x no-future-read a := x / 1 x := 1 rf U x rmw-1 r := CAS(x, 1, 1) / 1 Recall: W is either a write or an RMW. R is either a read or an RMW.

22 Bad patterns II 22 x := 1 x := 2 a := x / 2 a := x / 1 W x mo po W x coherence-ww W x mo W x rf po R x coherence-wr W x rf mo R x W x coherence-rw W x W x rf mo rf R x R x coherence-rr po po

23 Bad patterns III 23 W x mo rf rmw-2 U x mo mo W x W x U x rf atomicity In coherent executions, an RMW event may only read from its immediate mo-predecessor.

24 Alternative definition of coherence II 24 Theorem Let mo be a modification order for an execution graph G. G is coherent wrt mo iff the following hold: rf; po is irreflexive. mo; po is irreflexive. mo; rf; po is irreflexive. rf 1 ; mo; po is irreflexive. rf 1 ; mo; rf; po is irreflexive. rf is irreflexive. mo; rf is irreflexive. rf 1 ; mo; mo is irreflexive. (no-future-read) (coherence-ww) (coherence-rw) (coherence-wr) (coherence-rr) (rmw-1) (rmw-2) (rmw-atomicity)

25 Examples (aka litmus tests ) 25 Coherence test x := 1 a := x / 2 x = 0 x := 2 b := x / 1 Store buffering x := 1 a := y /0 x = y = 0 y := 1 b := x /0

26 Atomicity 26 Parallel increment x = 0 a := FAA(x, 1) b := FAA(x, 1) Guarantees that a = 1 b = 1. Can we implement locks in this semantics? Spinlock implementation lock(l) : r := 0; while r do r := CAS(l, 0, 1) unlock(l) : l := 0

27 Implementing locks? 27 Under COH, the spinlock implementation does not guarantee mutual exclusion. Spinlock implementation lock(l) : r := 0; while r do r := CAS(l, 0, 1) unlock(l) : l := 0 Lock example lock(l) x := 1 a := y /0 unlock(l) lock(l) y := 1 b := x /0 unlock(l)

28 Message passing More generally, COH is often too weak: x := 42; y := 1 x = y = 0 a := y; while a do a := y; b := x /0 x := 42; y := 1 x = y = 0 a := y; /1 b := x /0 MP is a common programming idiom. How can we disallow the weak behavior? 28

29 Supporting message passing 29 W x mo W x rf po R x coherence-wr W x mo W x rf (po rf) + R x coherence-wr Solution: Strengthen the notion of an observed write. In other words, make rf-edges synchronizing.

30 Release/acquire (RA) memory model 30 SC: po rf mo rb is acyclic COH: po loc rf mo rb is acyclic RA: (po rf) + loc mo rb is acyclic Definition Let mo be a modification order for an execution graph G. G is called RA-consistent wrt mo if (po rf) + loc mo rb is acyclic for some modification order mo for G (where rb = G.rf 1 ; mo \ id). Definition An execution graph G is RA-consistent if the following hold: G is complete G is RA-consistent wrt some modification order mo for G.

31 Alternative definition of RA consistency 31 Theorem Let mo be a modification order for an execution graph G. G is RA-consistent wrt mo iff the following hold: (po rf) + is irreflexive. mo; (po rf) + is irreflexive. rf 1 ; mo; (po rf) + is irreflexive. rf 1 ; mo; mo is irreflexive. (no-future-read) (coherence-ww) (coherence-wr) (rmw-atomicity)

32 Hardware implementation of RA 32 RA is cheaper to implement than SC, but some architectures still require some fences. On Power, a lightweight fence (lwsync) suffices, and RA is still cheaper than SC. Release write lwsync ; store Acquire read load ; lwsync (or load ; bc ; isync) ARMv7 is like Power, but has no lightweight fence. Release write dmb ; store Acquire read load ; dmb (or load ; bc ; isb) ARMv8 has special release/acquire accesses. Alternative: acquire read load ; dmb ld On TSO, no fences are needed. (See also exercise.)

33 Mixing the models 33 COH < RA < SC Revisit the MP idiom: x := 42 y := 1 a := y while a do a := y b := x /0 We only need the last read of y to synchronize. Idea: introduce access modes. x := rlx 42 y := rel 1 a := y rlx while a do a := y a := y acq b := x rlx /0

34 Happens-before 34 Each memory accesses has a mode: Reads: rlx or acq Writes: rlx or rel RMWs: rlx, acq, rel or acq-rel Strength order is given by (the transitive closure of): Synchronization: rlx acq rel acq-rel Happens-before: G.sw = [W rel ]; G.rf; [R acq ] G.hb = (G.po G.sw) +

35 Towards C/C++11 memory model 35 SC: po rf mo rb is acyclic COH: po loc rf mo rb is acyclic RA: (po rf) + loc mo rb is acyclic C11: hb loc rf mo rb is acyclic Definition Let mo be a modification order for an execution graph G. G is called C11-consistent wrt mo if hb loc rf mo rb is acyclic (where rb = G.rf 1 ; mo \ id). Definition An execution graph G is C11-consistent if the following hold: G is complete G is C11-consistent wrt some modification order mo for G.

36 The C/C++11 memory model 36 nonatomic relaxed release/ acquire sc The full C/C++11 is more general: Non-atomics for non-racy code (the default!) Four types of fences for fine grained control SC accesses to ensure sequential consistency if needed More elaborate definition of sw ( release sequences )

37 Summary 37 A declarative approach for (weak) concurrency semantics Uniformly and modularly handle various models Important weakenings of SC (coherence, RA) with alternative formulations based on bad patterns Introduction to the C/C++11 memory model

38 Exercise: Extended coherence order 38 Let G be a coherent execution wrt some modification order mo for G. Let eco = (rf mo rb) Does eco totally order all accesses to a given location x? 2. Provide a simplification of eco that avoids the use of transitive closure.

39 Exercise: RA vs. TSO 39 Do RA and TSO have the same behaviors? 1. Construct a program with two threads that has different outcomes under TSO and RA. 2. Construct a program without write-write races that distinguishes the two models.

40 Exercise: Write-before 40 Let G be a complete execution without RMW events and let: wb = [W]; (po rf) + loc ; [W] ([W]; (po rf) + loc ; rf 1 ; [W]\id) 1. Show that G is RA-consistent iff wb is acyclic. 2. (Optional, difficult) Extend the definition of wb to work for executions with RMW events. 3. (Optional, difficult) Can one define an analogue wb relation in terms of just G, such that G is SC-consistent iff wb is acyclic?