Encryption and Decryption by AES algorithm using FPGA

Transcription

1 Encryption and Decryption by AES algorithm using FPGA Sayali S. Kshirsagar Department of Electronics SPPU MITAOE, Alandi(D), Pune, India Savita Pawar Department of Electronics & Telecommunication SPPU MITAOE, Alandi(D), Pune, India Abstract This paper presents AES (Advanced Encryption Standard), it is a cryptographic algorithm used to secure digital data. We have compared two architectures, one has a generic architecture and the other one have a clock gating approach. The later one is supposed to be more area efficient and power efficient. AES is Federal Information Processing Standard (FIPS), also known as Rjindael algorithm. It uses 128 bit cipher key and 128 bit plain text for encryption and decryption. For encryption, a block named key schedule is used which produces the cipher key packets in 32 bit form and with the plain text they both are transformed in a unique way to give the encrypted text of the same size. This technique effectively reduces the power dissipation in the clocking network. For implementing AES Rijndael algorithm on FPGA and ASIC Verilog Hardware Descriptive Language is used. Xilinx ISE Design Suite version 14.7 is used for the Synthesis and Simulation of the code. The design has been successfully tested on Altera Cyclone II EP2C35F672C6 FPGA. The results on different platforms have been compared. Keywords AES, FIPS, Rijndael, FPGA, plaintext, ciphertext, Daemen and Vincent Rijmen, is selected [2].This algorithm comes in 128 bits, 192 bits and 256 bits. The basic unit of processing in the AES algorithm is a byte, which is group of eight bits treated as a single entity [1]. Internally, the AES algorithm s operations are performed on a two-dimensional array of bytes called the State. For our ease, the state can also be written in the form of matrix. This matrix contains four rows of bytes. Each row of a state consists of N b numbers of bytes, where N b is the length of block divided by 32. The AES algorithm is implemented on hardware as well as software. Due to high power consumption in FPGAs, there are few architecture designs targeting low power or energy efficient AES implementation in FPGAs. Most of the designs are defined to be low area and energy efficient, do not have their power consumption data available to allow any sort of direct comparison. Various Combinations of low power consumption techniques are used by many researches to provide energy efficient FPGA s based AES implementation. C I. INTRODUCTION RYPTOGRAPHY is the technology and study of creating and making use of systems for communicating in secret through communication channels that are not secure. Nw-a-days, it has become imperative to secure our digital data for the security reasons. Be it banks important account statements or classified military data, we cannot let them to go in wrong hands. Continuous development is seen in Cryptographic Techniques. Before AES came into existence, the Data Encryption Standard (DES) was standard for encryption [2].A group of 15 AES candidate algorithms were declared in August All algorithms that were declared by AES candidates due to successful breaking of small key length were experimented by various cryptographic researchers around the world. Five algorithms were selected and subjected to further analysis. Finally, on October 2, 2000, NIST declared that the Rijndael algorithm, invented by Joan II. Overview of AES A full AES implementation can be divided into two main components- the cipher and the key expander. The cipher is the component which is used to perform encryption or decryption on blocks of input data, while the key expander is responsible for preparing the input key for use by the cipher in each round. There are four transformations provided in this algorithm: SubBytes, ShiftRows, MixColumns and AddRoundKey for encryption. The first and the last rounds differ from other rounds in that there is an initial AddRoundkey transformation at the beginning of the initial round and MixColumns transformation is not performed in the last round. The Key Schedule block produces a new key everytime for the rounds from the cipher key whichis given at the initial round.

2 Table I: Number of Rounds ( a word is 32 bits ) Key length (words) Number of rounds (Nr) AES AES AES A. Rijndael Mathematics The computations required in this algorithm are mainly done in the finite field. This field is a commutative ring in which the non-zero figures/compnents have multiplicative inverses. The field used is Galois Field (2 8 ). For our convenience, the notations described here are hexadecimal. Multiplication of two polynomials in finite field is obtained by performing modulo with an irreducible polynomial to ensure that the final result stays within the used finite field. This can be achieved by first multiplying each term of the second polynomial with all of the elements of the first polynomial. Figure 1: MixColumn Multiplication on column of a state III. AES Encryption Process Fig.2 gives the flowchart for the AES encryption Process. B. Encryption Transformations Sub-bytes: In these steps each byte of the state array is to be replaced by its equivalent byte from the S-BOX or the Inverse S- BOX. These steps introduce non-linearity in the cipher. C. ShiftRows : The ShiftRows function performs byte wise circular shifts on each of the rows of the State, and is intended to transpose or move bytes throughout the State in each round. Each row is rotated left by a different number of bytes; except the first row. D. MixColumns : This method is based on Galois Field multiplication. Each byte of a column is replaced by another value that is a function of all four bytes in the given column. The columns are considered as polynomials over GF (2 8 ) and multiplied modulo x with a fixed polynomial a(x), given by the following equation. a(x) = {03} x 3 + {01}x 2 + {01}x + {02}. AddRoundKey : There is simple bitwise XOR function used between the state matrix and the cipher key produced by the Key Schedule. Figure 2: AES Encryption Flow A. Decryption Transformations AddRoundKey is the inverse function of itself because the XOR function present in it which is defined by its inverse. The round keys genersted needs to be selected in the reverse order.

3 InvShiftRows functions similar to ShiftRows, only the last three rows of the state are shifted right cyclically instead of left. InvSubBytes is done using a pre-calculated substitution table called InvS-box. This table contains 256 numbers (from 0 to 255) and their respective values. InvMixColumns is a mixing operation that generally operates on the columns of the state, combining the four bytes in each column. It is basically a matrix multiplication but in Galois field. Fig. 3 shows the matrix multiplication representation. Figure 3:InvMixColumn Multiplication on a column of a state IV. AES Decryption Process Fig.4 gives the flowchart for the AES decryption Process. Figure 4: AES Decryption Flow round uses the original input key and for the remaining rounds the keys produced by the key expansion are used. The key expansion produces a four byte word at a time, based on the previous word and the word one key length back. The pseudocode for KeyExpansion is shown below. fori=0 to Nk - 1 wi = keyi end fori = Nk to 4(Nr + 1) - 1 temp = wi-1 if (i mod Nk = 0) temp = SubWord(RotWord(wi-1)) XOR Rcon(i / Nk) else if (Nk> 6 and i mod Nk = 4) temp = SubWord(wi-1) end if wi = wi-nk XOR temp end The RotWord cyclically shifts each byte in a word startin from a single byte to the left. The Rcon is a constant word array, and only the leftmost byte in each word is nonzero [8]. V. Design Methodology and fpga implementation To optimize the power and area we are implementing RTL clock gating technique. For comparison, we also implemented one circuit with generic architecture.. To create a novel architecture for AES we used FSM to execute the encryption and decryption using a common block. This resource sharing reduced the area effectively. A finite-state machine (FSM) is a mathematical model for computing. It is assumed as a machine that is in finite number of states defined for that machine. The machine is in only one state at a time. It can change to different states when started by the transition state method. A finite state machine is defined as a number of states, and the triggering condition for each transition. Finite-state machines can resolve and represent many problems, among which are automation(design), parsing, and other applications. 1) Key Schedule Key schedule consists of two modules, key expansion and selection of the round key. Key expansion is used to generate the round keys for each round based on the original input key. The initial

4 RTL Schematic and Description done busy Signal to indicate the presence of encrypted or decrypted data at the output port. Signal to indicate the initialization of rounds of the aes. Output Output Table. III describes the different modes of the finite state machine which depend on the value of the input signal addr. Hexadecimal notation is used to describe the value of addr. Table III: Modes of the FSM Figure 5: AES module The input and output port is shared between encrypted data and decrypted data Burst-mode communication varies from traditional continuous-mode communication in that data is transmitted in bursts or packets of 32 bit each rather than in a continuous data stream. As all the inputs and outputs are 128-bit wide so a burst operation for both writing and reading of data on 32-bit port is utilized. Fig. 5 represents the black box view of the AES module. Table II lists the total input/output signals of the module with their functional description. Table II: Signals of the module AES add r 00h 02h 04h 08h 80h Mode Data at the input port will be accepted in bursts as key. Data at the input port will be accepted in bursts as plaintext needed for encryption. Data at the input port will be accepted in bursts as ciphertext needed for decryption. Data at the output port is the ciphertext obtained in bursts after encryption. Data at the output port is the plaintext obtained in bursts after decryption. Operation write write write read Read Name Description Direction clk Clock signal to the aes. rst Reset signal to the aes. addr 8-bit wide signal used for different modes of FSM. burst Signal used to describe burst read and burst write operation. req Signal used to acknowledge the presence of input data and registering it. r_w Read or Write signal. High for reading and Low for writing. din 32- bit wide signal used for providing data to the aes. dout 32- bit wide signal used for providing encrypted or decrypted data. Output VI. Synthesis and Simulation results We have utilized Flip Flop based clock gating to improve the performance. The results of both the designs i.e. the generic AES architecture and clock gated AES architecture are compared for both FPGA and ASIC. The design for AES has been coded by Verilog HDL. Clock Gating was used to reduce the power consumption. The synthesis and simulation results are achieved using Xilinx ISE For hardware implementation Virtex 5, XC5VLX30 and FF676 are selected as Family, Device and Package respectively.

5 A. Simulation Figure 6(a) and 6 (b) discusses the results of the encryption process and 7(a) and 7(b) discusses the results of the decryption process. 7(a): s for Decryption. 4 long words (each 32-bit wide). FigFigure Figure 6(a): s for Encryption. 4 long words(each 32-bit wide). Figure7(b): Output for Decryption. 4 long words(each 32-bit wide). B. Synthesis Figure 8 discusses the synthesis results of the AES Design with RTL clock gating Figure 6(b): Output for Encryption. 4 long words(each 32-bit wide).

6 Figure 8: Device Utilization Summary for AES Design with RTL Clock Gating VII. Comparison of POWER REPORTS Power dissipation was evaluated for generic AES design and Clock gated AES design. For FPGA we used Xilinx Power Estimator to measure the Dynamic power. Figure 9 provides the power summary generated from XPE for the Power efficient AES design. implementation was discussed. Employing the Design Methodologies the design was successfully synthesized using both Xilinx ISE 14.7 and Quartus II 8.1. The discussed approach resulted in a flexible economic key expansion functionality to keep the amount of power consumed per operation to as low a level as possible which can be seen in the results.the Synthesis and Power reports give the area and power dissipation on the desired FPGA. The result shows that this design with special mode of data transmission reduces the area and power consumption some extent. A FPGA Based implementation of area-optimized AES encryption and decryption algorithm which meets the actual application is proposed in this thesis. After being coded with VHDL Hardware Description Language, Xilinx ISE 14.7i is used to synthesize and simulate the VHDL implementation of AES algorithm. Xilinx XC3SD1800A FPGA is taken as the target device. Altera s Cyclone II FPGA (EP2C35F672C6) was also targeted to implement the algorithm and Quartus II 8.1 software was used for that purpose. Ultimately, a synthesis simulation of the new algorithm has been done and successfully implemented AES encryption/decryption on single FPGA. IX. References Figure 9: Xilinx Power Estimator VIII. Conclusion In this thesis, the development and assessment of an Area Efficient and Low Power FPGA based full AES [1] J. Daemen and V. Rijmen, "AES Proposal: Rijndael. NIST AES Proposal," June Available at [2] National Institute of Standards and Technology (U.S.), "Advanced Encryption Standard (AES)," Available at AES.pdf. [3] A. Rudra, P.K. Dubey, C.S. Jutla, V. Kumar, J.R. Rao, P. Rohatgi, "Efficient Rijndael encryption implementation with composite field arithmetic," Lecture Notes in Computer Science 2162 (2001) [4] J. Daemen, V. Rijmen, " AES proposal: The Rijndael Block Cipher, " Version 2 (Sept. 1999) pp [5] Mr. Atul M. Borkar, Dr. R. V. Kshirsagar and Mrs. M. V. Vyawahare, FPGA Implementation of AES Algorithm, International Conference on Electronics Computer Technology (ICECT), pp , rd.

7 [6] Leelavathi.G, Prakasha S, Shaila K, Venugopal K R, L. M. Patnaik "Design and Implementation of Advanced Encryption Algorithm with FPGA and ASIC", International Journal of Research in Engineering & Advanced Technology [7] (IJREAT), Volume 1, Issue 3, June-July, A. Menezes, P. Van Oorschot, and S. Vanstone, Handbook of applied cryptography, CRC press, New York, 1997, pp [8] Xinmiao Zhang, Student Member, IEEE, and Keshab K. Parhi, Fellow, IEEE "High-Speed VLSI Architectures for the AES Algorithm", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 9, SEPTEMBER [9] Frank Emnett and Mark Biegel,"Power Reduction Through RTL Clock Gating", SNUG San Jose [10] Dushyant Kumar Sharma,"Effects of Different Clock gating Techniques on Design", International Journal of Scientific & Engineering Research Volume 3, Issue 5, May