TABLE OF CONTENTS CHAPTER NO. TITLE PAGE NO.

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1 vii TABLE OF CONTENTS CHAPTER NO. TITLE PAGE NO. ABSTRACT LIST OF TABLES LIST OF FIGURES LIST OF SYMBOLS AND ABBREVIATION iii xii xiv xvii 1 INTRODUCTION GENERAL TYPES OF WIRELESS COMMUNICATION NETWORKS EVOLUTION OF WIRELESS COMMUNICATION NETWORKS SECURITY ISSUES IN WIRELESS COMMUNICATION Wireless Security Threats Security Objectives and Services NEED FOR SOFTWARE-DEFINED RADIO SECURITY ISSUES IN SOFTWARE DEFINED RADIO MOTIVATION OF RESEARCH OBJECTIVES OF THESIS ORGANIZATION OF THESIS 18

2 viii CHAPTER NO. TITLE PAGE NO. 2 LITERATURE REVIEW INTRODUCTION SECURITY ISSUES IN SDR A SURVEY HARDWARE IMPLEMENTATION OF CRYPTOGRAPHIC ALGORITHM A SURVEY CONCLUSION 29 3 DESIGN AND DEVELOPMENT OF RECONFIGURABLE ARCHITECTURE FOR DATA INTEGRITY UNIT INTRODUCTION HASHING ALGORITHM SHA Algorithm Description Mathematical Model Operations on Words Message Padding SHA-192 Hash Computation Computing Message Digest Security Analysis MD-5 ALGORITHM Algorithm Description HARDWARE IMPLEMENTATION OF MD UNIFIED ARCHITECTURE OF MD5 AND SHA Hash Function Core RESULTS AND DISCUSSION 53

3 ix CHAPTER NO. TITLE PAGE NO Synthesis Output Area Delay Product Analysis Throughput Analysis OUTCOME OF PLACING AND ROUTING POWER CONSUMPTION VERIFICATION AND VALIDATION OF THE RECONFIGURABLE HARDWARE Verification of the Hardware Testing Of Reconfigurable Hardware PERFORMANCE COMPARISON SUMMARY 63 4 DESIGN AND DEVELOPMENT OF RECONFIGURABLE ARCHITECTURE FOR AUTHENTICATION UNIT INTRODUCTION PROPOSED METHODOLOGY RSA Algorithm RSA Signature Algorithm D.H Algorithm ARCHITECTURE FOR AUTHENTICATION UNIT Implementation of Divider Architecture Modular Inverse Modular Exponentiation Montgomery Multiplication Montgomery Multiplication for RSA Exponentiation 79

4 x CHAPTER NO. TITLE PAGE NO. 4.4 IMPLEMENTATION OF AUTHENTICATION UNIT VERIFICATION AND TESTING OUTCOME OF PLACING AND ROUTING POWER CONSUMPTION PERFORMANCE ANALYSIS SUMMARY 86 5 DESIGN AND DEVELOPMENT OF AES-128/192/256 ENCRYPTOR AND DECRYPTOR UNIT INTRODUCTION ENCRYPTOR / DECRYPTOR ARCHITECTURE AES-128/192/ IMPLEMENTATION OF AES-128/192/256 ENCRYPTION ARCHITECTURE Encryption Module Results and Discussion Substitution Bytes (S - Box) Shift Rows Mix-Column Key expansion Add round key IMPLEMENTATION OF AES-128/192/256 DECRYPTION ARCHITECTURE Inverse Shift Rows Inverse Byte Substitution 104

5 xi CHAPTER NO. TITLE PAGE NO Inverse Mix Column Decryption Architecture IMPLEMENTATION OF AES ENCRYPTOR AND DECRYPTOR Synthesis Output Testing and Verification VERIFICATION AND VALIDATION OF THE RECONFIGURABLE HARDWARE Verification of the Hardware PERFORMANCE ANALYSIS SUMMARY CONCLUSION AND FUTURE WORK CONCLUSION SCOPE FOR FUTURE WORK 117 REFERENCES 119 LIST OF PUBLICATIONS 129 VITAE 130

6 xii LIST OF TABLES TABLE NO. TITLE PAGE NO. 1.1 Basic Enforcement of SDR Security Mechanism Attacks on Standard Hash Function Device e Utilization Summary of MD5, SHA-192 and Combined Architecture Throughput Analysis MD5, SHA-192 and Combined Architecture Power Consumed by Target Device Performance Comparison of Proposed Unified Architecture with Previous Work Binary (radix 2) Non- Restoring Division Hardware Utilization of Divider Algorithm to Compute Extended GCD of Two Factors Hardware Utilization of Inverse Algorithm Algorithm to perform A*B mod n Algorithm to perform Four-to-two CSA Montgomery Multiplication Device utilization summary of Montgomery Multiplication Algorithm to Perform Modified Modular Multiplier Exponentiation C d Mod n Device utilization summary of Modular Exponentiation Device utilization summary of RSA and DH Algorithms Device Utilization of Unified Architecture 81

7 xiii TABLE NO. TITLE PAGE NO Performance Comparison of Proposed Design with Previous Works Device Utilization Summary for Synthesizing Target Device Comparison of Hardware Performance of All AES Candidates Using Different Architecture Comparison of Performance of Proposed Architecture with Different Devices 114

8 xiv LIST OF FIGURES FIGURE NO. TITLE PAGE NO. 1.1 Types of Wireless Communication Networks Evolution History of WWAN Systems Accessing Multiple Networks and Services Through Multi-Mode Software An Overview of Proposed Models SHA-192 Compression Function Compression Function MD Operation Of Single Step Of MD Hardware Architecture of MD Data Transformation in MD5 Hardware Architecture Unified Hardware Architecture of MD5 And SHA-192 Hash Function Data Transformation for Combined Hash Computation Area-Delay Product Comparisons Throughput Comparisons of Proposed Design RTL Schematic of Combined Architecture Schematic Block Diagram of Integrity Unit View of Integrity Unit after Routing Hash Output for MD-5 Unified Architecture Hash Output for SHA-192 Unified Architecture Block Diagram of Reconfigurable Authentication Unit Flow chart of Non-restoring Division Non-Restoring Divider Architecture Block Diagram of 4 to 2 CSA Area Utilization Comparisons 82

9 xv FIGURE NO. TITLE PAGE NO. 4.6 Schematic Diagram of Authentication Unit View of Authentication Unit after Routing Power Consumption Comparisons Block Diagram of AES- 128/192/256 Encryptor and Decryptor Architecture Encryption Process of AES Schematic Diagram of substitution bytes Block Diagram of FDC Schematic Blocks Inside substitution byte Schematic Diagram of Shift Rows Functional Blocks Inside Shift Row Module Schematic Diagram of Mix-column Functional Blocks Inside Mix-Column Module Blocks Inside Polynomial Multiplication Block Schematic Diagram For Key Expansion Schematic Diagram Of Add Round key Functional Blocks Inside Add Round key Functional Blocks Inside Processing Block Gates Inside Block Schematic Diagram of Encryption Module Decryption Process of AES Schematic Diagram of Inverse Shift Row Schematic Diagram of Inverse Byte Substitution Operation Functional Blocks Inside Inverse Byte Substitution module Schematic Diagram of Inverse Mix Column 106

10 xvi FIGURE NO. TITLE PAGE NO Schematic Diagram of Decryption Module Schematic Diagram of Encryptor and Decryptor RTL schematic of Encryptor and Decryptor Simulated Output of 256 bit key Simulated Output of 198 bit key Simulated Output of 128-bit key 112

11 xvii LIST OF SYMBOLS AND ABBREVIATIONS Symbols A, B, C, D - 32-bit registers Y q bit block of message H i - Buffer to Store Initial Hash Values CV q - Chaining Variable C - Cipher Text Kt - Constant Words K i - Constant Input X<< s - Circularly Shifting X Left by S Bit Position d - Decryption Key A V B - Denotes Bit-Wise Logical OR of A and B A B - Denotes Bit-Wise Logical AND of A and B ~ (A) - Denotes Bit-Wise Logical Complement of A A XOR B - Denotes Bit-Wise Logical Exclusive OR of A and B, X XOR Y - Denotes Bit-Wise XOR of X and Y XY - Denote The Bit Wise AND of X and Y. e - Encryption Key MHz - Frequency in Mega Hertz GF(p) - Galois Field gcd - Greatest Common Divisor Nk - Key Length p,q - Large Prime Numbers - Less than or Equal to < - Less Than V - Logical or operation - Logical AND operation Mbps - Megabits per second

12 xviii m i - Message input + - Modulo-2 32 addition Nb - Number of blocks Nr - Number of rounds ft (A,B,C) - Nonlinear function of (A,B,C) mw - Power in mill watts n - Product of two primes p and q - Primitive Root of q M - Plain Text R(x) - Round Key (n) - toteint function W i - words of the message schedule Abbreviation AC - Attribute certificate AES - Advanced Encryption Standard ASICs - Application Specific Integrated Circuits CDMA - Code Division Multiple Access CLBs - Combinational Logical Blocks CLR - Clear input CODEC - coder/decoder CSR - Carry Save Representation D-AES - Diversified- Advanced Encryption Standard DES - Data Encryption Standard Dffs - D-flip-flops DH - Diffie- Hellman Algorithm DSPs - Digital Signal Processors FCC - Federal Communication Commission FIPS - Federal Information Processing Standard FPGA - Field Programmable Gate Array

13 xix HMAC - Medium Access Control I/Os - Input/output Blocks IP - Internal Protocol LUT - Look up Table MD4 - Message Digest 4 MD5 - Message Digest 5 MIMO - Multiple Input Multiple Output NIST - National Institute of Standards and Technology NSA - National Security Agency OFDMA - Orthogonal Frequency Division Multiple Access PDA - Personal Digital Assistants PKC - Public key Certificate RSA RISC - Reduced Instruction Set Computing processor RSA - Rivest Shamir Adelmen SCA - Software Communication Architecture SDR - Software-Defined Radio SHA-1 - Secure Hash Algorithm-1 SHA Secure Hash Algorithm-192 SP-network - Substitution Permutation network TDMA - Time Division Multiple Access VHDL - Very High Speed Integrated Circuit Hardware Description Language VLSI - Very Large Scale Integrated circuit WAP - Wireless Application Protocol WPAN - Wireless Personal Area Networks WLAN - Wireless Local Area Networks WMAN - Wireless Metro Area Network WWAN - Wireless Wide Area Networks WCDMA - Wireless Code Division Multiple Access