Cache-Conscious Concurrency Control of Main-Memory Indexes on Shared-Memory Multiprocessor Systems

Size: px
Start display at page:

Download "Cache-Conscious Concurrency Control of Main-Memory Indexes on Shared-Memory Multiprocessor Systems"

Transcription

1 Cache-Conscious Concurrency Control of Main-Memory Indexes on Shared-Memory Multiprocessor Systems Sang K. Cha, Sangyong Hwang, Kihong Kim, Keunjoo Kwon VLDB 2001 Presented by: Raluca Marcuta 1 / 31

2 1 Introduction Background and Motivation Objectives 2 Concurrency Control Approaches Physical Versioning Lock Coupling 3 Implementation Main Idea of OLFIT Node Operations Tree Operations 4 Experimental Evaluation Pure Search Performance Pure Update Performance Performance with Varying Update Ratio 5 Conclusions and Future Work 6 Related Work 7 Critique 2 / 31

3 Background and Motivation Cache-conscious index structures Approach : reduce cache misses by increasing index fanout Goal : improve search performance Examples : CSB+-tree (Cache Sensitive B+-tree) CR-tree (cache-conscious version of the R-tree) Concurrency control (CC) in shared-memory multiprocessors Crucial for real-world main memory database applications Concurrent updates and reads Approaches : physical versioning, lock coupling, tree-level latching 3 / 31

4 Objectives A new, more efficient CC scheme for main memory indexes OLFIT : Optimistic Latch-Free Index Traversal Customized for B+-trees and CSB+-trees Eliminates latching during index traversal Reduces latching during index update Goals Multiprocessor scalability of : index search update performance 4 / 31

5 Physical Versioning Approach Index readers do not interfere with updaters New version of the node for the updater Incorporation of new version : tree-level latching or node-level latching Advantages Latch-free traversal of indexes High concurrency for read transactions Disadvantages High cost for creating versions - memory allocation and write Index performance decreases with the increase of update ratio Poor scalability of update performance 5 / 31

6 Lock Coupling Approach Latching nodes during index traversal Hold latch on node until request granted for latch on child Disadvantages Poor scalability Heavy latching of the nodes Latching index nodes => coherence cache misses Coherence cache misses A processor s cached copy of a block is invalidated by another processor updating the cache block. 6 / 31

7 Coherence Cache Misses Caused by Latching Latches : placed inside the index node Latching operation Acquire/release latch Involves memory write : Invalidation of cache block regardless if the node updated 7 / 31

8 Coherence Cache Misses Caused by Latching (cont.) 8 / 31

9 Coherence Cache Misses Caused by Latching (cont.) 9 / 31

10 Coherence Cache Misses Caused by Latching (cont.) 10 / 31

11 Coherence Cache Misses Caused by Latching (cont.) 11 / 31

12 Coherence Cache Misses Caused by Latching (cont.) 12 / 31

13 Rationale Purpose of index CC Index readers reach the correct leaf without interfering with concurrent updaters Index updaters do not interfere with each other Criteria for a good CC scheme High degree of parallelism Problem Probability of coherence cache misses increases with the number of processors Save cache misses by Latch-free traversal during index search Latch-free traversal during index update 13 / 31

14 Latch-Free Index Search and Update Latch-free index search Condition = consistent node reads Consistency = no update between start and end of node read Latch-free index update Assumptions 1 Most node updates occur at the leaf level or near the leaf level 2 Number of leaf nodes > number of processors => probability of conflict = low Consequences 1 Latches on upper-level nodes are acquired too conservatively 2 Latches on leaf nodes are acquired too pessimistically 14 / 31

15 Main Idea of OLFIT 1 Traverse down the index optimistically without latching any nodes 2 Updaters acquire the latch of the leaf node to be updated 3 Latch acquisition proceeds upward if node split or deletion necessary Update operations on a node = serialized using a latch Read operations on a node = retried in case of inconsistency 15 / 31

16 Node Structure of B+-tree for OLFIT Two primitives : UpdateNode and ReadNode 16 / 31

17 Node Operations for OLFIT Algorithm UpdateNode U1. Acquire latch. U2. Update the content. U3. Increment version. U4. Release latch. Algorithm ReadNode R1. Copy the value of version into a register R. R2. Read the content of the node. R3. If latch is locked, go to R1. R4. If the current value of version is different from the copied value in R, go to R1. 17 / 31

18 Example of Concurrency Control 18 / 31

19 Example of Concurrency Control 19 / 31

20 Example of Concurrency Control 20 / 31

21 Example of Concurrency Control 21 / 31

22 Example of Concurrency Control 22 / 31

23 Tree Operations for OLFIT Dealing with node split Use high key and link pointer to the right neighbor Dealing with node deletion Remove links to node Register node to garbage collector Deallocate node when no operation reads the node 23 / 31

24 Experimental Evaluation Implementation of index CC schemes for B+-tree and CSB+-tree Lock coupling with node latches (LC) Tree-level locking with a tree latch (TL) Physical versioning with node latches (VN) Physical versioning with a tree latch (VT) OLFIT (OL) No concurrency control (NO) Experimental setting 8 CPUs, each with 8MB L2 cache, cache line of 64 bytes Workloads : 100% search, 100% insert, 50% insert + 50% delete + mixture of search, insert and delete Initial index : 10 million uniformly distributed 4-byte integers Size of index nodes : 128 bytes 24 / 31

25 Pure Search Performance for B+-tree OL, VN and VT - similar to NO TL - worse due to contention at the tree-latch LC - worst due to many coherence cache misses 25 / 31

26 Pure Update Performance for B+-tree and CSB+-tree OL - the only scalable one VN and VT - worse due to high cost of versioning VN and LC - slowly increase performance as number of threads increases VT and TL - worse due to contention at the tree-latch 26 / 31

27 Eight-Thread Performance with Varying Update Ratio OL, VN and VT - comparable for update ratio = 0 OL - better than other when update ratio increases 27 / 31

28 Conclusions and Future Work Conclusions The effect of latching in CC => coherence cache misses New optimistic index CC - OLFIT for B+-trees and CSB+-trees 1 No latching during index traversal 2 Latching for index update - only when necessary Performance comparison experiments Superior update and read scalability of OLFIT Future work Adaptation of OLFIT to other cache-conscious schemes, e.g. CR-tree Test OLFIT in real main memory database applications 28 / 31

29 Related Work Concurrency of Operations on B-Trees Logical and Physical Versioning in Main Memory Databases Presented paper Indexing Moving Objects using Short-Lived Throwaway Indexes Relation to own paper Concurrency control in main memory indexes Reduce latching to achieve greater performance - allow reading during updating 29 / 31

30 Critique Good aspects Relevant and various comparison experiments of five CC schemes : varying the number of threads on different workloads single thread and eight-thread varying the update ratio Good background Structured - easy to follow argument Could be improved More detailed proof that node splits are correctly handled (example) Generation of workloads is uniform - variation of insert/delete locality No related work section - included in the introduction instead Better formulation, e.g. parallel transact, we use the technique of using 30 / 31

31 Questions? 31 / 31

Advance Operating Systems (CS202) Locks Discussion

Advance Operating Systems (CS202) Locks Discussion Advance Operating Systems (CS202) Locks Discussion Threads Locks Spin Locks Array-based Locks MCS Locks Sequential Locks Road Map Threads Global variables and static objects are shared Stored in the static

More information

Hazard Pointers. Safe Resource Reclamation for Optimistic Concurrency

Hazard Pointers. Safe Resource Reclamation for Optimistic Concurrency Document Number: P0233R3 Date: 2017-02-06 Reply-to: maged.michael@acm.org, michael@codeplay.com Authors: Maged M. Michael, Michael Wong, Paul McKenney, Arthur O'Dwyer, David Hollman Project: Programming

More information

Deukyeon Hwang UNIST. Wook-Hee Kim UNIST. Beomseok Nam UNIST. Hanyang Univ.

Deukyeon Hwang UNIST. Wook-Hee Kim UNIST. Beomseok Nam UNIST. Hanyang Univ. Deukyeon Hwang UNIST Wook-Hee Kim UNIST Youjip Won Hanyang Univ. Beomseok Nam UNIST Fast but Asymmetric Access Latency Non-Volatility Byte-Addressability Large Capacity CPU Caches (Volatile) Persistent

More information

Foster B-Trees. Lucas Lersch. M. Sc. Caetano Sauer Advisor

Foster B-Trees. Lucas Lersch. M. Sc. Caetano Sauer Advisor Foster B-Trees Lucas Lersch M. Sc. Caetano Sauer Advisor 14.07.2014 Motivation Foster B-Trees Blink-Trees: multicore concurrency Write-Optimized B-Trees: flash memory large-writes wear leveling defragmentation

More information

CSCI 4717 Computer Architecture

CSCI 4717 Computer Architecture CSCI 4717/5717 Computer Architecture Topic: Symmetric Multiprocessors & Clusters Reading: Stallings, Sections 18.1 through 18.4 Classifications of Parallel Processing M. Flynn classified types of parallel

More information

A Practical Scalable Distributed B-Tree

A Practical Scalable Distributed B-Tree A Practical Scalable Distributed B-Tree CS 848 Paper Presentation Marcos K. Aguilera, Wojciech Golab, Mehul A. Shah PVLDB 08 March 8, 2010 Presenter: Evguenia (Elmi) Eflov Presentation Outline 1 Background

More information

Heckaton. SQL Server's Memory Optimized OLTP Engine

Heckaton. SQL Server's Memory Optimized OLTP Engine Heckaton SQL Server's Memory Optimized OLTP Engine Agenda Introduction to Hekaton Design Consideration High Level Architecture Storage and Indexing Query Processing Transaction Management Transaction Durability

More information

Cost of Concurrency in Hybrid Transactional Memory. Trevor Brown (University of Toronto) Srivatsan Ravi (Purdue University)

Cost of Concurrency in Hybrid Transactional Memory. Trevor Brown (University of Toronto) Srivatsan Ravi (Purdue University) Cost of Concurrency in Hybrid Transactional Memory Trevor Brown (University of Toronto) Srivatsan Ravi (Purdue University) 1 Transactional Memory: a history Hardware TM Software TM Hybrid TM 1993 1995-today

More information

Chapter 18 Parallel Processing

Chapter 18 Parallel Processing Chapter 18 Parallel Processing Multiple Processor Organization Single instruction, single data stream - SISD Single instruction, multiple data stream - SIMD Multiple instruction, single data stream - MISD

More information

Hazard Pointers. Safe Resource Reclamation for Optimistic Concurrency

Hazard Pointers. Safe Resource Reclamation for Optimistic Concurrency Document Number: P0233R1 Date: 2016 05 29 Reply to: maged.michael@acm.org, michael@codeplay.com Authors: Maged M. Michael, Michael Wong Project: Programming Language C++, SG14/SG1 Concurrency, LEWG Hazard

More information

AST: scalable synchronization Supervisors guide 2002

AST: scalable synchronization Supervisors guide 2002 AST: scalable synchronization Supervisors guide 00 tim.harris@cl.cam.ac.uk These are some notes about the topics that I intended the questions to draw on. Do let me know if you find the questions unclear

More information

Goldibear and the 3 Locks. Programming With Locks Is Tricky. More Lock Madness. And To Make It Worse. Transactional Memory: The Big Idea

Goldibear and the 3 Locks. Programming With Locks Is Tricky. More Lock Madness. And To Make It Worse. Transactional Memory: The Big Idea Programming With Locks s Tricky Multicore processors are the way of the foreseeable future thread-level parallelism anointed as parallelism model of choice Just one problem Writing lock-based multi-threaded

More information

Organisasi Sistem Komputer

Organisasi Sistem Komputer LOGO Organisasi Sistem Komputer OSK 14 Parallel Processing Pendidikan Teknik Elektronika FT UNY Multiple Processor Organization Single instruction, single data stream - SISD Single instruction, multiple

More information

Bw-Tree. Josef Schmeißer. January 9, Josef Schmeißer Bw-Tree January 9, / 25

Bw-Tree. Josef Schmeißer. January 9, Josef Schmeißer Bw-Tree January 9, / 25 Bw-Tree Josef Schmeißer January 9, 2018 Josef Schmeißer Bw-Tree January 9, 2018 1 / 25 Table of contents 1 Fundamentals 2 Tree Structure 3 Evaluation 4 Further Reading Josef Schmeißer Bw-Tree January 9,

More information

Speculative Synchronization: Applying Thread Level Speculation to Parallel Applications. University of Illinois

Speculative Synchronization: Applying Thread Level Speculation to Parallel Applications. University of Illinois Speculative Synchronization: Applying Thread Level Speculation to Parallel Applications José éf. Martínez * and Josep Torrellas University of Illinois ASPLOS 2002 * Now at Cornell University Overview Allow

More information

Introduction. New latch modes

Introduction. New latch modes A B link Tree method and latch protocol for synchronous node deletion in a high concurrency environment Karl Malbrain malbrain@cal.berkeley.edu Introduction A new B link Tree latching method and protocol

More information

CMSC Computer Architecture Lecture 15: Memory Consistency and Synchronization. Prof. Yanjing Li University of Chicago

CMSC Computer Architecture Lecture 15: Memory Consistency and Synchronization. Prof. Yanjing Li University of Chicago CMSC 22200 Computer Architecture Lecture 15: Memory Consistency and Synchronization Prof. Yanjing Li University of Chicago Administrative Stuff! Lab 5 (multi-core) " Basic requirements: out later today

More information

Synchronizing Data Structures

Synchronizing Data Structures Synchronizing Data Structures 1 / 56 Overview caches and atomics list-based set memory reclamation Adaptive Radix Tree B-tree Bw-tree split-ordered list hardware transactional memory 2 / 56 Caches Caches

More information

Computer Organization. Chapter 16

Computer Organization. Chapter 16 William Stallings Computer Organization and Architecture t Chapter 16 Parallel Processing Multiple Processor Organization Single instruction, single data stream - SISD Single instruction, multiple data

More information

Background: disk access vs. main memory access (1/2)

Background: disk access vs. main memory access (1/2) 4.4 B-trees Disk access vs. main memory access: background B-tree concept Node structure Structural properties Insertion operation Deletion operation Running time 66 Background: disk access vs. main memory

More information

416 Distributed Systems. Distributed File Systems 4 Jan 23, 2017

416 Distributed Systems. Distributed File Systems 4 Jan 23, 2017 416 Distributed Systems Distributed File Systems 4 Jan 23, 2017 1 Today's Lecture Wrap up NFS/AFS This lecture: other types of DFS Coda disconnected operation 2 Key Lessons Distributed filesystems almost

More information

Claude TADONKI. MINES ParisTech PSL Research University Centre de Recherche Informatique

Claude TADONKI. MINES ParisTech PSL Research University Centre de Recherche Informatique Got 2 seconds Sequential 84 seconds Expected 84/84 = 1 second!?! Got 25 seconds MINES ParisTech PSL Research University Centre de Recherche Informatique claude.tadonki@mines-paristech.fr Séminaire MATHEMATIQUES

More information

Chapter 12: Indexing and Hashing (Cnt(

Chapter 12: Indexing and Hashing (Cnt( Chapter 12: Indexing and Hashing (Cnt( Cnt.) Basic Concepts Ordered Indices B+-Tree Index Files B-Tree Index Files Static Hashing Dynamic Hashing Comparison of Ordered Indexing and Hashing Index Definition

More information

Multiprocessor Support

Multiprocessor Support CSC 256/456: Operating Systems Multiprocessor Support John Criswell University of Rochester 1 Outline Multiprocessor hardware Types of multi-processor workloads Operating system issues Where to run the

More information

Lock-Free and Practical Doubly Linked List-Based Deques using Single-Word Compare-And-Swap

Lock-Free and Practical Doubly Linked List-Based Deques using Single-Word Compare-And-Swap Lock-Free and Practical Doubly Linked List-Based Deques using Single-Word Compare-And-Swap Håkan Sundell Philippas Tsigas OPODIS 2004: The 8th International Conference on Principles of Distributed Systems

More information

Problem. Indexing with B-trees. Indexing. Primary Key Indexing. B-trees: Example. B-trees. primary key indexing

Problem. Indexing with B-trees. Indexing. Primary Key Indexing. B-trees: Example. B-trees. primary key indexing 15-82 Advanced Topics in Database Systems Performance Problem Given a large collection of records, Indexing with B-trees find similar/interesting things, i.e., allow fast, approximate queries 2 Indexing

More information

PERFORMANCE ANALYSIS AND OPTIMIZATION OF SKIP LISTS FOR MODERN MULTI-CORE ARCHITECTURES

PERFORMANCE ANALYSIS AND OPTIMIZATION OF SKIP LISTS FOR MODERN MULTI-CORE ARCHITECTURES PERFORMANCE ANALYSIS AND OPTIMIZATION OF SKIP LISTS FOR MODERN MULTI-CORE ARCHITECTURES Anish Athalye and Patrick Long Mentors: Austin Clements and Stephen Tu 3 rd annual MIT PRIMES Conference Sequential

More information

Realistic and Efficient Multi-Channel Communications in WSN

Realistic and Efficient Multi-Channel Communications in WSN Realistic and Efficient Multi-Channel Communications in WSN Miji Kim Andreas Schädeli Silvia Dorotheea Rus Cievoloth Gilber Coca Olmos Content Introduction Problem description Interference problems Time

More information

Data Processing on Modern Hardware

Data Processing on Modern Hardware Data Processing on Modern Hardware Jens Teubner, TU Dortmund, DBIS Group jens.teubner@cs.tu-dortmund.de Summer 2014 c Jens Teubner Data Processing on Modern Hardware Summer 2014 1 Part V Execution on Multiple

More information

Implementierungstechniken für Hauptspeicherdatenbanksysteme: The Bw-Tree

Implementierungstechniken für Hauptspeicherdatenbanksysteme: The Bw-Tree Implementierungstechniken für Hauptspeicherdatenbanksysteme: The Bw-Tree Josef Schmeißer January 9, 218 Abstract The Bw-Tree as presented by Levandoski et al. was designed to accommodate the emergence

More information

Lecture 19: Coherence and Synchronization. Topics: synchronization primitives (Sections )

Lecture 19: Coherence and Synchronization. Topics: synchronization primitives (Sections ) Lecture 19: Coherence and Synchronization Topics: synchronization primitives (Sections 5.4-5.5) 1 Caching Locks Spin lock: to acquire a lock, a process may enter an infinite loop that keeps attempting

More information

Per-Thread Batch Queues For Multithreaded Programs

Per-Thread Batch Queues For Multithreaded Programs Per-Thread Batch Queues For Multithreaded Programs Tri Nguyen, M.S. Robert Chun, Ph.D. Computer Science Department San Jose State University San Jose, California 95192 Abstract Sharing resources leads

More information

Multi-Processor / Parallel Processing

Multi-Processor / Parallel Processing Parallel Processing: Multi-Processor / Parallel Processing Originally, the computer has been viewed as a sequential machine. Most computer programming languages require the programmer to specify algorithms

More information

Designing Next-Generation Data- Centers with Advanced Communication Protocols and Systems Services. Presented by: Jitong Chen

Designing Next-Generation Data- Centers with Advanced Communication Protocols and Systems Services. Presented by: Jitong Chen Designing Next-Generation Data- Centers with Advanced Communication Protocols and Systems Services Presented by: Jitong Chen Outline Architecture of Web-based Data Center Three-Stage framework to benefit

More information

Blocking Analysis of FIFO, Unordered, and Priority-Ordered Spin Locks

Blocking Analysis of FIFO, Unordered, and Priority-Ordered Spin Locks On Spin Locks in AUTOSAR: Blocking Analysis of FIFO, Unordered, and Priority-Ordered Spin Locks Alexander Wieder and Björn Brandenburg MPI-SWS RTSS 2013 12/04/2013 Vancouver, Canada Motivation: AUTOSAR:

More information

Abstraction, Reality Checks, and RCU

Abstraction, Reality Checks, and RCU Abstraction, Reality Checks, and RCU Paul E. McKenney IBM Beaverton University of Toronto Cider Seminar July 26, 2005 Copyright 2005 IBM Corporation 1 Overview Moore's Law and SMP Software Non-Blocking

More information

Database System Concepts, 6 th Ed. Silberschatz, Korth and Sudarshan See for conditions on re-use

Database System Concepts, 6 th Ed. Silberschatz, Korth and Sudarshan See  for conditions on re-use Chapter 11: Indexing and Hashing Database System Concepts, 6 th Ed. See www.db-book.com for conditions on re-use Chapter 12: Indexing and Hashing Basic Concepts Ordered Indices B + -Tree Index Files Static

More information

Go Deep: Fixing Architectural Overheads of the Go Scheduler

Go Deep: Fixing Architectural Overheads of the Go Scheduler Go Deep: Fixing Architectural Overheads of the Go Scheduler Craig Hesling hesling@cmu.edu Sannan Tariq stariq@cs.cmu.edu May 11, 2018 1 Introduction Golang is a programming language developed to target

More information

DATA STRUCTURE AND ALGORITHM USING PYTHON

DATA STRUCTURE AND ALGORITHM USING PYTHON DATA STRUCTURE AND ALGORITHM USING PYTHON Advanced Data Structure and File Manipulation Peter Lo Linear Structure Queue, Stack, Linked List and Tree 2 Queue A queue is a line of people or things waiting

More information

Lecture Notes on Advanced Garbage Collection

Lecture Notes on Advanced Garbage Collection Lecture Notes on Advanced Garbage Collection 15-411: Compiler Design André Platzer Lecture 21 November 4, 2010 1 Introduction More information on garbage collection can be found in [App98, Ch 13.5-13.7]

More information

CSL373: Lecture 5 Deadlocks (no process runnable) + Scheduling (> 1 process runnable)

CSL373: Lecture 5 Deadlocks (no process runnable) + Scheduling (> 1 process runnable) CSL373: Lecture 5 Deadlocks (no process runnable) + Scheduling (> 1 process runnable) Past & Present Have looked at two constraints: Mutual exclusion constraint between two events is a requirement that

More information

Lecture: Coherence and Synchronization. Topics: synchronization primitives, consistency models intro (Sections )

Lecture: Coherence and Synchronization. Topics: synchronization primitives, consistency models intro (Sections ) Lecture: Coherence and Synchronization Topics: synchronization primitives, consistency models intro (Sections 5.4-5.5) 1 Performance Improvements What determines performance on a multiprocessor: What fraction

More information

Multiprocessor Cache Coherency. What is Cache Coherence?

Multiprocessor Cache Coherency. What is Cache Coherence? Multiprocessor Cache Coherency CS448 1 What is Cache Coherence? Two processors can have two different values for the same memory location 2 1 Terminology Coherence Defines what values can be returned by

More information

The dark powers on Intel processor boards

The dark powers on Intel processor boards The dark powers on Intel processor boards Processing Resources (3U VPX) Boards with Multicore CPUs: Up to 16 cores using Intel Xeon D-1577 on TR C4x/msd Boards with 4-Core CPUs and Multiple Graphical Execution

More information

GLocks: Efficient Support for Highly- Contended Locks in Many-Core CMPs

GLocks: Efficient Support for Highly- Contended Locks in Many-Core CMPs GLocks: Efficient Support for Highly- Contended Locks in Many-Core CMPs Authors: Jos e L. Abell an, Juan Fern andez and Manuel E. Acacio Presenter: Guoliang Liu Outline Introduction Motivation Background

More information

Summary: Open Questions:

Summary: Open Questions: Summary: The paper proposes an new parallelization technique, which provides dynamic runtime parallelization of loops from binary single-thread programs with minimal architectural change. The realization

More information

Parallel Processing. Computer Architecture. Computer Architecture. Outline. Multiple Processor Organization

Parallel Processing. Computer Architecture. Computer Architecture. Outline. Multiple Processor Organization Computer Architecture Computer Architecture Prof. Dr. Nizamettin AYDIN naydin@yildiz.edu.tr nizamettinaydin@gmail.com Parallel Processing http://www.yildiz.edu.tr/~naydin 1 2 Outline Multiple Processor

More information

CLOUD-SCALE FILE SYSTEMS

CLOUD-SCALE FILE SYSTEMS Data Management in the Cloud CLOUD-SCALE FILE SYSTEMS 92 Google File System (GFS) Designing a file system for the Cloud design assumptions design choices Architecture GFS Master GFS Chunkservers GFS Clients

More information

PrimeBase XT. A transactional engine for MySQL. Paul McCullagh SNAP Innovation GmbH

PrimeBase XT. A transactional engine for MySQL.  Paul McCullagh SNAP Innovation GmbH PrimeBase XT A transactional engine for MySQL Paul McCullagh SNAP Innovation GmbH Our Company SNAP Innovation GmbH was founded in 1996, currently 25 employees. Purpose: develop and support PrimeBase database,

More information

Array-based Cache Conscious Trees

Array-based Cache Conscious Trees Regular Paper Array-based Cache Conscious Trees Hidehisa Takamizawa,, Kazuyuki Nakajima, and Masayoshi Aritsugi Making effective use of cache can give good performance. In this paper, Array-Based Cache

More information

The Adaptive Radix Tree

The Adaptive Radix Tree Department of Informatics, University of Zürich MSc Basismodul The Adaptive Radix Tree Rafael Kallis Matrikelnummer: -708-887 Email: rk@rafaelkallis.com September 8, 08 supervised by Prof. Dr. Michael

More information

Transactional Memory: Architectural Support for Lock-Free Data Structures Maurice Herlihy and J. Eliot B. Moss ISCA 93

Transactional Memory: Architectural Support for Lock-Free Data Structures Maurice Herlihy and J. Eliot B. Moss ISCA 93 Transactional Memory: Architectural Support for Lock-Free Data Structures Maurice Herlihy and J. Eliot B. Moss ISCA 93 What are lock-free data structures A shared data structure is lock-free if its operations

More information

Portland State University ECE 588/688. Directory-Based Cache Coherence Protocols

Portland State University ECE 588/688. Directory-Based Cache Coherence Protocols Portland State University ECE 588/688 Directory-Based Cache Coherence Protocols Copyright by Alaa Alameldeen and Haitham Akkary 2018 Why Directory Protocols? Snooping-based protocols may not scale All

More information

MULTIPROCESSORS. Characteristics of Multiprocessors. Interconnection Structures. Interprocessor Arbitration

MULTIPROCESSORS. Characteristics of Multiprocessors. Interconnection Structures. Interprocessor Arbitration MULTIPROCESSORS Characteristics of Multiprocessors Interconnection Structures Interprocessor Arbitration Interprocessor Communication and Synchronization Cache Coherence 2 Characteristics of Multiprocessors

More information

Scalable Concurrent Hash Tables via Relativistic Programming

Scalable Concurrent Hash Tables via Relativistic Programming Scalable Concurrent Hash Tables via Relativistic Programming Josh Triplett September 24, 2009 Speed of data < Speed of light Speed of light: 3e8 meters/second Processor speed: 3 GHz, 3e9 cycles/second

More information

CST-Trees: Cache Sensitive T-Trees

CST-Trees: Cache Sensitive T-Trees CST-Trees: Cache Sensitive T-Trees Ig-hoon Lee 1, Junho Shim 2, Sang-goo Lee 3, and Jonghoon Chun 4 1 Prompt Corp., Seoul, Korea ihlee@prompt.co.kr 2 Department of Computer Science, Sookmyung Women s University,

More information

Chapter 6 Concurrency: Deadlock and Starvation

Chapter 6 Concurrency: Deadlock and Starvation Operating Systems: Internals and Design Principles Chapter 6 Concurrency: Deadlock and Starvation Seventh Edition By William Stallings Operating Systems: Internals and Design Principles When two trains

More information

BzTree: A High-Performance Latch-free Range Index for Non-Volatile Memory

BzTree: A High-Performance Latch-free Range Index for Non-Volatile Memory BzTree: A High-Performance Latch-free Range Index for Non-Volatile Memory JOY ARULRAJ JUSTIN LEVANDOSKI UMAR FAROOQ MINHAS PER-AKE LARSON Microsoft Research NON-VOLATILE MEMORY [NVM] PERFORMANCE DRAM VOLATILE

More information

Lecture 8: Directory-Based Cache Coherence. Topics: scalable multiprocessor organizations, directory protocol design issues

Lecture 8: Directory-Based Cache Coherence. Topics: scalable multiprocessor organizations, directory protocol design issues Lecture 8: Directory-Based Cache Coherence Topics: scalable multiprocessor organizations, directory protocol design issues 1 Scalable Multiprocessors P1 P2 Pn C1 C2 Cn 1 CA1 2 CA2 n CAn Scalable interconnection

More information

Chapter 11: Indexing and Hashing

Chapter 11: Indexing and Hashing Chapter 11: Indexing and Hashing Basic Concepts Ordered Indices B + -Tree Index Files B-Tree Index Files Static Hashing Dynamic Hashing Comparison of Ordered Indexing and Hashing Index Definition in SQL

More information

Concurrency, Thread. Dongkun Shin, SKKU

Concurrency, Thread. Dongkun Shin, SKKU Concurrency, Thread 1 Thread Classic view a single point of execution within a program a single PC where instructions are being fetched from and executed), Multi-threaded program Has more than one point

More information

Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution

Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution Ravi Rajwar and Jim Goodman University of Wisconsin-Madison International Symposium on Microarchitecture, Dec. 2001 Funding

More information

Lecture 12 Transactional Memory

Lecture 12 Transactional Memory CSCI-UA.0480-010 Special Topics: Multicore Programming Lecture 12 Transactional Memory Christopher Mitchell, Ph.D. cmitchell@cs.nyu.edu http://z80.me Database Background Databases have successfully exploited

More information

Trees. Reading: Weiss, Chapter 4. Cpt S 223, Fall 2007 Copyright: Washington State University

Trees. Reading: Weiss, Chapter 4. Cpt S 223, Fall 2007 Copyright: Washington State University Trees Reading: Weiss, Chapter 4 1 Generic Rooted Trees 2 Terms Node, Edge Internal node Root Leaf Child Sibling Descendant Ancestor 3 Tree Representations n-ary trees Each internal node can have at most

More information

Low Overhead Concurrency Control for Partitioned Main Memory Databases. Evan P. C. Jones Daniel J. Abadi Samuel Madden"

Low Overhead Concurrency Control for Partitioned Main Memory Databases. Evan P. C. Jones Daniel J. Abadi Samuel Madden Low Overhead Concurrency Control for Partitioned Main Memory Databases Evan P. C. Jones Daniel J. Abadi Samuel Madden" Banks" Payment Processing" Airline Reservations" E-Commerce" Web 2.0" Problem:" Millions

More information

Parallel access to linked data structures

Parallel access to linked data structures Parallel access to linked data structures [Solihin Ch. 5] Answer the questions below. Name some linked data structures. What operations can be performed on all of these structures? Why is it hard to parallelize

More information

Memory Consistency and Multiprocessor Performance

Memory Consistency and Multiprocessor Performance Memory Consistency Model Memory Consistency and Multiprocessor Performance Define memory correctness for parallel execution Execution appears to the that of some correct execution of some theoretical parallel

More information

Optimizing Replication, Communication, and Capacity Allocation in CMPs

Optimizing Replication, Communication, and Capacity Allocation in CMPs Optimizing Replication, Communication, and Capacity Allocation in CMPs Zeshan Chishti, Michael D Powell, and T. N. Vijaykumar School of ECE Purdue University Motivation CMP becoming increasingly important

More information

Fall 2015 COMP Operating Systems. Lab #8

Fall 2015 COMP Operating Systems. Lab #8 Fall 2015 COMP 3511 Operating Systems Lab #8 1 Outline Thrashing Working-Set model File system File system implementation 2 Q. 1 Please state the disadvantages and advantages with the following page replacement

More information

!! What is virtual memory and when is it useful? !! What is demand paging? !! When should pages in memory be replaced?

!! What is virtual memory and when is it useful? !! What is demand paging? !! When should pages in memory be replaced? Chapter 10: Virtual Memory Questions? CSCI [4 6] 730 Operating Systems Virtual Memory!! What is virtual memory and when is it useful?!! What is demand paging?!! When should pages in memory be replaced?!!

More information

CA485 Ray Walshe Google File System

CA485 Ray Walshe Google File System Google File System Overview Google File System is scalable, distributed file system on inexpensive commodity hardware that provides: Fault Tolerance File system runs on hundreds or thousands of storage

More information

Deadlock. Concurrency: Deadlock and Starvation. Reusable Resources

Deadlock. Concurrency: Deadlock and Starvation. Reusable Resources Concurrency: Deadlock and Starvation Chapter 6 Deadlock Permanent blocking of a set of processes that either compete for system resources or communicate with each other No efficient solution Involve conflicting

More information

Index. ADEPT (tool for modelling proposed systerns),

Index. ADEPT (tool for modelling proposed systerns), Index A, see Arrivals Abstraction in modelling, 20-22, 217 Accumulated time in system ( w), 42 Accuracy of models, 14, 16, see also Separable models, robustness Active customer (memory constrained system),

More information

TrafficDB: HERE s High Performance Shared-Memory Data Store Ricardo Fernandes, Piotr Zaczkowski, Bernd Göttler, Conor Ettinoffe, and Anis Moussa

TrafficDB: HERE s High Performance Shared-Memory Data Store Ricardo Fernandes, Piotr Zaczkowski, Bernd Göttler, Conor Ettinoffe, and Anis Moussa TrafficDB: HERE s High Performance Shared-Memory Data Store Ricardo Fernandes, Piotr Zaczkowski, Bernd Göttler, Conor Ettinoffe, and Anis Moussa EPL646: Advanced Topics in Databases Christos Hadjistyllis

More information

CS4021/4521 INTRODUCTION

CS4021/4521 INTRODUCTION CS4021/4521 Advanced Computer Architecture II Prof Jeremy Jones Rm 4.16 top floor South Leinster St (SLS) jones@scss.tcd.ie South Leinster St CS4021/4521 2018 jones@scss.tcd.ie School of Computer Science

More information

Lecture: Consistency Models, TM

Lecture: Consistency Models, TM Lecture: Consistency Models, TM Topics: consistency models, TM intro (Section 5.6) No class on Monday (please watch TM videos) Wednesday: TM wrap-up, interconnection networks 1 Coherence Vs. Consistency

More information

A Concurrent Skip List Implementation with RTM and HLE

A Concurrent Skip List Implementation with RTM and HLE A Concurrent Skip List Implementation with RTM and HLE Fan Gao May 14, 2014 1 Background Semester Performed: Spring, 2014 Instructor: Maurice Herlihy The main idea of my project is to implement a skip

More information

High Performance Transactions in Deuteronomy

High Performance Transactions in Deuteronomy High Performance Transactions in Deuteronomy Justin Levandoski, David Lomet, Sudipta Sengupta, Ryan Stutsman, and Rui Wang Microsoft Research Overview Deuteronomy: componentized DB stack Separates transaction,

More information

(Preliminary Version 2 ) Jai-Hoon Kim Nitin H. Vaidya. Department of Computer Science. Texas A&M University. College Station, TX

(Preliminary Version 2 ) Jai-Hoon Kim Nitin H. Vaidya. Department of Computer Science. Texas A&M University. College Station, TX Towards an Adaptive Distributed Shared Memory (Preliminary Version ) Jai-Hoon Kim Nitin H. Vaidya Department of Computer Science Texas A&M University College Station, TX 77843-3 E-mail: fjhkim,vaidyag@cs.tamu.edu

More information

15 418/618 Project Final Report Concurrent Lock free BST

15 418/618 Project Final Report Concurrent Lock free BST 15 418/618 Project Final Report Concurrent Lock free BST Names: Swapnil Pimpale, Romit Kudtarkar AndrewID: spimpale, rkudtark 1.0 SUMMARY We implemented two concurrent binary search trees (BSTs): a fine

More information

Memory Consistency and Multiprocessor Performance. Adapted from UCB CS252 S01, Copyright 2001 USB

Memory Consistency and Multiprocessor Performance. Adapted from UCB CS252 S01, Copyright 2001 USB Memory Consistency and Multiprocessor Performance Adapted from UCB CS252 S01, Copyright 2001 USB 1 Memory Consistency Model Define memory correctness for parallel execution Execution appears to the that

More information

Concurrency Control. Chapter 17. Database Management Systems 3ed, R. Ramakrishnan and J. Gehrke 1

Concurrency Control. Chapter 17. Database Management Systems 3ed, R. Ramakrishnan and J. Gehrke 1 Concurrency Control Chapter 17 Database Management Systems 3ed, R. Ramakrishnan and J. Gehrke 1 Conflict Schedules Two actions conflict if they operate on the same data object and at least one of them

More information

The Google File System

The Google File System The Google File System By Ghemawat, Gobioff and Leung Outline Overview Assumption Design of GFS System Interactions Master Operations Fault Tolerance Measurements Overview GFS: Scalable distributed file

More information

Eunomia: Scaling Concurrent Search Trees under Contention Using HTM

Eunomia: Scaling Concurrent Search Trees under Contention Using HTM Eunomia: Scaling Concurrent Search Trees under Contention Using HTM Xin Wang*, Weihua Zhang*, Zhaoguo Wang, Ziyun Wei*, Haibo Chen, Wenyun Zhao * Software School, Fudan University Shanghai Key Laboratory

More information

Concurrency: Principles of Deadlock. Processes and resources. Concurrency and deadlocks. Operating Systems Fall Processes need resources to run

Concurrency: Principles of Deadlock. Processes and resources. Concurrency and deadlocks. Operating Systems Fall Processes need resources to run Concurrency: Principles of Deadlock Operating Systems Fall 2002 Processes and resources Processes need resources to run CPU, memory, disk, etc process waiting for a resource cannot complete its execution

More information

CS140 Operating Systems and Systems Programming Midterm Exam

CS140 Operating Systems and Systems Programming Midterm Exam CS140 Operating Systems and Systems Programming Midterm Exam October 31 st, 2003 (Total time = 50 minutes, Total Points = 50) Name: (please print) In recognition of and in the spirit of the Stanford University

More information

Chapter 18. Parallel Processing. Yonsei University

Chapter 18. Parallel Processing. Yonsei University Chapter 18 Parallel Processing Contents Multiple Processor Organizations Symmetric Multiprocessors Cache Coherence and the MESI Protocol Clusters Nonuniform Memory Access Vector Computation 18-2 Types

More information

Caches. Cache Memory. memory hierarchy. CPU memory request presented to first-level cache first

Caches. Cache Memory. memory hierarchy. CPU memory request presented to first-level cache first Cache Memory memory hierarchy CPU memory request presented to first-level cache first if data NOT in cache, request sent to next level in hierarchy and so on CS3021/3421 2017 jones@tcd.ie School of Computer

More information

Lecture 21: Transactional Memory. Topics: Hardware TM basics, different implementations

Lecture 21: Transactional Memory. Topics: Hardware TM basics, different implementations Lecture 21: Transactional Memory Topics: Hardware TM basics, different implementations 1 Transactions New paradigm to simplify programming instead of lock-unlock, use transaction begin-end locks are blocking,

More information

Transactional Interference-less Balanced Tree

Transactional Interference-less Balanced Tree Transactional Interference-less Balanced Tree Technical Report Ahmed Hassan, Roberto Palmieri, and Binoy Ravindran Virginia Tech, Blacksburg, VA, USA. Abstract. In this paper, we present TxCF-Tree, a balanced

More information

Lecture: Consistency Models, TM. Topics: consistency models, TM intro (Section 5.6)

Lecture: Consistency Models, TM. Topics: consistency models, TM intro (Section 5.6) Lecture: Consistency Models, TM Topics: consistency models, TM intro (Section 5.6) 1 Coherence Vs. Consistency Recall that coherence guarantees (i) that a write will eventually be seen by other processors,

More information

Physical Level of Databases: B+-Trees

Physical Level of Databases: B+-Trees Physical Level of Databases: B+-Trees Adnan YAZICI Computer Engineering Department METU (Fall 2005) 1 B + -Tree Index Files l Disadvantage of indexed-sequential files: performance degrades as file grows,

More information

) Intel)(TX)memory):) Transac'onal) Synchroniza'on) Extensions)(TSX))) Transac'ons)

) Intel)(TX)memory):) Transac'onal) Synchroniza'on) Extensions)(TSX))) Transac'ons) ) Intel)(TX)memory):) Transac'onal) Synchroniza'on) Extensions)(TSX))) Transac'ons) Transactions - Definition A transaction is a sequence of data operations with the following properties: * A Atomic All

More information

CS3600 SYSTEMS AND NETWORKS

CS3600 SYSTEMS AND NETWORKS CS3600 SYSTEMS AND NETWORKS SPRING 2013 Lecture 13: Paging Prof. Alan Mislove (amislove@ccs.neu.edu) Paging Physical address space of a process can be noncontiguous; process is allocated physical memory

More information

Review: Creating a Parallel Program. Programming for Performance

Review: Creating a Parallel Program. Programming for Performance Review: Creating a Parallel Program Can be done by programmer, compiler, run-time system or OS Steps for creating parallel program Decomposition Assignment of tasks to processes Orchestration Mapping (C)

More information

Shared Cache Aware Task Mapping for WCRT Minimization

Shared Cache Aware Task Mapping for WCRT Minimization Shared Cache Aware Task Mapping for WCRT Minimization Huping Ding & Tulika Mitra School of Computing, National University of Singapore Yun Liang Center for Energy-efficient Computing and Applications,

More information

Chapter 11: Indexing and Hashing

Chapter 11: Indexing and Hashing Chapter 11: Indexing and Hashing Database System Concepts, 6 th Ed. See www.db-book.com for conditions on re-use Chapter 11: Indexing and Hashing Basic Concepts Ordered Indices B + -Tree Index Files B-Tree

More information

Shared Memory and Distributed Multiprocessing. Bhanu Kapoor, Ph.D. The Saylor Foundation

Shared Memory and Distributed Multiprocessing. Bhanu Kapoor, Ph.D. The Saylor Foundation Shared Memory and Distributed Multiprocessing Bhanu Kapoor, Ph.D. The Saylor Foundation 1 Issue with Parallelism Parallel software is the problem Need to get significant performance improvement Otherwise,

More information

Outline. Database Tuning. Ideal Transaction. Concurrency Tuning Goals. Concurrency Tuning. Nikolaus Augsten. Lock Tuning. Unit 8 WS 2013/2014

Outline. Database Tuning. Ideal Transaction. Concurrency Tuning Goals. Concurrency Tuning. Nikolaus Augsten. Lock Tuning. Unit 8 WS 2013/2014 Outline Database Tuning Nikolaus Augsten University of Salzburg Department of Computer Science Database Group 1 Unit 8 WS 2013/2014 Adapted from Database Tuning by Dennis Shasha and Philippe Bonnet. Nikolaus

More information

Chapter 11: Indexing and Hashing

Chapter 11: Indexing and Hashing Chapter 11: Indexing and Hashing Database System Concepts, 6 th Ed. See www.db-book.com for conditions on re-use Chapter 11: Indexing and Hashing Basic Concepts Ordered Indices B + -Tree Index Files B-Tree

More information