Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions

Transcription

1 Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions Zhaohui Fu Sharad Malik Department of Electrical Engineering Princeton University Princeton, NJ 08544, USA Abstract Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific constraints in Conjunctive Normal Form (CNF), which is accepted as input by most efficient contemporary SAT solvers [1 3]. However, such translation may have information loss. For example, when a circuit is encoded into CNF, structural information such as gate orientation, logic paths, signal observability, etc. is lost. However, recent research [4 6] shows that a substantial amount of the lost information can be restored in circuit form. This paper presents an efficient algorithm (CNF2CKT) for extracting circuit information from CNF instances. CNF2CKT is optimal in the sense that it extracts a maximum acyclic combinational circuit from any given CNF using the logic gates pre-specified in a library. The extracted circuit structure is valuable in various ways, particularly when the CNF is not encoded from the circuit, or the circuit description is not readily available. As an example, we show that the extracted circuit structure can be used to derive Circuit Observability Don t Cares [7] for speeding up CNF-SAT [8]. I. INTRODUCTION One of the major contributing factors to the recent successes in Boolean Satisfiability (SAT) research is the simple representation of the problem in the Conjunctive Normal Form (CNF). In the CNF description, a formula is expressed as a conjunction of clauses, each of which is a disjunction of literals. A literal is the occurrence of a variable in true or complemented form. For example, the formula (x+y )(x +y) is the CNF representation for the equality function for x and y (x y) with 2 clauses, each of which has 2 literals. The CNF representation of a SAT problem provides a data structure for efficient implementation of various techniques used in most contemporary SAT solvers [1 3]. Various verification or optimization problems can be easily encoded in CNF [9]. The simplicity of CNF comes with a tradeoff. Usually the domain specific representation contains more information than its encoded CNF counterpart. One such example is various verification tasks, such as equivalence and property checking, that arise from logic circuits. The encoded CNF does not have the explicit circuit structure, which could be very helpful in many situations like the applications of various Circuit-SAT [10] techniques and the use of Observability Don t Cares (ODC) [7] in CNF-SAT [8]. A. Motivation The entire effort of extracting circuit structure from CNF may seem redundant. Why not just retain the circuit from which this CNF was generated? Indeed, wherever possible that should be preferred course of action. However, this extraction is useful in the following scenarios: This research is supported by Award FA A from the Air Force Research Laboratory. Z. Fu is on leave from the Department of Computer Science, National University of Singapore, Singapore ) The CNF is not encoded from a circuit description. All SAT instances generated in Artificial Intelligence (AI), e.g. planning and scheduling, belong to this category. Some Electronic Design Automation (EDA) problems, like FPGA routing, are not encoded from a circuit, either. 2) The CNF is encoded from a circuit, which may not be available. Almost all the CNF benchmarks currently available online belong to this category. B. Previous Work It was generally thought that the information loss during encoding from circuit to CNF is unavoidable. Li first proposed an equivalence reasoning technique called EqSatz [4] that dynamically detects equivalent literals (gates) in the SAT instance. Ostrowski constructs an implicit graph of clauses [5] to recover AND and OR gates from the SAT instance in addition to the equivalence gates. Roy et al. use the CNF signature [6] to detect (N)AND, (N)OR, X(N)OR and MAJ3 gates from the CNF instance. However, all these previous attempts have several limitations. First, the gate detection mechanisms are all hard coded for each logic gate to be detected (which only include (N)AND, (N)OR, X(N)OR and MAJ3 gates). This leads to efficient implementation due to highly specialized pattern matching. However, it is also limiting as the hard coded pattern matcher cannot be easily generalized to recognize arbitrary gates that may have been present in a gate library used to generate such a CNF. Roy et al. propose a more general pattern matching approach based on sub-graph isomorphism, but the paper does not mention any implementation or experimentation. Second, the processes of detecting individual gates and reconstructing an acyclic circuit are inter-mixed, with no guarantee on the maximum size of the restored circuit structure. Third, their experiments show very interesting results, but some attributes, e.g. the size of the connected component in the restored circuit, are missing, thus one cannot deduce the exact efficacy of their approaches. Despite some limitations, these attempts, particularly by Roy et al. [6], demonstrate promising results in CNF-to-circuit decoding. C. Our Contribution There have long been two problem representation based directions in SAT research, circuit-sat [10] and CNF-SAT. Typically most circuit-sat techniques are not applicable in CNF-SAT. We present a tool CNF2CKT that bridges the gap between circuit-sat and CNF- SAT. The CNF2CKT algorithm efficiently extracts a maximum circuit structure from any given CNF instance. Some important features of CNF2CKT are: 1) It uses generic pattern matching techniques to detect all possible gate matchings (candidate matchings) for every logic gate in a user-specified gate library.

2 2) It then constructs a maximum acyclic combinational circuit by selecting a maximum subset of gate matchings, i.e. a cover, from all the candidate matchings. Maximum here is with respect to the number of logic gates in the extracted circuit, i.e. the size of the cover, since one matching corresponds to one logic gate in the extracted circuit. The cover is maximum in the sense that no other circuit structure containing more logic gates can be extracted from the CNF description. We also provide a specific application on how the extracted circuit structure could help in detecting and propagating Circuit Observability Don t Care information [7] in CNF-SAT [8]. This is useful for speeding up SAT even when the original CNF was derived from non-circuit applications. II. PATTERN MATCHING WITH CNF SIGNATURES The encoding of a logic circuit into CNF is of complexity O(n) [9], where n is the size of the circuit in the number of gates. The algorithm is a straightforward traversal of the circuit and for each logic gate, generating the corresponding set of clauses consistent with the logic function of that gate. This unique set of clauses is called a CNF signature [6] for that gate. There is a matching of a set of clauses from the CNF description to a gate, when each of these matches a clause in the CNF signature of that particular gate. For example, the CNF description...(x + z )(y + z )(x + y + z)... has a matching for an AND gate, whose CNF signature is (a + c )(b + c )(a + b + c) with x a,y b and z c. Note that the sign of the literals in the matched clauses must match as well. Instead of using a generic graph matcher (e.g. VFLib [11] as suggested by Roy et al.), we implement our own pattern matcher that takes advantage of the following facts. First, a valid candidate matching must have the same number of literals in all the matched clauses. This observation is useful in the early pruning of the search space. Second, we exploit various early termination strategies. For example, since we are only interested in finding a (not all) maximum matching, we treat the inputs of a logic gate as an unordered set. In other words, once a matching is found involving a set of inputs, we do not need to search any other matching involving the same set of inputs unless the output signal for that matching has changed. For a generic graph matcher each different order of inputs is a different graph matching. For example, a 10-input AND gate means 10! matchings in VFLib versus only 1 in CNF2CKT. Our pattern matcher explicitly utilizes these special property constraints and is sketched in Algorithm 1. Let V (CNF) be the set of all variables and C(CNF) be the set of all clauses in the given CNF. Then v V(CNF) is one Boolean variable and c C(CNF) is one clause. Since each CNF clause contains one or more literals, i.e. variable with positive/negative phase, we let l c to be a literal and c the total number of literals in clause c. var(l) = v gives the corresponding variable v of literal l. A key clause of a CNF signature is a clause that contains most variables (i.e. longest) associated with that gate. While we recognize that multiple output logic gates may be present in a library, we only consider single output gates in this paper. Multiple output gates are likely to be treated as separate gates with respect to each output signal during CNF encoding, as this results in a more compact CNF description. Note that the output variable must appear in every clause in the CNF signature. We use V(g) to denote the set of variables associated with gate g in the library. We use the key clause from the CNF signature of a given logic gate as a pivot to be compared against all the clauses in the CNF description. This is due to the observation that most logic gates in gate libraries have one key clause that contains all the input variables. Since every clause also contains the output variable, the key clause contains all variables associated with that logic gate. For example, the CNF signature of a 5-input AND gate contains the key clause (a + b +c +d +e + f ), where every variable except f (output variable) is an input variable. This observation is valid for other logic gates as well, such as (N)AND, (N)OR, INV, BUF and X(N)OR. Once we match the key clause from a CNF signature to a target clause in the CNF description, the remaining procedure is straightforward: First, both the number of positive and negative literals in the key clause and the matched target clause must be equal respectively. Second, we let the output variable be matched to any variable in the key clause with the same phase, i.e. positive or negative. Finally, with the output variable fixed in the key clause, the remaining variables must all be input variables. All possible permutations of the input variable matchings are generated one by one. For each permutation, we check if there are corresponding clauses in the CNF description that match those remaining unmatched clauses in the CNF signature. This check can be done very efficiently as each variable maintains a set of all clause indices it appears in according to its phase and the only operations involved are a series of set intersections. Though all permutations need to be searched in general, the first matched permutation terminates the entire search as subsequent matchings involving the same set of inputs are no longer necessary. Algorithm 1 Find All Candidate Matchings 1: for all gate g LIB do 2: c g := key clause in CNF signature of g 3: v gout := output variable of g 4: for all clause c C(CNF) do 5: if c g = c then 6: for all l c do 7: for all permutation p of V(g) \ {v gout } do 8: if c = V(g) and a matching m of g exists with c \ {var(l)} p and var(l) v gout then 9: Record m and continue from line :4 10: else if c < V(g) and multiple partial matchings of g exist with var(l) v gout then 11: for all Partial matching m do 12: if we can complete m with set of variables δ s.t. δ c \ {var(l)} p then 13: Record m 14: end if 15: end for 16: Continue from line 7 17: end if 18: end for 19: end for 20: end if 21: end for 22: end for The use of the key clause not only eases our pattern matching, it also plays an important role in the pruning of repeated matchings. Since the key clause in the CNF signature can be uniquely chosen in most cases, each candidate matching is discovered exactly once. Without this pruning, a candidate gate with an n clause CNF signature could be discovered as many as n times. It is worth mentioning that there are cases where the CNF signature of a gate does not have a key clause containing all input variables. Consider the gate that implements the logic function d = ab+bc. The CNF signature is (a +b +d)(b +c +d)(b+d )(a+c+d ) and none

3 of the four clauses contains all 4 variables a,b,c and d. CNF2CKT is still able to find all matchings for such a logic gate in the library despite the lack of the clause containing all variables, as illustrated in line 10 in Algorithm 1. In this case, CNF2CKT uses a structure hashing to prune the repeated matchings explicitly by recording the normalized (e.g. alphabetically sorted) successful matchings in the hash table. However, the introduction of the structure hashing causes a considerable amount of overhead in the entire algorithm in this case. Note that Algorithm 1 completely finds all possible gate matchings, which is important since we are going to construct a maximum acyclic combinational circuit using these matchings. III. CONSTRUCTING THE CIRCUIT USING MATCHINGS Using all detected gate matchings as building blocks, we need to construct a maximum acyclic combinational circuit from the given CNF. We focus on acyclic combinational circuits because in most cases an acyclic combinational circuit is used in the verification tasks. Let all possible gate matchings be denoted by M. Each individual matching m M matches logic gate g(m) from the library with set of inputs I(m), output variable out(m) to a set of matched clauses C(m) C(CNF). Recall that all gates in the library are single output. A clause c C(CNF) could be involved in a set of matchings S(c). Our objective is to select a maximum cover M c M such that the set of gates {g(m) : m M c } form an acyclic combinational circuit. With this notation, we present our constraints: 1) v V (CNF) if v = out(m i ) and v = out(m j ) for m i,m j M c, then m i = m j. In other words, every signal in the circuit can be the output of at most one gate in the cover. 2) c C(CNF) if c C(m i ) and c C(m j ) for m i,m j M c, then m i = m j. In other words, each clause can be involved in only one matching in the cover. 3) c C(CNF) if S(c) /0, then m S(c) such that m M c. In other words, every matched clause must be involved in at least one matching in the cover. 4) The logic circuit formed by {g(m) : m M c } must be acyclic. Constraints 1 and 2 are the correctness conditions for the cover, Constraint 3 focuses on maximizing the cover M c and Constraint 4 enforces an acyclic circuit to be extracted from the CNF. A. Maximizing the Cover M c Constraint 1 is clearly true for all logic circuits. Constraint 2 is true since the output variable appears in every clause in the CNF signature. Consider the following proof by contradiction. Proof: Suppose a clause c is involved in matchings m i,m j and m i m j. Then there must exist a variable x c and x = out(m i ). Similarly, there exists y c and y = out(m j ). According to constraint 1, x y. So we have y I(m i ) and x I(m j ), which means g(m i ) has x as input and y as output; similarly g(m j ) has y as input and x as output and they form a cycle! The contradiction shows that each clause can only be involved in at most one matching. We propose a SAT based approach to solve this problem optimally using zchaff [1]. While, SAT like MIS, is NP-complete, there are several highly efficient SAT packages available. We use a Boolean variable to denote whether the matching is going to be present in the cover. So the problem of finding a maximum cover is equivalent to finding a satisfying assignment with maximum true variables, which is also known as the max-ones SAT problem [12]. We do not solve the general max-ones problem, but rather construct a solution for this specific instance. Constraint 1 can be encoded into a set of clauses in the form of (m 1 + m 2 )(m 1 + m 3 )(m 2 + m 3 ) if all three matchings m 1,m 2 and m 3 share the same variable as their output. When a clause is involved in n matchings, constraint 2 and 3 together require the one-hot property (one and only one of them is true) among these n matchings. For example, these are the derived clauses for the onehot constraint with 3 matchings: (m 1 +m 2 )(m 1 +m 3 )(m 2 +m 3 )(m 1 + m 2 + m 3 ). Therefore, the objective of our max-ones SAT problem is equivalent to maximizing the total number of matchings in the cover M c. Unlike constraint 1 and 2, constraint 3 is not always true. It will be true only if no clause is left uncovered by M c. In fact, it may cause the overall optimization problem to be over-constrained. However, we include it in our SAT based approach because it motivates the SAT solver to look for the maximum number of true variables, which is equivalent to the maximum matchings in cover M c. If we only have constraint 1 and 2, then the SAT solver could easily give a trivial satisfying solution with all variables set to false. This is due to the fact that all clauses generated according to constraint 1 and 2 are 0-implication, i.e. they can only imply variables to be false (or 0), but can never imply a variable to be true (or 1). Constraint 3 helps us to avoid this situation by introducing 1-implication clauses like (m 1 + m 2 + m 3 ) when a clause is involved in matching m 1, m 2 and m 3. We refer to this kind of a clause as a constraint 3 clause. If the resulting SAT instance, with all clauses generated according to constraint 1, 2 and 3, is satisfiable, then clearly we have found a maximum cover (possibly cyclic at this point) since every matched clause is involved. On the other hand, if the SAT instance turns out to be unsatisfiable, the only reason is because of the over-constraints imposed by constraint 3, some of which have to be relaxed in order to obtain a satisfying solution. This problem is known as the Partial MAX-SAT problem [13], which contains two types of clauses: relaxable (constraint 3 clauses in our case) and non-relaxable (all other clauses). The objective is to satisfy all non-relaxable clauses and maximum number of relaxable clauses. We adopt an iterative relaxation strategy [13] with the use of the unsatisfiable core [14] that can be provided by the SAT solver for unsatisfiable instances. An unsatisfiable core is a subset of the original CNF clauses that are unsatisfiable by themselves. For each unsatisfiable core found (in each iteration) with k (k > 0) constraint 3 clauses, we add an unique relaxation variable to each of the k clauses. We restrict these k relaxation variables to be one-hot, which ensures that at any time there can only be one and at most one clause being relaxed (i.e. its relaxation variable is true). The relaxation process continues until the problem instance becomes satisfiable. This iterative UNSAT core relaxation strategy provides the optimal solution [13]. B. Enforcing the Acyclic Property of the Resulting Circuit Our discussion so far has been focusing on finding the maximum cover. However, we also have to enforce it to be acyclic. These cycles in the extracted circuits are usually caused by the undirectional gates. A gate is called undirectional if its output variable cannot be uniquely determined based only on its CNF signature and it is called directional if otherwise. For example, an n-input XOR gate (undirectional) can have n different orientations in terms of its output signal without violating constraint 1, 2 or 3. However, among these n orientations, many of them are likely to cause a combinational cycle somewhere else in the circuit. We perform an acyclic check for each maximum cover found by SAT. If the resulting circuit is cyclic, the cycle is identified and the matchings corresponding to the cycle are grouped into a blocking clause [15], which is added back to the problem instance to avoid

4 the solutions containing this cycle. The current solution is hence invalidated and the SAT solver is asked to find another feasible maximum cover. For example, if gates g(m 1 ),g(m 2 ),...,g(m k ) {g(m) : m M c } create a combinational cycle in the circuit, then the corresponding matchings are blocked by adding the clause (m 1 + m m k ). Note that the adding of blocking clause utilizes the incremental [16] SAT feature of zchaff. Maintaining the maximum amount of the learned clauses, i.e. recording the most visited search space, is a great advantage. Since constraints 1, 2 and 3 guarantee a maximum cover, the resulting solution is a maximum cover with the acyclic property. The combined algorithm for both maximum cover and restriction to an acyclic circuit is given in Algorithm 2. Algorithm 2 Construct A Maximum Acyclic Cover 1: Given all possible candidate matchings, construct a SAT instance using constraint 1, 2 and 3. 2: while true do 3: while SAT solver returns UNSATISFIABLE do 4: Let C o := the UNSAT CORE 5: Iteratively relax all constraint 3 clauses in C o 6: end while 7: while SAT solver returns SATISFIABLE do 8: if Resulting graph is acyclic then 9: Return this maximum cover 10: else 11: Add blocking clause containing matchings in the cycle 12: end if 13: end while 14: end while Note that Algorithm 2 has nested WHILE loops because there may not be any acyclic solution at this point, which in turn means that we need to further relax certain constraint 3 clauses. We will present one such case (XOR-Chain) in Section IV. IV. EXPERIMENTAL RESULTS We performed extensive experiments on thousands of CNF descriptions [17], both circuit encoded and non-circuit encoded. Circuit encoded benchmarks include DIMACS, beijing, ISCAS85 and various IBM benchmarks. Non-circuit encoded benchmarks include hanoi and some difficult benchmarks used in the SAT 05 Competition [18], e.g. the VPN class of benchmarks that are generated by model analyzer Alloy [19] on VPN models. Due to the page limit, we try to present more representative benchmarks (i.e. benchmarks with largest/smallest extracted circuit structure using largest/smallest amount of time). Further, we present more non-circuit generated benchmarks since it is not surprising to see that a large amount of circuit structure can be extracted from circuit generated benchmarks. Our matching library consists of (N)AND, (N)OR gates up to 10 inputs, X(N)OR gate up to 4 inputs, INV, BUF and MAJ3 gates. It is worth mentioning that both the matching time and the covering time are dependent on the gate library. Obviously, the more gates we have in the library, the longer it takes to match all of them. The complexity of the gates in the library also affects the execution time. For example, the CNF signature of a 4-input XOR gate has 16 clauses, each of which has 5 literals. Even verifying a partial matching of this gate takes more time than verifying a complete matching of a 4-input AND gate, which has only 5 clauses, 4 of which are 2 literal clauses. All the experiments are conducted on a Dell PowerEdge 700 running Linux Fedora Core 1.0 (g++ GCC 3.3.2) with single Pentium 4 2.8GHz, 1MB L2 cache CPU on 800MHz main bus. The first row in Table I gives the result of c499 whose original CNF description contains 606 variables in 1870 clauses. Our pattern matcher detects a total of 1124 candidate matchings. After 46 iterations of cycle detection/elimination and 0 iteration of relaxation on constraint 3 clauses, we can successfully construct an acyclic combinational circuit using 564 (out of 1870) matchings found by the pattern matcher. The total number of clauses involved in the construction of this circuit is The largest connected component in the circuit involves 605 variables, which is just 1 less than the total number of variables in the CNF description. The remaining 1 variable and unmatched clauses correspond to the property assertion for this benchmark. Note that the largest connected component involves more variables than the size of the cover M c, this is because input variables are included in the connected component but are excluded from the cover since they do not match to any gate in the library. The pattern matcher takes 0.06 second and the construction of the circuit takes 0.04 second. Note that if a CNF comes from a circuit, it is guaranteed for the circuit structure to be extracted completely. The circuit structures extracted from non-circuit generated CNF may vary dramatically. For example, we can only extract a set of small circuit structures from hanoi6. While for benchmarks like Mat317, we could recover a large circuit structure that includes every variable in the problem. Note that there are still unmatched clauses in this case, which correspond to the undetected relationships among some of these variables. In circuit encoded benchmarks, Table I also A B Fig. 1. C D F An XOR chain with three inputs shows the result of an XOR-Chain with 16 inputs. The XOR-Chain benchmark is based on the logic equation (v 1 (v 2 (v 3 (... (v n 1 v n ))))) ((((v 1 v 2 ) v 3 )... v n 1 ) v n ). Figure 1 shows an XOR-Chain with 3 inputs. The final assertion is E G, hence the CNF description containing clauses (E + G)(E + G ) should always be unsatisfiable. However, note that (E +G)(E +G ) can be matched as an INV, which is shown with segmented lines in Figure 1. Such topology is always cyclic if we try to include all 4 XOR gate and the INV gate in our final circuit. As a result, a huge number of blocking clauses are added to avoid each possible cycle and eventually the problem turns unsatisfiable to include all 5 gates. After relaxing one of the constraint 3 clauses (leaving any one of the 5 gate uncovered), we can now find an acyclic solution with 4 gates. The XOR-Chain is an extreme case of a heavily cyclic circuit, which we never encountered in any other circuit encoded industrial benchmark. Although not shown in our results, there are cases where the number of detected gates is too large for the covering algorithm to find the optimal solution within given time limit, e.g. 1 hour. V. DERIVING CIRCUIT OBSERVABILITY DON T CARES FROM CNF: AN APPLICATION The ability to decode circuit structures from the CNF has many applications, such as applying various Circuit-SAT algorithms [10,20,21] on CNF-SAT; customized SAT solvers for different sets of benchmarks based on the characteristics of the extracted E G

5 TABLE I STATISTICS OF THE EXTRACTED CIRCUIT STRUCTURE FROM BOTH CIRCUIT ENCODED AND NON-CIRCUIT ENCODED BENCHMARKS. Cate- Number Number Matches Cover Clauses Largest Cyclic Relax Matching Covering Benchmark gory Variables Clauses M M c Used Compon. Iter. Iter. time (s) time (s) Circuit Benchmarks Non-Circuit Benchmarks c bitadd xorchain longmult longmult longmult IBM01r/k IBM06r/k hanoi par simon/mat simon/mat linvrinv marijn/el l pyhala VPN/clause VPN/clause VPN/clause VPN/clause VPN/clause circuit (e.g. different decision strategies for CNFs for different types of circuits), etc. In addition to the above applications, we give an example of a straightforward application, which is to derive the Circuit Observability Don t Cares (Cir-ODC) from the extracted circuit structure and use it to accelerate the SAT solver [8,22 24]. The notion of Cir-ODC is as follows. Some signal s, under certain conditions C, no longer affects the outputs of the circuit. These conditions, C, are referred to as observability don t care conditions for s [8]. Figure 2 shows a two input AND gate G, which takes the output Fig. 2. An AND gate G takes as input the only fan-out from a logic cone C. value of a logic cone C of gates as one of its inputs. The output value of the AND gate G is fixed to be 0 if its input from B is zero, regardless of the output value of C, and therefore the entire logic cone of C need not be considered any more if it has only one fan-out that goes into G. Correspondingly in SAT, all the clauses corresponding to C can be ignored in the SAT solver in subsequent search. These clauses can be treated as Cir-ODC clauses and those gate outputs as Cir-ODC variables, since they are unobservable at the outputs of the circuit. This is accomplished by adding certain don t care literals to these clauses which are handled specially in SAT. These don t care literals help the SAT solver to reduce the unnecessary Boolean Constraint Propagation and provide a better guide to the decision heuristic. On the other hand, the SAT solver has to be modified in several aspects (e.g. no implication on don t care literals, decision heuristic, conflict driven clause learning, etc.) to handle the Cir-ODC information. In the example given by Figure 2, if we use b to denote the output variable of B, then don t care literal b is the Cir-ODC B C G condition for C to be unobservable. Clearly we need circuit structure information to derive these don t care literals. With the CNF2CKT algorithm provided in this paper, we can do just that when only the CNF is available. Table II gives detailed performance comparison between zchaff with Cir-ODC handling capability and the original zchaff. The first row of Table II shows the results for benchmark longmult12 with 5974 variables, among which 4987 gates are identified (The detailed information of benchmark longmult12, e.g. number of clauses, size of the largest connected component, etc., can be found in Table I). The Cir-ODC computation algorithm derives a total number of 2190 Cir- ODC literals and the maximum number of Cir-ODC literals added to a particular clause is 24. The time used for extracting the maximum circuit structure by CNF2CKT is 0.69 seconds (gate matching takes 0.55 seconds and SAT covering takes 0.14 seconds as shown in Table I). The time used for detecting/propagating Cir-ODC literals is 0.04 seconds. zchaff with Cir-ODC handling capability takes seconds, which brings the total time used by this approach to seconds. While zchaff alone (no CNF2CKT, Cir-ODC, etc.) takes seconds on benchmark longmult12. zchaff with Cir-ODC handling capability shows obvious advantages on both circuit encoded and non-circuit encoded benchmarks. Note that the VPN class of benchmarks are difficult to solve (this is also the reason that they are given more time in our experiment as compared to other circuit encoded benchmarks) and clause8 is not solvable at SAT 05 Competition [18] by any solvers within 200 minutes. For small benchmarks like clause2, the overall performance of zchaff with Cir-ODC using CNF2CKT is comparable to zchaff alone due to the overhead caused by CNF2CKT. However, for large benchmarks like clause6 and clause8, the time taken by CNF2CKT is very small compared to the time taken by zchaff. clause10 is an extremely large benchmark (187MB) and CNF2CKT takes seconds, but the overall performance is still significantly better than zchaff alone. More experimental results are given in Figure 3. Note the execution time taken by zchaff with Cir-ODC also includes the time used by CNF2CKT in the gate matching/circuit construction and the time

6 TABLE II PERFORMANCE COMPARISON ON ZCHAFF WITH CIR-ODC INFORMATION OBTAINED USING CNF2CKT. Cate- Number Gates Cir-ODC Literals zchaff Using Cir-ODC from CNF2CKT Benchmark gory Variables Detected Total Max/Cls CNF2CKT CirODC zchaffdc Total Circuit Non-Circuit zchaff longmult longmult longmult IBM01r/k > 3600 IBM06r/k > 3600 VPN/clause VPN/clause VPN/clause VPN/clause mem out VPN/clause used in Cir-ODC computation. The benchmark families considered in experiments on using Cir-ODC information include longmult, ferry, fpga routing, parity, hard eq check and various IBM benchmarks. The Cir-ODC handling ability clearly improves the performance of zchaff, both in terms of reducing the average execution time and the number of time-outs. Time Used: zchaff Only Time Used: CNF2CKT + Cir-ODC + zchaff with Cir-ODC Handling Fig. 3. Scatter plot of the execution time in seconds. Time-out is set to 300 seconds. The time used by zchaff with Cir-ODC includes the time used by CNF2CKT and the Cir-ODC computation time. There are 220 points in this figure and 137/83 of them are above/below the dividing line. VI. CONCLUSIONS We have presented a practically efficient and optimal tool, CNF2CKT, for extracting the maximum circuit structure from any given CNF description according to a pre-specified gate library. The CNF-to-circuit decoding time is library dependent and short for most benchmarks. The extracted circuit structure is useful in many applications, particularly when the CNF is not encoded from a circuit, or the circuit descriptions are not readily available. We show an example of exploiting circuit observability don t cares in CNF-SAT. We believe that CNF2CKT could benefit other researchers, particularly in the academia, by providing a viable way to bridge the gap between circuit-sat and CNF-SAT so that successful techniques from either branch can be easily shared with the other one. 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