CPRI v6.0 IP Core User Guide

Transcription

1 CPRI v6.0 IP Core User Guide Last updated for Quartus Prime Design Suite: 17.0 IR3, 17.0, 17.0 Update 1, 17.0 Update 2 Subscribe UG Innovation Drive San Jose, CA

2 TOC-2 CPRI v6.0 IP Core User Guide Contents About the CPRI v6.0 IP Core CPRI v6.0 IP Core Supported Features CPRI v6.0 IP Core Device Family and Speed Grade Support Device Family Support CPRI v6.0 IP Core Performance: Device and Transceiver Speed Grade Support IP Core Verification Resource Utilization for CPRI v6.0 IP Cores Release Information Getting Started with the CPRI v6.0 IP Core Installation and Licensing Generating CPRI v6.0 IP Cores CPRI v6.0 IP Core File Structure CPRI v6.0 IP Core Parameters Integrating Your IP Core in Your Design: Required External Blocks Adding the Transceiver TX PLL IP Core Adding the Reset Controller Adding the Transceiver Reconfiguration Controller Adding the Off-Chip Clean-Up PLL Adding and Connecting the Single-Trip Delay Calibration Blocks Simulating Intel FPGA IP Cores Understanding the Testbench Running the Testbench Compiling the Full Design and Programming the FPGA Functional Description Interfaces Overview CPRI v6.0 IP Core Clocking Structure Example CPRI v6.0 Clock Connections in Different Clocking Modes CPRI v6.0 IP Core Reset Requirements Start-Up Sequence Following Reset Start-Up Sequence Interface Signals AUX Interface AUX Interface Signals AUX Interface Synchronization Auxiliary Latency Cycles Direct Interface CPRI Frame Data Format Direct IQ Interface Ctrl_AxC Interface Direct Vendor Specific Access Interface Real-Time Vendor Specific Interface

3 CPRI v6.0 IP Core User Guide TOC-3 Direct HDLC Serial Interface Direct L1 Control and Status Interface L1 Debug Interface Media Independent Interface (MII) to External Ethernet Block Gigabit Media Independent Interface (GMII) to External Ethernet Block CPU Interface to CPRI v6.0 IP Core Registers CPU Interface Signals Accessing the Hyperframe Control Words Auto-Rate Negotiation Extended Delay Measurement Extended Delay Measurement for Soft Internal Buffers Extended Delay Measurement for Intel Stratix 10 Hard FIFOs Extended Delay Measurement Interface Deterministic Latency and Delay Measurement and Calibration Delay Measurement and Calibration Features Delay Requirements Single-Hop Delay Measurement Multi-Hop Delay Measurement Delay Calibration Features CPRI v6.0 IP Core Transceiver and Transceiver Management Interfaces CPRI Link Main Transceiver Clock and Reset Signals Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface Intel Arria 10 and Intel Stratix 10 Transceiver Reconfiguration Interface Interface to the External Reset Controller Interface to the External PLL Transceiver Debug Interface Testing Features CPRI v6.0 IP Core Loopback Modes CPRI v6.0 IP Core Self-Synchronization Feature CPRI v6.0 IP Core Signals CPRI v6.0 IP Core L2 Interface CPRI v6.0 IP Core L1 Direct Access Interfaces CPRI v6.0 IP Core Management Interfaces CPRI v6.0 IP Core Transceiver and Transceiver Management Signals CPRI v6.0 IP Core Registers INTR Register L1_STATUS Register L1_CONFIG Register BIT_RATE_CONFIG Register PROT_VER Register TX_SCR Register RX_SCR Register CM_CONFIG Register CM_STATUS Register...5-9

4 TOC-4 CPRI v6.0 IP Core User Guide START_UP_SEQ Register START_UP_TIMER Register FLSAR Register CTRL_INDEX Register TX_CTRL Register RX_CTRL Register RX_ERR Register RX_BFN Register LOOPBACK Register TX_DELAY Register RX_DELAY Register TX_EX_DELAY Register RX_EX_DELAY Register ROUND_TRIP_DELAY Register XCVR_BITSLIP Register DELAY_CAL_STD_CTRL1 Register DELAY_CAL_STD_CTRL2 Register DELAY_CAL_STD_CTRL3 Register DELAY_CAL_STD_CTRL4 Register DELAY_CAL_STD_CTRL5 Register DELAY_CAL_STD_STATUS Register DELAY_CAL_RTD Register XCVR_TX_FIFO_DELAY Register XCVR_RX_FIFO_DELAY Register Additional Information... A-1 CPRI v6.0 IP Core User Guide Archives... A-1 CPRI v6.0 IP Core User Guide Revision History...A-2

5 About the CPRI v6.0 IP Core 1 UG Subscribe The Common Public Radio Interface (CPRI) v6.0 Intel FPGA IP core implements the CPRI Specification V6.0 ( ). CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE). The CPRI v6.0 IP core targets high-performance, remote, radio network applications. You can configure the CPRI v6.0 IP core as an RE or an REC. Figure 1-1: Typical CPRI Application on Intel FPGA Devices Example system implementation with a two-hop daisy chain. Optical links between devices support high performance. FPGA Routing Layer FPGA IQ Direct AUX AUX IQ Direct CPRI v6.0 IP Core (RE Slave) CPRI v6.0 IP Core (RE Master) CPRI v6.0 IP Core (RE Slave) CPRI CPRI CPRI Optical Link Optical Link FPGA CPRI CPRI v6.0 IP Core (REC) Base Band Module Clock Module Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered Innovation Drive, San Jose, CA 95134

6 1-2 CPRI v6.0 IP Core Supported Features UG CPRI v6.0 IP Core Supported Features The CPRI v6.0 IP core offers the following features: Compliant with the Common Public Radio Interface (CPRI) Specification V6.0 ( ) Interface Specification available on the CPRI Industry Initiative website ( Supports radio equipment controller (REC) and radio equipment (RE) module configurations. Supports the following CPRI link features: Configurable CPRI communication line bit rate (to , , , , , 6.144, , , or Gbps) using Intel FPGA on-chip high-speed transceivers. CPRI line bit rate auto-rate negotiation support. Configurable and run-time programmable synchronization mode: master port or slave port on a CPRI link. Scrambling and descrambling at and Gbps. Optional scrambling and descrambling at , , and Gbps. Transmitter (Tx) and receiver (Rx) delay measurement and calibration. Optional support for single-trip delay calibration. Optional round-trip delay calibration. L1 link status and alarm (Z.130.0) control and status monitoring. Access to all Vendor Specific data. Diagnostic parallel reverse loopback paths. Diagnostic serial and parallel forward loopback paths. Diagnostic stand-alone slave testing mode. Includes the following interfaces: Register access interface to external or on-chip processor, using the Intel Avalon Memory-Mapped (Avalon-MM) interconnect specification. Optional auxiliary (AUX) interface for full access to raw CPRI frame. Provides direct access to full radioframe, synchronizes the frame position with timing references, and enables routing application support from slave to master ports to implement daisy-chain topologies. Optional choice of IEEE BASE-X compliant 10/100 Mbps MII or 1000BASE-X compliant 1Gbps GMII for Ethernet frame access. Optional direct I/Q access interface enables integration of all user-defined air standard I/Q mapping schemes. Optional external I/Q mapper and demapper modules with reference design support. Optional external I/Q compression and decompression modules with reference design support. Optional vendor specific data access interfaces provide direct access to Vendor Specific (VS), Control AxC (Ctrl_AxC), and Real-time Vendor Specific (RTVS) subchannels. Optional HDLC serial interface provides direct access to slow control and management subchannels. Optional L1 inband interface provides direct access to Z link status and alarm control word. About the CPRI v6.0 IP Core

7 UG CPRI v6.0 IP Core Device Family and Speed Grade Support 1-3 Related Information CPRI Industry Initiative website For a detailed specification of the CPRI protocol refer to the CPRI Specification V6.0 ( ) Interface Specification available on the CPRI Industry Initiative website. Altera wiki CPRI v6.0 IP core information Includes links to the I/Q mapper and other CPRI v6.0 IP core reference designs. Intel FPGA Design Store Includes CPRI v6.0 reference designs. CPRI v6.0 IP Core Device Family and Speed Grade Support The following sections list the device family and device speed grade support offered by the CPRI v6.0 IP core: Device Family Support Table 1-1: Intel FPGA IP Core Device Support Levels Device Support Level Definition Advance Preliminary Final The IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (datapath width, burst depth, I/ O standards tradeoffs). Intel has verified the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution. Intel has verified the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. Table 1-2: CPRI v6.0 IP Core Device Family Support Shows the level of support offered by the CPRI v6.0 IP core for each Intel FPGA device family. About the CPRI v6.0 IP Core

8 1-4 Device Family Support UG Device Family Support Intel Stratix 10 Intel Arria 10 Arria V (GX and GT) Arria V GZ Cyclone V (GX and GT) Stratix V (GX and GT) Other device families Advance Intel Stratix 10 device support is available only in the Intel Quartus Prime Pro Edition software v17.0 IR3. It is not available in software releases 17.0, 17.0 Update 1, and 17.0 Update 2. The software release v17.0 IR3 supports only L-tile devices. Default support level provided in the Intel Quartus Prime software. Refer to the Quartus Prime Standard Edition Software and Device Support Release Notes and the Quartus Prime Pro Edition Software and Device Support Release Notes for the relevant software release. Default support level provided in Intel Quartus Prime Standard Edition software. Refer to the Quartus Prime Standard Edition Software and Device Support Release Notes for the relevant software release. Default support level provided in Intel Quartus Prime Standard Edition software. Refer to the Quartus Prime Standard Edition Software and Device Support Release Notes for the relevant software release. Default support level provided in Intel Quartus Prime Standard Edition software. Refer to the Quartus Prime Standard Edition Software and Device Support Release Notes for the relevant software release. Default support level provided in Intel Quartus Prime Standard Edition software. Refer to the Quartus Prime Standard Edition Software and Device Support Release Notes for the relevant software release. No support Related Information CPRI v6.0 IP Core Performance: Device and Transceiver Speed Grade Support on page 1-5 About the CPRI v6.0 IP Core

9 UG CPRI v6.0 IP Core Performance: Device and Transceiver Speed Grade Support 1-5 Timing and Power Models Reports the default device support levels in the current version of the Intel Quartus Prime Standard Edition software. Timing and Power Models Reports the default device support levels in the current version of the Intel Quartus Prime Pro Edition software. CPRI v6.0 IP Core Performance: Device and Transceiver Speed Grade Support Table 1-3: Slowest Supported Device Speed Grade and Supported Transceiver Speed Grade Device Family Lower device speed grade numbers correspond to faster devices. The entry -x indicates that both the industrial speed grade Ix and the commercial speed grade Cx are supported for this device family and CPRI line bit rate. Table entries show slowest supported device speed grade / supported transceiver speed grade. Intel Stratix 10 Intel Arria 10 Stratix V GT Stratix V GX Arria V GZ Arria V GX Arria V GT Cyclone V GT Cyclone V GX CPRI Line Bit Rate (Gbps) (1) (1) -2 / -3-3 / -4-3 / H3-2 / H2-4 / H3-2 / H2-4 / H3-3 / H2 (1) -6 / H6-5 / H4-5 / H4 (1) -5/H3 (1) -7 / H5 (1) -8 / H7-7 / H6 (1) (1) The CPRI v6.0 IP core does not support this CPRI line bit rate for this device family. About the CPRI v6.0 IP Core

10 1-6 IP Core Verification UG IP Core Verification To ensure functional correctness of the CPRI v6.0 IP core, Intel performs extensive validation through both simulation and hardware testing. Before releasing a version of the CPRI v6.0 IP core, Intel runs comprehensive regression tests in the associated version of the Intel Quartus Prime software. Related Information Knowledge Base Errata for CPRI v6.0 IP core Some exceptions to functional correctness are documented in the CPRI v6.0 IP core errata. Altera wiki CPRI v6.0 Errata page Other exceptions to functional correctness are documented on the Altera wiki CPRI v6.0 Errata page. Resource Utilization for CPRI v6.0 IP Cores Resource utilization changes depending on the parameter settings you specify in the CPRI v6.0 parameter editor. For example, with every additional interface you enable, the IP core requires additional resources to implement the module that supports that interface. The resource utilization numbers are approximate as the Intel Quartus Prime Fitter assigns resources based on the entirety of your design. The numbers below result from a single run on a simple design. Your results may vary. Table 1-4: Minimum and Maximum IP Core Variations for Resource Utilization Reporting The IP core FPGA resource utilization table reports resource utilization for a minimum IP core variation and a maximum IP core variation. Parameters not specified remain at their default values, or their values do not affect resource utilization. Line bit rate Parameter Minimum Variation Maximum Variation Gbps for target device in the Intel Arria 10 and Intel Stratix 10 device families, Gbps for all other device families Synchronization mode Master Master Operation mode TX/RX Duplex TX/RX Duplex Core clock source input Internal Internal Receiver soft buffer depth 4 8 Auxiliary and direct interfaces write latency cycle(s) Enable interface, for all optional direct interfaces in the L1 Features tab 9 Off Maximum bit rate (device family dependent) On About the CPRI v6.0 IP Core

11 UG Resource Utilization for CPRI v6.0 IP Cores 1-7 Parameter Minimum Variation Maximum Variation Ethernet PCS interface NONE GMII L2 Ethernet PCS Tx/Rx FIFO depth Enable single-trip delay calibration Enable round-trip delay calibration Round-trip delay calibration FIFO depth 11 Off Off 4 Off On Table 1-5: IP Core FPGA Resource Utilization Lists the resources and expected performance for minimum and maximum variations of the CPRI v6.0 IP core in each supported device family. These results were obtained using the Intel Quartus Prime v17.0 IR3 software on an Intel Stratix 10 device, and using the Intel Quartus Prime v17.0 software for all other target device families. The numbers of ALMs and logic registers are rounded up to the nearest 100. The numbers of ALMs, before rounding, are the ALMs needed numbers from the Intel Quartus Prime Fitter Report. Intel Stratix 10 Device (with L-Tile Transceivers) ALMs Logic Registers M20K Blocks Minimum ( Gbps CPRI line bit rate) Maximum ( Gbps CPRI line bit rate) Intel Arria 10 Device ALMs Logic Registers M20K Blocks Minimum ( Gbps CPRI line bit rate) Maximum ( Gbps CPRI line bit rate) Arria V GX or GT Device ALMs Logic Registers M10K Blocks Minimum ( Gbps CPRI line bit rate) Maximum (6.144 Gbps CPRI line bit rate) Arria V GZ Device ALMs Logic Registers M20K Blocks Minimum ( Gbps CPRI line bit rate) Maximum ( Gbps CPRI line bit rate) About the CPRI v6.0 IP Core

12 1-8 Release Information UG Cyclone V GX or GT Device ALMs Logic Registers M10K Blocks Minimum ( Gbps CPRI line bit rate) Maximum ( Gbps CPRI line bit rate) Stratix V GX or GT Device ALMs Logic Registers M20K Blocks Minimum ( Gbps CPRI line bit rate) Maximum ( Gbps CPRI line bit rate) Related Information Fitter Resources Reports in the Intel Quartus Prime Help Information about Intel Quartus Prime resource utilization reporting, including ALMs needed. Release Information Table 1-6: CPRI v6.0 IP Core Current Release Information Item Compatible Intel Quartus Prime Software Version Description 17.0 IR3, 17.0, 17.0 Update 1, and 17.0 Update 2 Release Date Ordering Codes IP-CPRI-V6 About the CPRI v6.0 IP Core

13 Getting Started with the CPRI v6.0 IP Core 2 UG Subscribe Explains how to install, parameterize, and simulate the CPRI v6.0 IP core. Installation and Licensing on page 2-2 The CPRI v6.0 IP core is an extended FPGA IP core which is not included with the Intel Quartus Prime release. This section provides a general overview of the Intel extended FPGA IP core installation process to help you quickly get started with any Intel extended FPGA IP core. Generating CPRI v6.0 IP Cores on page 2-3 After you install and integrate the extended IP core in the ACDS release, the CPRI v6.0 IP core supports the standard customization and generation process. This IP core does not generate a testbench or example design simultaneously with generation of the IP core. Instead, you must use the Example Design button in the CPRI v6.0 parameter editor to generate the testbench. This IP core is not supported in Qsys. CPRI v6.0 IP Core File Structure on page 2-3 The Intel Quartus Prime software generates the following IP core output file structure. CPRI v6.0 IP Core Parameters on page 2-7 The CPRI v6.0 parameter editor provides the parameters you can set to configure the CPRI v6.0 IP core and simulation testbench. Integrating Your IP Core in Your Design: Required External Blocks on page 2-17 You must connect your CPRI v6.0 IP core to some additional required design components. Your design can simulate and compile without some of these connections and logical blocks, but it will not function correctly in hardware unless all of them are present and connected in your design. Simulating Intel FPGA IP Cores on page 2-25 The Intel Quartus Prime software supports RTL- and gate-level design simulation of Intel FPGA IP cores in supported EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation. Understanding the Testbench on page 2-26 Intel provides a demonstration testbench with the CPRI v6.0 IP core. Running the Testbench on page 2-26 To run the CPRI v6.0 IP core demonstration testbench, follow these steps. Compiling the Full Design and Programming the FPGA on page 2-28 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered Innovation Drive, San Jose, CA 95134

14 2-2 Installation and Licensing Related Information Introduction to Intel FPGA IP IP Cores Additional information about generating an Intel FPGA IP core and integrating it in your Intel Quartus Prime project. UG Installation and Licensing The CPRI v6.0 IP core is an extended FPGA IP core which is not included with the Intel Quartus Prime release. This section provides a general overview of the Intel extended FPGA IP core installation process to help you quickly get started with any Intel extended FPGA IP core. The Intel extended FPGA IP cores are available from the Altera Self-Service Licensing Center (SSLC). Refer to Related Information below for the correct link for this IP core. Figure 2-1: IP Core Installation Directory Structure Directory structure after you install the CPRI v6.0 IP core. Intel Quartus Prime installation directory ip Contains the Intel FPGA IP Library and third-party IP cores altera_cloud Contains the Intel FPGA extended IP cores that you install cpri_ii Contains the CPRI v6.0 IP core files Table 2-1: IP Core Installation Locations Location Software Platform <drive>:\intelfpga_pro\<version>\ quartus\ip\altera_cloud <drive>:\intelfpga\<version>\quartus\ ip\altera_cloud <home directory>:/intelfpga_pro/ <version>/quartus/ip/altera_cloud <home directory>:/intelfpga/<version> /quartus/ip/altera_cloud Intel Quartus Prime Pro Edition Intel Quartus Prime Standard Edition Intel Quartus Prime Pro Edition Intel Quartus Prime Standard Edition Windows * Windows Linux * Linux Related Information Intel FPGA website Getting Started with the CPRI v6.0 IP Core

15 UG Generating CPRI v6.0 IP Cores 2-3 Self-Service Licensing Center (SSLC) After you purchase the CPRI v6.0 IP core, the IP core is available for download from the SSLC page in your myaltera account. You must create a myaltera account if you do not have one already, and log in to access the SSLC. On the SSLC page, click Run for this IP core. The SSLC provides an installation dialog box to guide your installation of the IP core. Generating CPRI v6.0 IP Cores You can quickly configure a custom IP variation in the parameter editor. Use the following steps to specify CPRI v6.0 IP core options and parameters in the parameter editor. 1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name CPRI v6.0. The parameter editor appears. 2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys (in Intel Quartus Prime Standard Edition) or <your_ip>.ip (in Intel Quartus Prime Pro Edition). Click OK. 3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to "IP Core Parameters" for information about specific IP core parameters. Specify parameters defining the IP core functionality, port configurations, and device-specific features. Specify options for processing the IP core files in other EDA tools. 4. Click Generate HDL. The Generation dialog box appears. 5. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications. 6. To generate a simulation testbench, click Generate Example Design. Please refer to the instructions in the Running the Testbench section. 7. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template. 8. Click Finish. The parameter editor adds the top-level.qsys or.ip file to the current project automatically. If you are prompted to manually add the.qsys file to the project, click Project > Add/Remove Files in Project to add the file. 9. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports. CPRI v6.0 IP Core File Structure The Intel Quartus Prime software generates the following IP core output file structure. Getting Started with the CPRI v6.0 IP Core

16 2-4 CPRI v6.0 IP Core File Structure Figure 2-2: IP Core Generated Files UG <project directory> <your_ip>.qsys or.ip - System or IP integration file <your_ip>.sopcinfo - Software tool-chain integration file (Standard Edition only) <your_ip> IP variation files <your_ip>_<n> IP variation files <your_ip>.cmp - VHDL component declaration file <your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or.vhd - Sample instantiation template <your_ip>.ppf - XML I/O pin information file <your_ip>.qip - Lists IP synthesis files <your_ip>.sip - Lists files for simulation <your_ip>_generation.rpt - IP generation report <your_ip>.debuginfo - Contains post-generation information (Standard Edition only) <your_ip>.html - Connection and memory map data <your_ip>.bsf - Block symbol schematic <your_ip>.spd - Combines individual simulation scripts cpri_ii_0_testbench Example location for your IP core design example files. The default location is cpri_ii_0_testbench, but you are prompted to specify a different path <your_ip>.qgsimc - Lists simulation parameters to support incremental regeneration (Pro Edition only) <your_ip>.qgsynthc - Lists synthesis parameters to support incremental regeneration (Pro Edition only) sim Simulation files synth IP synthesis files <ip subcores_ver> Subcore libraries <EDA tool name> Simulator scripts <your_ip>.v or.vhd Top-level simulation file <simulator_setup_scripts> <your_ip>.v or.vhd Top-level IP synthesis file synth Subcore synthesis files <HDL files> sim Subcore Simulation files <HDL files> Table 2-2: IP Core Generated Files File Name Description <your_ip>.qsys (Intel Quartus Prime Standard Edition only) <your_ip>.ip (Intel Quartus Prime Pro Edition only) The Qsys system or top-level IP variation file. <your_ip> is the name that you give your IP variation. Getting Started with the CPRI v6.0 IP Core

17 UG CPRI v6.0 IP Core File Structure 2-5 File Name <system>.sopcinfo <your_ip>.cmp <your_ip>.html <your_ip>_generation.rpt <your_ip>.debuginfo <your_ip>.qgsimc <your_ip>.qgsynthc <your_ip>.qip <your_ip>.csv <your_ip>.bsf <your_ip>.spd <your_ip>.ppf <your_ip>_bb.v Description Describes the connections and IP component parameterizations in your Qsys system. You can parse its contents to get requirements when you develop software drivers for IP components. (Intel Quartus Prime Standard Edition only) Downstream tools such as the Intel Nios II tool chain use this file. The.sopcinfo file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component. The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files. A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments. IP or Qsys generation log file. A summary of the messages during IP generation. Contains post-generation information. Used to pass System Console and Bus Analyzer Toolkit information about the Qsys interconnect. The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect. (Intel Quartus Prime Standard Edition only) Lists simulation parameters to support incremental regeneration. (Intel Quartus Prime Pro Edition only) Lists synthesis parameters to support incremental regeneration. (Intel Quartus Prime Pro Edition only) Contains all the required information about the IP component to integrate and compile the IP component in the Quartus Prime software. Contains information about the upgrade status of the IP component. A Block Symbol File (.bsf) representation of the IP variation for use in Quartus Prime Block Diagram Files (.bdf). Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The.spd file contains a list of files generated for simulation, along with information about memories that you can initialize. The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner. You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box. Getting Started with the CPRI v6.0 IP Core

18 2-6 CPRI v6.0 IP Core File Structure UG File Name <your_ip>.sip <your_ip>_inst.v and _ inst.vhd <your_ip>.regmap <your_ip>.svd <your_ip>.v and <your_ip>.vhd mentor/ aldec/ synopsys/vcs/ synopsys/vcsmx/ cadence/ submodules/ <child IP cores>/ Description Contains information required for NativeLink simulation of IP components. You must add the.sip file to your Intel Quartus Prime project. HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation. If IP contains register information,.regmap file generates. The.regmap file describes the register map information of master and slave interfaces. This file complements the.sopcinfo file by providing more detailed register information about the system. This enables register display views and user customizable statistics in the System Console. Allows hard processor system (HPS) System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system. During synthesis, the.svd files for slave interfaces visible to System Console masters are stored in the.sof file in the debug section. System Console reads this section, which Qsys can query for register map information. For system slaves, Qsys can access the registers by name. HDL files that instantiate each submodule or child IP core for synthesis or simulation. Contains a ModelSim script msim_setup.tcl to set up and run a simulation. Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation. Contains a shell script vcs_setup.sh to set up and run a VCS simulation. Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX simulation. Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation. Contains HDL files for the IP core submodule. For each generated child IP core directory, Qsys generates synth/ andsim/ sub-directories. Getting Started with the CPRI v6.0 IP Core

19 UG CPRI v6.0 IP Core Parameters 2-7 CPRI v6.0 IP Core Parameters The CPRI v6.0 parameter editor provides the parameters you can set to configure the CPRI v6.0 IP core and simulation testbench. The CPRI v6.0 parameter editor has three tabs. Table 2-3: General CPRI v6.0 IP Core Parameters Describes the general parameters for customizing the CPRI v6.0 IP core. These parameters appear on the General tab in the CPRI v6.0 parameter editor. Parameter Options Default Setting Parameter Description Line bit rate (Mbits/ s) Lowest bit rate supporte d for the device family Selects the CPRI line bit rate. Refer to CPRI v6.0 IP Core Performance: Device and Transceiver Speed Grade Support on page 1-5 for supported CPRI line bit rates in the supported device families. The parameter editor does not allow you to specify a CPRI line bit rate that the target device does not support. Synchronization mode Master Slave Master Specifies whether the CPRI v6.0 IP core is configured as a CPRI link master or a CPRI link slave. The value of this parameter determines the initial and reset clocking mode of the CPRI v6.0 IP core. You can modify the IP core clocking mode dynamically by modifying the value of the synchronization_mode field of the L1_CONFIG register. Operation mode TX/RX Duplex TX Simplex RX Simplex TX/RX Duplex Specifies whether the CPRI v6.0 IP core is configured with RX functionality only (RX Simplex), with TX functionality only (TX Simplex), or with both RX and TX functionality (TX/TX Duplex). If you specify a simplex mode, the Quartus Prime Fitter synthesizes logic for only one direction of traffic. If the CPRI v6.0 IP core is in TX simplex operation mode, it can transmit on the CPRI link but cannot receive. If the CPRI v6.0 IP core is in RX simplex operation mode, it can receive traffic on the CPRI link but cannot transmit. Currently, IP core variations that target an Intel Stratix 10 device support only the TX/RX Duplex mode. Getting Started with the CPRI v6.0 IP Core

20 2-8 CPRI v6.0 IP Core Parameters UG Parameter Options Default Setting Parameter Description Core clock source input External Internal Internal Specifies the clock source of the cpri_coreclk. In the internal clocking scheme, you should drive the cpri_coreclk with the cleaned-up xcvr_ recovered_clk in CPRI slave IP cores, and with the external master clock in CPRI master IP cores. In this clocking scheme, the IP core uses the cpri_ coreclk input clock only when the IP core is running at the CPRI line bit rate of or Gbps, The external clocking scheme supports the singletrip delay calibration feature. In this clocking scheme, the IP core uses this clock at all CPRI line bit rates. You can drive the cpri_coreclk input clock with the tx_clkout output clock from the TX PCS. Transmitter local clock division factor Specifies the division factor for the local clock divider. The IP core divides the high speed clock from the transceiver TX PLL (xcvr_ext_pll_clk) to generate the serial TX clock. This feature supports the configuration of multiple instances of the CPRI v6.0 IP core that run at different CPRI line bit rates but share use of the same TX PLL. This parameter is not available if you set the value of Operation mode to RX Simplex. IP core variations that target an Intel Arria 10 device or an Intel Stratix 10 device, with Line bit rate set to Mbps or slower, support only the value of 1. Getting Started with the CPRI v6.0 IP Core

21 UG CPRI v6.0 IP Core Parameters 2-9 Parameter Options Default Setting Parameter Description Number of receiver CDR reference clock(s) Receiver CDR reference clock frequency (MHz) 1 2 Per drop-down menu 1 Specifies the width of the receiver reference clock that controls the receiver. The CPRI v6.0 IP core supports the selection of one or two clocks. This option supports auto-negotiation to and from the CPRI line bit rate of Gbps in CPRI v6.0 IP core variations that target a Stratix V device. Refer to "IP Core Clocking Structure." If you set this parameter to the value of 1, the xcvr_ cdr_refclk is a single clock. If you set this parameter to the value of 2, the xcvr_cdr_refclk input signal is two bits wide, to support two distinct reference clocks. Intel recommends that you specify a two-bit clock for Stratix V variations that are expected to implement auto-negotiation up to a Gbps CPRI line bit rate. In this case the typical design drives one bit of the xcvr_cdr_refclk clock with a common MHz clock for the lower CPRI line bit rates and drives the other bit with a MHz clock for the Gbps CPRI line bit rate. However, these specific clock frequencies are not required. If the value of this parameter is 2, the receiver clocks the CDR with the xcvr_cdr_refclk[0] input signal by default. You can switch the receiver to use xcvr_ cdr_refclk[1], or back to xcvr_cdr_refclk[0], by dynamically reconfiguring the RX transceiver. IP core variations that target a device family other than the Stratix V device family, support only a single-bit receiver reference clock. This parameter is not available if you set the value of Operation mode to TX Simplex Specifies the incoming reference clock frequency for the receiver CDR PLL, in MHz. You must drive the input clock xcvr_cdr_refclk or xcvr_cdr_refclk[0] at the frequency you specify for this parameter. This parameter is not available if you set the value of Operation mode to TX Simplex. Getting Started with the CPRI v6.0 IP Core

22 2-10 CPRI v6.0 IP Core Parameters UG Parameter Options Default Setting Parameter Description VCCR_GXB and VCCT_GXB supply voltage for the transceiver 1_1V 1_0V 1_0V Specifies whether the transceiver supply voltage is 1.1 V or 1.0 V. The supply voltage must match the voltage you specify for this parameter, in IP core variations that target an Intel Stratix 10 device. This parameter affects only IP core variations that target an Intel Stratix 10 device. You can ignore it for other device families. Recovered clock source PCS PMA PCS Specifies the clock source of the xcvr_recovered_ clk. Intel recommends that you set this parameter to the value of PMA in IP core variations that target a Stratix V device, if you expect your IP core to autonegotiate to or from the CPRI line bit rate of Gbps. In this case, sourcing the recovered clock from the PMA improves jitter on that clock. If you specify the PCS source, the IP core switches between two PCS-internal clocks at auto-negotiation to or from the CPRI line bit rate of Gbps. This parameter is not available for CPRI master IP cores IP cores that target an Intel Stratix 10 device IP cores for which you set the value of Operation mode to TX Simplex Receiver soft buffer depth 4, 5, 6, 7, or 8 6 The value you specify for this parameter is log 2 of the IP core Layer 1 Rx buffer depth.the IP core supports a maximum Layer 1 RX buffer depth of 256. The default depth of the buffer is 64, specified by the parameter default value of 6. For most systems, the default buffer depth is adequate to handle dispersion, jitter, and drift that can occur on the link while the system is running. However, the parameter is available for cases in which additional depth is required. Increasing the value of this parameter increases resource utilization. Increasing the value of this parameter affects latency only when the buffer fills beyond the default capacity. In that case, the larger buffer increases latency but prevents data loss. The user guide refers to this parameter value as RX_ BUF_DEPTH. This parameter is not available if you set the value of Operation mode to TX Simplex. Getting Started with the CPRI v6.0 IP Core

23 UG CPRI v6.0 IP Core Parameters 2-11 Parameter Options Default Setting Parameter Description Enable line bit rate auto-negotiation On Off Off Turn on the Enable line bit rate auto-negotiation parameter to specify that your CPRI v6.0 IP core supports auto-rate negotiation. If you turn on this parameter, your IP core does not implement auto-negotiation. You must dynamically reconfigure the transceiver to modify the CPRI line bit rate and implement auto-negotiation. However, if you turn off this parameter, the IP core does not support bit line rate auto-negotiation, and you cannot modify the CPRI line bit rate dynamically. If you turn off this parameter and also turn off Enable start-up sequence state machine, Enable single-trip delay calibration, and in Intel Arria 10 devices, the Enable ADME, transceiver capability, control and status registers access, the transceiver reconfiguration interface is not available. This parameter is available when you specify a CPRI line bit rate (value for the Line bit rate parameter) that is greater than Mbps. This parameter is not yet available for Intel Stratix 10 devices. Enable line bit rate auto-negotiation down to Mbps On Off Off Turn on this parameter to specify that your autorate negotiation enabled CPRI v6.0 IP core can support auto-rate negotiation all the way down to the CPRI line bit rate of Gbps. This parameter is available for devices that support a CPRI line bit rate of Mbps, and when you turn on Enable line bit rate auto-negotiation. Table 2-4: CPRI v6.0 IP Core Interface Feature Parameters Describes the parameters for customizing the CPRI v6.0 IP core Layer 1 and Layer 2 interfaces and testing features. These parameters appear on the Interfaces tab in the CPRI v6.0 parameter editor. Parameter Options Default Setting Parameter Description L1 Features Management (CSR) interface standard Currently, only the Avalon- MM CPU interface is available in the CPRI v6.0 IP core. Selects the interface specification that describes the behavior of the CPRI v6.0 IP core register access interface. Getting Started with the CPRI v6.0 IP Core

24 2-12 CPRI v6.0 IP Core Parameters UG Parameter Options Default Setting Parameter Description Avalon-MM interface addressing type Word Byte Word Specifies the addressing mode for the Avalon-MM CPU interface.if the addressing mode is Word, you must ensure you correctly align the connections between Avalon-MM components. This parameter specifies how other components must connect to the cpu_address bus on the CPU interface. Auxiliary and direct interfaces write latency cycle(s) 0 to 9 0 Specifies the additional write latency on the AUX TX interface and other direct TX interfaces to the CPRI v6.0 IP core. The write latency is the number of cpri_clkout cycles from when the aux_tx_seq output signal has the value of 0 to when user logic writes data to the AUX TX interface. For other direct interfaces, the IP core notifies user logic when it is ready for input and the user does not need to monitor the aux_tx_ seq signal. When Auxiliary and direct interfaces write latency cycle(s) has the value of zero, the write latency on the direct TX interfaces is one cpri_ clkout cycle. When Auxiliary and direct interfaces write latency cycle(s) has the value of N, the write latency is (1+N) cpri_clkout cycles. Set this parameter to a value that provides user logic with sufficient advance notice of the position in the CPRI frame. The processing time that user logic requires after determining the current position in the CPRI frame is implementation specific. This parameter is available if you turn on at least one direct interface in your CPRI v6.0 IP core variation. Enable auxiliary interface On Off Off Turn on this parameter to include the AUX interface in your CPRI v6.0 IP core. The AUX interface provides full access to the raw CPRI frame. Getting Started with the CPRI v6.0 IP Core

25 UG CPRI v6.0 IP Core Parameters 2-13 Parameter Options Default Setting Parameter Description Enable all control word access via management interface On Off Off Turn on this parameter to enable access to all control words in a hyperframe using the CPRI v6.0 CTRL_INDEX, TX_CTRL, and RX_CTRL registers. Use this option with caution. During transmission, this feature has higher priority than the MII, the GMII, the HDLC serial interface, the L1 control and status interface, and the generation of special symbols (K28.5, D16.2, /S/, /T/), and can overwrite standard control words in the hyperframe. Enable direct Z alarm bits access interface On Off Off Turn on this parameter to include a dedicated L1 control and status interface to communicate the contents of the CPRI frame Z word, which includes alarms and reset signals. Enable direct ctrl_axc access interface On Off Off Turn on this parameter to include a dedicated interface to access the Ctrl_AxC subchannels in the CPRI frame. Enable direct vendor specific access interface On Off Off Turn on this parameter to include a dedicated interface to access the VS subchannels in the CPRI frame. Enable direct realtime vendor specific interface On Off Off Turn on this parameter to include a dedicated interface to access the RTVS subchannel in the CPRI frame. This parameter is available when you specify a CPRI line bit rate of Mbps. Enable start-up sequence state machine On Off Off Turn on this parameter to include a start-up sequence state machine in the CPRI v6.0 IP core. If you turn off this parameter and also turn off Enable line bit rate auto-negotiation, Enable single-trip delay calibration, and in Intel Arria 10 and Intel Stratix 10 devices, the Enable ADME, transceiver capability, control and status registers access, the transceiver reconfiguration interface is not available. This parameter is available if you set the value of Operation mode to TX/RX Duplex. Getting Started with the CPRI v6.0 IP Core

26 2-14 CPRI v6.0 IP Core Parameters UG Parameter Options Default Setting Parameter Description Enable protocol version and C&M channel setting autonegotiation On Off Off Turn on this parameter to include a negotiator block that performs auto-negotiation of L1 inband protocol version (communicated in CPRI frame position Z.2.0) and L2 C&M rates (communicated in CPRI frame positions Z.66.0 and Z.194.0). This parameter is available when you turn on Enable start-up sequence state machine. Enable direct I/Q mapping interface On Off Off Turn on this parameter to include a dedicated interface to access the raw I/Q data bytes in the CPRI frame. L2 Features Enable HDLC serial interface On Off Off Turn on this parameter to include a dedicated interface to communicate the contents of the slow C&M subchannels. For full HDLC communication, you must connect a user-defined HDLC module to this interface. Ethernet PCS interface NONE MII GMII NONE Specify whether to include an MII or GMII port to communicate with the fast C&M (Ethernet) CPRI subchannel. You can also specify that the IP core does not support either interface. An MII port complies with the IEEE BASE-X 100Mbps MII specification, A GMII port complies with the IEEE BASE-X 1Gbps GMII specification. For full Ethernet communication, you must connect a user-defined Ethernet MAC to this interface. L2 Ethernet PCS Tx/ Rx buffer depth 7, 8, 9, 10, 11 7 The value you specify for this parameter is log 2 of the IP core Layer 2 Ethernet PCS Rx buffer depth and Tx buffer depth. The IP core supports a maximum Layer 2 Ethernet PCS buffer depth of 1024 for MII and 2048 for GMII. This parameter is available when you include an MII or GMII port to communicate with the fast C&M (Ethernet) CPRI subchannel by selecting the value of MII or GMII for the Ethernet PCS interface parameter. The new value of 11 is supported only for GMII. Debug Features Getting Started with the CPRI v6.0 IP Core

27 UG CPRI v6.0 IP Core Parameters 2-15 Parameter Options Default Setting Parameter Description Enable L1 debug interfaces On Off Off Turn on this parameter to include dedicated transceiver status and L1 Rx status interfaces to support debug. This parameter is not available if you set the value of Operation mode to TX Simplex. Enable ADME, transceiver capability, control and status registers access On Off Off Turn on this parameter to support debugging through the System Console and to expose transceiver registers. If you turn off this parameter and also turn off Enable line bit rate autonegotiation, Enable start-up sequence state machine, and Enable single-trip delay calibration, the Intel Arria 10 or Intel Stratix 10 transceiver reconfiguration interface is not available. This parameter is available only for Intel Arria 10 and Intel Stratix 10 devices. Enable transceiver PMA serial forward loopback path On Off Off Turn on this parameter to enable transceiver PMA serial forward loopback. To turn on transceiver PMA serial forward loopback (Tx to Rx), you must also write the value of 2'b01 to the loop_forward field of the LOOPBACK register at offset 0x44. This parameter is not available if you set the value of Operation mode to TX Simplex or to RX Simplex. Enable parallel forward loopback paths On Off Off Turn on this parameter to enable other internal parallel forward loopback paths (Tx to Rx). To turn on internal parallel forward loopback, you must also write a non-zero value to the loop_ forward field of the LOOPBACK register at offset 0x44. This parameter is not available if you set the value of Operation mode to TX Simplex or to RX Simplex. Getting Started with the CPRI v6.0 IP Core

28 2-16 CPRI v6.0 IP Core Parameters UG Parameter Options Default Setting Parameter Description Enable parallel reversed loopback paths On Off Off Turn on this parameter to enable internal parallel reverse loopback (Rx to Tx). To turn on reverse loopback, you must also write a non-zero value to the loop_reversed field of the LOOPBACK register at offset 0x44, to specify the parts of the CPRI frame that are sent on the loopback path. This parameter is not available if you set the value of Operation mode to TX Simplex or to RX Simplex. Table 2-5: CPRI v6.0 IP Core Advanced Feature Parameters Describes the parameters for customizing the CPRI v6.0 IP core delay calibration features. These parameters appear on the Advanced tab in the CPRI v6.0 parameter editor. Parameter Options Default Setting Parameter Description Enable single-trip delay calibration On Off Off Turn on this parameter to specify that your CPRI v6.0 IP core supports single-trip delay calibration. If you turn on this parameter, your IP core implements single-trip delay calibration only if you connect it according to Adding and Connecting the Single-Trip Delay Calibration Blocks on page Intel provides the required external blocks but you must connect them to the IP core in your design. This parameter is only available in IP core variations that target an Intel Arria 10 device. If you turn off this parameter and also turn off Enable line bit rate auto-negotiation, Enable start-up sequence state machine the transceiver reconfiguration interface is not available. This parameter is available only if you set the value of the Core clock source input parameter to External. Enable round-trip delay calibration On Off Off Turn on this parameter to to specify that your CPRI v6.0 IP core supports round-trip delay calibration. This parameter is available only if you set the value of the Synchronization mode parameter to Master. Getting Started with the CPRI v6.0 IP Core