AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

Transcription

1 AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 AN This application note describes how to implement deterministic latency for Common Public Radio Interface (CPRI) and Open Base Station Architecture Initiative Reference Point 3-01 (OBSAI RP3-01) protocols with transceivers in Stratix IV, HardCopy IV, Arria II GX, and Cyclone IV devices. It also describes the transceiver configuration and clocking scheme to implement deterministic latency. You can create your proprietary CPRI, OBSAI RP3-01, or other interfaces requiring deterministic latency designs based on the implementation descriptions in this application note. The CPRI and OBSAI RP3-01 are point-to-point, high-speed serial interfaces in wireless applications for connecting base station component and remote radio heads. Figure 1 shows various CPRI topologies. Fundamentally, CPRI connects between a radio equipment controller (C) and radio equipment () modules (in single-hop connections). For high bandwidth, multiple s can be chained to a single C (in multi-hop connections), with CPRI links between the modules. The C port is always the master port and the is the slave port for links between C and. For links between s, the port nearest to C is the master. Figure 1. CPRI Topologies Ring C Tree and branch Chain Point-to Point The CPRI and OBSAI RP3-01 specifications have stringent requirements concerning the accuracy of round-trip delay measurements that the system must make. For example, the CPRI specification requires that the round-trip delay measurement accuracy, excluding the cable, must be within ± ns for single-hop and multi-hop connections. In multi-hop connections, the allowed delay uncertainty is accumulated over the number of hops in the connection. To speed development time, Altera offers the complete easy-to-use intellectual property (IP) core for building a CPRI v4.1 that includes the transceiver. f For more information about the Altera CPRI IP solution, refer to the Altera CPRI IP. July 2010 Altera Corporation AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

2 Page 2 Transceiver Support for CPRI and OBSAI RP3-01 Applications Transceiver Support for CPRI and OBSAI RP3-01 Applications The Stratix IV, HardCopy IV, Arria II GX, and Cyclone IV devices include embedded transceivers with deterministic latency features that easily meet the delay accuracy requirements of the CPRI and OBSAI RP3-01 specifications. The deterministic latency features enable you to accurately compute the transceiver datapath latencies when implementing the interfaces. Table 1 indicates the supported data rates for CPRI and OBSAI RP3-01 implementations using transceivers in Stratix IV, HardCopy IV, Arria II GX, and Cyclone IV devices. Table 1. Supported Data Rates for CPRI and OBSAI RP3-01 Implementations (Note 1) CPRI Protocol OBSAI RP3-01 Data Rate (Mbps) Stratix IV HardCopy IV Arria II GX Cyclone IV v v v v v v v v v v v v 3072 v v v v v v v 6144 v v v 768 v v v v 1536 v v v v 3072 v v v v 6144 v v v Note to Table 1: (1) To implement deterministic latency on other proprietary protocols, refer to the respective device family data sheet on the supported data rate. AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 Altera Corporation

3 Implementing Deterministic Latency for CPRI and OBSAI RP3-01 Interfaces Page 3 Implementing Deterministic Latency for CPRI and OBSAI RP3-01 Interfaces This section explains the methods for configuring the transceiver channels with deterministic latency features to implement the CPRI and OBSAI RP3-01 interfaces. Figure 2 shows an overview of CPRI implementation using transceivers. Figure 2. Overview of CPRI Implementation using Transceivers C #1 #2 Transceiver Channel (Master) Tx Transceiver Channel (Slave) Rx (1) (1) Sync Buffer Sync Buffer Transceiver Channel (Master) Tx Transceiver Channel (Slave) Rx (1) Sync Buffer User Logic CPRI PD User Logic PD CPRI PD User Logic Sync Buffer Rx Tx Sync Buffer Rx Tx PD PD Clean-Up PLL Clean-Up PLL Note to table Figure 2: (1) The selected synchronization buffer with phase detector is not required for transceiver implementation with PLL PFD feedback. Use the Deterministic Latency functional mode on the transceiver channels. In this mode, the transmitter channel is configured with no delay uncertainty, and with datapath latency fixed relative to the core fabric interface clock (on the tx_clkout port). The transmitter channel datapath latency can be fixed relative to the transmitter phase-locked loop (PLL) input reference clock (on the pll_inclk port) by enabling the PLL phase frequency detector (PFD) feedback. Using the PLL PFD feedback simplifies port implementations in remote radio heads, effectively eliminating the need for additional logic in the core fabric to implement a synchronization buffer with a phase detector. The requirement for port implementations in remote radio heads without PLL PFD feedback is discussed in Interface Clocking on page 9. The phase detector implementation is discussed in Phase Detector Logic on page In CPRI, PLL PFD feedback is optional for C port implementation. Altera recommends enabling the PLL PFD feedback for port implementation to simplify your interface design. For the receiver, the channel datapath is configured with no latency uncertainty. The latency variation from the link synchronization function (in the word aligner block) is deterministic with the rx_bitslipboundaryselectout port. You can optionally fix the round trip transceiver latency for port implementation in the remote radio head to compensate the latency variation in the word aligner block using the tx_bitslipboundaryselect port. The tx_bitslipboundaryselect port is available to control the amount of bits to be slipped in the transmitter serial data July 2010 Altera Corporation AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

4 Page 4 Implementing Deterministic Latency for CPRI and OBSAI RP3-01 stream. You can optionally use the tx_bitslipboundaryselect port to round the round-trip latency to a whole number of cycles. Using the byte deserializer in the transceiver requires you to create additional logic in the core fabric to determine if the comma byte is received in the lower or upper byte of the word. The delay is dependent on which word the comma byte appears in. The total transmitter and receiver channel datapath latencies are computed as follows: Total transmitter channel datapath latency = transmitter fixed latency + tx_bitslipboundaryselect delay Total receiver channel datapath latency = receiver fixed latency + rx_bitslipboundaryselectout delay + byte deserializer delay Figure 3 shows the transceiver configuration in Deterministic Latency mode. In the receiver channel, the recovered clock is available in the core fabric to capture receiver data from the rx_dataout port. The 1 (single) and 4 (bonded) channel configurations are supported in this mode. Figure 3. Transceiver Configuration in Deterministic Latency Mode Core Fabric Transmitter Channel PCS Transmitter Channel PMA TX Phase Compensation FIFO (1) Byte Serializer 8B/10B Encoder Serializer tx_dataout tx_clkout PCIe hard IP PIPE Interface wrclk tx_clkout[0] rdclk wrclk rdclk /2 Receiver Channel PCS Low-Speed Parallel Clock Local Clock Divider Receiver Channel PMA RX Phase Compensation FIFO (1) Byte Ordering Byte Deserializer 8B/10B Decoder Rate Match FIFO Deskew FIFO Word Aligner Deserializer CDR rx_datain High-Speed Serial Clock rx_clkout /2 Parallel Recovered Clock Parallel Recovered Clock Note to Figure 3: (1) The TX and RX phase compensation FIFOs are configured to register mode. 1 Physical layer functions required for CPRI, OBSAI RP3-01, or other protocols not offered in the transceiver must be implemented in user logics. AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 Altera Corporation

5 Transceiver Channel Instantiation Page 5 Table 2 lists the transceiver configurations for the supported CPRI and OBSAI RP3-01 data rates. Table 2. FPGA Fabric-Transceiver Interface Clock Rates for Supported Line Rates and Channel Widths Protocol Line Rate (Mbps) Stratix IV/HardCopy IV Interface Clock Rates (MHz) Arria II GX Interface Clock Rates (MHz) Cyclone IV Interface Clock Rates (MHz Channel Width (1) Channel Width (1) Channel Width (1) 8/10 16/20 (2) 32/40 (3) 8/10 16/20 (2) 8/10 16/20 (4) CPRI OBSAI RP3 Notes to Table 2: (4) (4) (5) (5) (5) (4) (4) (5) (1) The 8/16/32 bit channel widths are supported with 8B/10B encoder/decoder and the 10/20/40 bits without 8B1/0B encoder/decoder. The ALTGX megafunction automatically enables the 8B/10B encoder/decoder according to the channel width selection. (2) Supported in double-width mode or with the byte serializer/deserializer block. (3) Supported in double-width mode and with the byte serializer/deserializer block. (4) Supported with the byte serializer/deserializer block only. (5) Supported in double-width mode only. Transceiver Channel Instantiation This section describes an example transceiver configuration when using the ALTGX MegaWizard Plug-In Manager to implement the CPRI or OBSAI RP3-01 interface with deterministic latency features. The example assumes the implementation of an slave port (transmit and receive), with the CPRI link running at Gbps using the Stratix IV GX device. The 8B/10B encoder and decoder block is used in this example. Perform the following steps to create the transceiver instantiation for the example: 1. Create a transceiver instance using the ALTGX MegaWizard Plug-In Manager. July 2010 Altera Corporation AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

6 Page 6 Transceiver Channel Instantiation 2. In the General tab, select the following options: a. Which protocol you will be using? Deterministic Latency b. Which subprotocol you will be using? X1 c. What is the operation mode? Transmitter and Receiver d. What is the number of channels? 1 e. What is the deserializer block width? Double f. What is the channel width? 32 g. What is the effective data rate? 6144 h. What is the input clock frequency? For supported transceiver configurations at desired data rates for the CPRI and OBSAI RP3-01 interfaces, refer to Table In the PLL/Ports tab, select Enable PLL phase frequency detector (PFD) feedback to compensate latency uncertainty in the Tx dataout and Tx clkout paths relative to the reference clock option. 1 To select the PLL PFD feedback option, the input clock frequency (provided to pll_inclk) must be the same as the transmitter interface clock frequency (on the tx_clkout port). In this example, the pll_inclk frequency of MHz is the same as the tx_clkout frequency (as listed in Table 2). 1 The PLL PFD feedback is not supported when using the ATX PLL in Stratix IV and HardCopy IV devices. 4. In the Ports/Calibration tab, ensure that the Enable TX Phase Comp FIFO in register mode option is checked. If you uncheck it, the FIFO contributes one or two clock cycles of latency uncertainty. 5. In the Word Aligner tab, select the Use manual word alignment mode option to control the word aligner operation using the rx_enapatternalign port. 1 Only the parameters directly relevant to deterministic latency implementation in the ALTGX MegaWizard Plug-In Manager are listed. f For additional information about the options and settings in the ALTGX MegaWizard Plug-In Manager interface, refer to the ALGX Transceiver Setup Guide in volume 3 of the Stratix IV Device Handbook. Considerations when implementing auto-rate negotiation are discussed in Design Considerations for Auto-Rate Negotiation on page After completing the additional options and settings, click Finish. AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 Altera Corporation

7 Input Reference Clocks and Transmit Side Clock Generation Page 7 Input Reference Clocks and Transmit Side Clock Generation This section explains the input reference clock connections and schemes for the transmit side clock generation. The clocking requirements are different for port implementations in base station component and remote radio heads. For example, the CPRI specification requires any to reuse a transmit clock traceable to C (which can be the receiver recovered clock from the slave port) on its master ports. Figure 4 shows the methods of implementing input reference clocking for CPRI port implementations in C and s (in single-hop and multi-hop connections). Figure 4. Input Reference Clocking in C and s (Note 1) C #1 #2 pll_inclk pll_inclk pll_inclk pll_inclk ALTGX ALTGX ALTGX ALTGX rx_clkout rx_clkout rx_cruclk rx_cruclk rx_cruclk rx_cruclk Clean-Up PLL Clean-Up PLL Note to Figure 4: (1) The input clock ports shown in the diagram are applicable for Stratix IV, HardCopy IV, and Arria II GX devices only. 1 When configured in Deterministic Latency mode, the Cyclone IV GX device provides an input reference clock port for each transmitter PLL and MPLL that clocks the CDR. For example, in a 1 transmitter and receiver channel configuration, the input reference clock is available as the pll_inclk[1:0] port; with the pll_inclk[0] port as the input reference clock for the transmitter PLL, and the pll_inclk[1] port as the input reference clock for the MPLL that clocks the CDR. For the C, use a common input reference clock source for the transmitter PLL and the CDR. In any, send the receiver recovered clock from the slave port to an external clean-up PLL before feeding into the transmitter PLL input reference clocks of the slave port and master port (in a multi-hop connection). The external clean-up PLL is required to reduce the phase noise of the receiver recovered clock. Use the following guidelines when selecting the appropriate external clean-up PLL for port implementation in : Choose an external cleanup PLL device with a sufficient input and output frequency range to handle auto-rate negotiation scenarios in your application. The output clock from the clean-up PLL must meet the TX FCLK phase noise requirement as specified in respective device family data sheets. An example of a suitable clean-up PLL device for such implementation is the CDCL6010 from Texas Instruments. July 2010 Altera Corporation AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

8 Page 8 Input Reference Clocks and Transmit Side Clock Generation Use any of the supported input reference clocking methods to the transmitter PLL and the CDR. f For details about supported input reference clocking methods in each device family, refer to the following documents: Stratix IV Transceiver Clocking chapter in volume 2 of the Stratix IV Device Handbook HardCopy IV GX Transceiver Architecture chapter in volume 3 of the HardCopy IV Device Handbook Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook Cyclone IV Transceiver Architecture chapter in volume 2 of the Cyclone IV Device Handbook The transmitter PLL utilization is dependent on PLL PFD feedback usage. When the feedback is enabled, a PLL is required for each transmitter channel to independently compensate the latency uncertainty in respective channels. For example, a multi-hop implementation requires two PLLs when the PLL PFD feedback is enabled. Implementing a multi-hop with the feedback using Stratix IV, HardCopy IV, and Arria II GX devices requires a transceiver block and both its CMU PLLs. For Cyclone IV devices, a transceiver block and three left PLLs are required to implement a multi-hop with feedback enabled. Additionally, four transmit channels can be bonded together (in 4 channel configurations) to share a PLL with common latency. The bonded channels must all run at the same data rate, which may limit auto-rate negotiation options. Figure 5 shows an example of a transmit side clock generation and CDR clocking for multi-hop using the Cyclone IV GX device with PLL PFD feedback enabled. Figure 5. Transmit Side Clock Generation and CDR Clocking for Multi-Hop using Cyclone IV GX Device with PLL PFD Feedback Enabled (Note 1) MPLL_6 Ch 3 Tx Ch 3 Rx Ch 2 Tx Transceiver Block GXBL0 Ch 2 Rx Ch 1 Tx (Master) Ch 1 Rx (Master) High and Low-Speed Clocks CDR Clocks Ch 0 Tx (Slave) Ch 0 Rx (Slave) MPLL_5 GPLL_1 Note to table Figure 5: (1) The example assumes the channels that implement slave and master ports are running at the same data rate. AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 Altera Corporation

9 Interface Clocking Page 9 Interface Clocking This section explains the core fabric-transceiver interface clocking requirements. The clocking requirements are dependent on PLL PFD feedback usage and core fabric-transceiver interface clock frequency. The PLL PFD feedback enables the transmitter channel datapath latency to be fixed relative to the input reference clock on the pll_inclk port by ensuring a deterministic path between clocks from the tx_clkout and pll_inclk ports. Use the clock from the pll_inclk port to clock core registers sending data to the transmitter channel as shown in Figure 6. Figure 6. Core Fabric-Transmitter Interface Clocking with the PLL PFD Feedback (Note 1) reference clock source tx_reg tx_pipereg pll_inclk D Q D Q tx_datain/tx_ctrlenable ALTGX tx_dataout tx_clkout Note to Figure 6: (1) Registers in the shaded block are optionally used to achieve timing closure. Without the PLL PFD feedback, the transmitter channel datapath latency is fixed relative to the interface clock on the tx_clkout port. Use the clock from the tx_clkout port to clock core registers sending data to the transmitter channel as shown in Figure 7. 1 Without the PLL PFD feedback, delay uncertainty exists between clocks from the tx_clkout and pll_inclk ports. Figure 7. Core Fabric-Transmitter Interface Clocking without the PLL PFD Feedback (Note 1) tx_reg tx_pipereg1 tx_pipereg2 (2) D Q D Q D Q tx_datain/tx_ctrlenable ALTGX tx_dataout RCLK or GCLK PCLK tx_clkout Notes to Figure 7: (1) Registers in the shaded block are optionally used to achieve timing closure. (2) Additional timing constraint is required when the tx_pipereg2 registers are used. July 2010 Altera Corporation AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

10 Page 10 Interface Clocking Depending on the implementations, there may be delay uncertainty transferring data between the receiver and transmitter clock domains. The receiver recovered clock may have an unknown phase relationship with the transmitter clock, resulting in a delay uncertainty that may exceed the required accuracy of the round-trip delay measurement limit for the interface. For example, delay uncertainty occurs in CPRI C port implementation without PLL PFD feedback between clocks from the rx_clkout and tx_clkout ports, and in CPRI slave port implementation without PLL PFD feedback between clocks from the pll_inclk (derived from rx_clkout through the external clean-up PLL) and tx_clkout ports. To overcome this, create an additional logic in the core fabric to implement a synchronization buffer with a phase detector to determine the phase difference. Include the measured delay from the phase difference into the total round-trip latency computation. The phase detector implementation is discussed in Phase Detector Logic on page 11. In certain implementations at high core fabric-transceiver interface clock frequencies, you may not achieve timing closure when interfacing core registers to the transmitter and receiver channels. To meet the core fabric-transceiver interface timing requirement, use the following methods for each configuration scenario: Transmitter Channel with PLL PFD Feedback Pipeline the data with intermediate registers (tx_pipereg in Figure 6) using the clock from the tx_clkout port. Include the following assignment into the.qsf file which assigns non-global routing to the clock from the tx_clkout port: set_instance_assignment -name GLOBAL_SIGNAL OFF -from gxb_rec_fb*tx_clkout_int_wire[0] -to tx_pipereg* gxb_rec_fb is the transceiver instance that provides the tx_clkout port, and tx_pipereg are the registers used to pipeline the data to the transmitter channel. Transmitter Channel without PLL PFD Feedback Pipeline the data with negative-edge triggered intermediate registers (tx_pipereg1 and tx_pipereg2 in Figure 7) using the clock from tx_clkout port. Include the following constraint into the.sdc file, which adjusts the setup requirement between the pipeline registers to transmitter channel. set_multicycle_path -setup -from [get_registers tx_pipereg2*] 2 The tx_pipereg2 are the last stage of pipeline registers interfacing to the transmitter channel. Receiver Channel Include the following constraint into the.sdc file, which adjusts the setup requirement between the receiver channel to capture registers (diagram shown in Figure 8). set_multicycle_path -setup -from [get_registers rx_reg*] 0 The rx_reg are registers used to capture data from the receiver channel. AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 Altera Corporation

11 Phase Detector Logic Page 11 Figure 8. Core Fabric-Receiver Interface Clocking (Note 1) rx_reg (1) Q D rx_dataout/rx_ctrldetect ALTGX rx_clkout Note to table Figure 8: (1) Additional timing constraint is optional to achieve timing closure. For details about the methods described for scenarios on the transmitter channel without PLL PFD feedback and receiver channel, refer to AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode. 1 Use the described methods to meet the core fabric-transceiver interface timing requirement only if you are not able to achieve timing when interfacing core registers to the transmitter and receiver channels. Each stage of pipeline registers adds a latency of one clock cycle to the transmit datapath. Phase Detector Logic This section describes an example of phase detector logic implementation to measure the phase difference between the clock domains. Use the measured phase difference to calculate the total latency of the interface datapath. The phase detection design in this example takes advantage of the PLL dynamic phase shifting feature that is supported in the Stratix IV, HardCopy IV, Arria II GX, and Cyclone IV devices. The logic in the design continuously adjusts the phase of a measurement clock to determine the relative phase offsets between the desired clock domains. Figure 9 shows a block diagram of the phase detection design that measures the phase difference between two clock domains. For example, between clocks from rx_clkout and tx_clkout when used in an slave port without PLL PFD feedback. July 2010 Altera Corporation AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

12 Page 12 Phase Detector Logic Figure 9. Block Diagram of Example Phase Detection Design (Note 1) Phase Detector Phase Detector rx_clkout D Q D Q Q D Q D tx_clkout measure_clk PLL reference_clk PLL Phase Shift State Machine phase of measure_clk Phase Offset Comparator Phase Offset Comparator rx_clkout_phase_offs tx_clkout_phase_offs The following list describes the implementation of each block in Figure 9: PLL The PLL (a core fabric PLL) takes a reference clock and generates a measurement clock with dynamic phase shift capability. The required phase shift step resolution depends on the system needs. A smaller phase shift step resolution provides a higher level of delay accuracy, but requires longer duration to step through all the steps in a clock period. Phase Detector The phase detector comprises a set of pipeline registers that samples the target clock with the measurement clock from the PLL. A phase detector is required for each clock domain that needs measurement. PLL Phase Shift State Machine The state machine controls the continuous phase increments of the measurement clock from the PLL and outputs the phase of the measurement clock. Phase Offset Comparator The comparator finds and reports the phase offsets that match the first rising edge of a target clock from the phase detector output and measurement clock from the PLL. A comparator is required for each clock domain that needs measurement. Using the outputs from the phase detection logic, the latency between two clock domains can be computed. Using the example illustrated in Figure 9, the latency between clocks from rx_clkout and tx_clkout is computed as follows: Latency between clocks from rx_clkout and tx_clkout = phase offsets for rx_clkout phase offsets for tx_clkout phase shift step resolution f For details about implementing dynamic phase shifting in Stratix IV, HardCopy IV, and Arria II GX devices, refer to the PLL Dynamic Phase Shifting in the Quartus II Software section of AN 454: Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices. For Cyclone IV devices, refer to the Implementing PLL Dynamic Phase Shifting in Quartus II Software section in AN 507: Implementing PLL Reconfiguration in Cyclone III Devices. AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 Altera Corporation

13 Design Considerations for Auto-Rate Negotiation Page 13 1 Create additional logic (for example, a synchronization buffer) to facilitate data transfer between the clock domains. Include the additional latencies from the data transfer logics to the total latency calculation. Design Considerations for Auto-Rate Negotiation When implementing auto-rate negotiation capability to the CPRI or OBSAI RP3-01 interfaces, consider the following: Configure the transceiver with the highest data rate intended for the device and use the supported dynamic reconfiguration features to switch to lower data rates. Perform timing closure with the transceiver channel configuration at the highest data rate intended for the port implementation. When using PLL PFD feedback, ensure that the clocks from the pll_inclk and tx_clkout ports have the same frequency at each reconfigured data rate. Take advantage of reconfiguration features on the TX local divider and TX PLL switching in Stratix IV, HardCopy IV, and Arria II GX devices to enable implementing up to four transmitter channels in a transceiver block with independent data rate reconfiguration capability. Take advantage of the reconfiguration feature on the RX local divider in the Cyclone IV device to enable implementing up to four receiver channels in a transceiver block with independent data rate reconfiguration capability that switches between two data rates (in multiples of two). Use bonded ( 4) channel configuration when PLL PFD feedback is required for all four transmitter channels. Create over-sampling logics in the core fabric for auto-rate negotiation on the transmit side. f For details on dynamic reconfiguration implementation when using transceivers, refer to the following documents for the respective device family: Stratix IV Dynamic Reconfiguration chapter in volume 2 of the Stratix IV Device Handbook HardCopy IV GX Dynamic Reconfiguration chapter in volume 3 of the HardCopy IV Device Handbook AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX Devices Table 3 and Table 4 list the example configurations and clocking schemes in various implementation scenarios that require auto-rate negotiation for Stratix IV, HardCopy IV, Arria II GX, and Cyclone IV devices. July 2010 Altera Corporation AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

14 Page 14 Design Considerations for Auto-Rate Negotiation Table 3. Auto-Rate Negotiation Implementation Scenarios using Stratix IV, HardCopy IV, and Arria II GX Devices (Part 1 of 2) Scenarios Channel Utilization Reconfiguration Option Details Dedicated CMU PLL per channel Shared CMU PLL (without PLL PFD feedback path support) Up to two independent 1 duplex channels in a transceiver block, with each channel using a dedicated CMU PLL Up to four independent 1 duplex channels in a transceiver block, with the channels sharing one or two CMUs Channel and CMU PLL reconfiguration Channel and CMU PLL reconfiguration Perform negotiation to the desired data rate by reconfiguring the specific receiver channel and CMU PLL (affecting the transmitter only). Supports PLL PFD feedback for each transmitter channel. Ensure that the input reference clock frequency is the same as the clock from the tx_clkout port at each reconfigured data rate. Perform negotiation to the desired data rate by reconfiguring the specific receiver channel. Data rate division in TX Perform negotiation to related data rates (in multiples of /1, /2 or /4 of each other) by reconfiguring the TX local clock divider of the specific transmitter channel. For example: From Mbps to Mbps, or Mbps From 6144 Mbps to 3072 Mbps Enable the channels to share the same CMU PLL and perform negotiation independently without affecting each other while listening to the same CMU PLL. Channel reconfiguration with TX PLL select Perform negotiation to the unrelated data rates (not in multiples of /1, /2, or /4 of each other) by reconfiguring the specific transmitter channel to select clocks from another CMU PLL. For example: From 6144 Mbps to Mbps From Mbps to 3072 Mbps Uses two CMUs one with the initial line rate clock settings and the other with the negotiated lower line rate clock settings. Reconfiguration at the specific transmitter channel does not affect the other channels that listen to either of the CMU PLLs. Use with Data rate division in TX reconfiguration option for greater negotiation flexibility. For example: From 6144 Mbps to Mbps, then to 3072 Mbps From Mbps to 3072 Mbps, then to Mbps AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 Altera Corporation

15 Design Considerations for Auto-Rate Negotiation Page 15 Table 3. Auto-Rate Negotiation Implementation Scenarios using Stratix IV, HardCopy IV, and Arria II GX Devices (Part 2 of 2) Scenarios Channel Utilization Reconfiguration Option Details Shared CMU PLL (with PLL PFD feedback support) Four duplex channels bundled in ( 4) bonded mode, with all channels sharing CMU0PLL Channel and CMU PLL reconfiguration Implement over-sampling in your user logic Perform negotiation to the desired line rate by reconfiguring the specific receiver channel. Do not implement over-sampling logic on the receiver datapath. Implement variable over-sampling (sending the same bit multiple times) in the user logic at each transmitter path with the CMU0 PLL clock settings at the highest data rate intended for the device. Implement 8B/10B encoding in the user logic selects 10/20/40 bits channel width to bypass the 8B/10B encoder in transceiver. Perform negotiation to the data rates that are multiples of each other (/2, /4, or even /8) by enabling the appropriate over-sampling path in the user logic. Negotiation at a specific transmitter channel does not affect other channels in the bundle. Supports the PLL PFD feedback path for each transmitter, compensating transmitter uncertainty in the four bonded channels at the same time to the CMU0 PLL. July 2010 Altera Corporation AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

16 Page 16 Design Considerations for Auto-Rate Negotiation Table 4. Auto-Rate Negotiation Implementation Scenarios using Cyclone IV Devices Scenarios Dedicated PLLs per channel Shared PLL (with the PLL PFD feedback support) Channel Utilization Up to two independent 1 duplex channels in a transceiver block, using two PLLs for each channel (one PLL for transmitter and another for receiver) with PLL PFD feedback, and one PLL for each channel without PLL PFD feedback (transmitter and receiver share the same PLL) Four duplex channels bundled in ( 4) bonded mode, with all the transmitter channels sharing one PLL and receiver channels listening to another PLL Reconfiguration Option Details PLL reconfiguration Perform negotiation to the desired data rate by reconfiguring the specific PLL that clocks the target transmitter or receiver channel, or both, when transmitter and receiver listens to the same PLL. Supports PLL PFD feedback for each transmitter channel. RX local divider reconfiguration Implement over-sampling in your user logic Perform negotiation to data rates that are in multiples of /2 of each other by reconfiguring the RX local divider at the specific receiver channel. For example: From Mbps to Mbps Reconfiguration at the specific receiver channel does not affect the other receiver channels in the bundle. Do not implement over-sampling logic on the receiver datapath. Implement variable over-sampling (sending the same bit multiple times) in the user logic at each transmitter path with the PLL clock settings at the highest line rate intended for the device. Implement 8B/10B encoding in the user logic selects 10/20 bits channel width to bypass the 8B/10B encoder in the transceiver. Perform negotiation to the line rates that are in multiples of /2 of each other by enabling the appropriate over-sampling path in the user logic. Negotiation at a specific transmitter does not affect the other channels in the bundle. Supports the PLL PFD feedback path for each transmitter, compensating transmitter uncertainty in the four bonded channels at the same time to the PLL. AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 Altera Corporation

17 Summary Page 17 Summary In this application note, transceiver configuration and clocking schemes to implement deterministic latency for CPRI and OBSAI RP3-01 protocols with transceivers in Stratix IV, HardCopy IV, Arria II GX and Cyclone IV devices are discussed. You can create your proprietary CPRI, OBSAI RP3-01, or other interfaces requiring deterministic latency designs based on the described implementations. Document Revision History Table 5 lists the revision history for this application note. Table 5. Document Revision History Date Revision Changes Made July Initial release. July 2010 Altera Corporation AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

18 Document Revision History 101 Innovation Drive San Jose, CA Technical Support Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.