LTS-20 Serial Adapter and PSG-20 User s Guide

Transcription

1 LTS-20 Serial Adapter and PSG-20 User s Guide Version 2 I ECHELON Corporation OlC

2 No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Echelon Corporation. Echelon, LON, LONWORKS, LonTalk, Neuron, LONMARK, 3150, 3120, LonPoint, the Echelon and LonMark logos, and LonBuilder are trademarks of Echelon Corporation registered in the United States and other countries. LonMaker is a trademark of Echelon. Other names may be trademarks of their respective companies. Printed in the United States of America. Copyright by Echelon Corporation. Echelon Corporation

3 Preface This document describes how to use an LTS-20 LonTalk Serial Adapter and a host processor with an EIA-232 (formerly RS-232) serial interface with a LONWORKS@ network. LTS-20 User s Guide

4 Audience This user s guide provides specifications and instructions for LTS-20 users. Content This manual provides detailed information LTS-20 and PSG-20. l l l l l l l l l l l l l Chapter 1 introduces the LTS-20. Chapter 2 provides an overview of the LTS-20. about the hardware and software for the Chapter 3 describes product development with the LTS-20 module. Chapter 4 describes EM1 and ESD issues for LTS-20 and PSG-20 modules. Chapter 5 describes the LTS-20 software. Chapter 6 discusses creating SLTA network driver. Chapter 7 discusses using the DOS network driver. Chapter 8 discusses using the UNIX network driver. Chapter 9 discusses using the LTS-NSI mode. Chapter 10 discusses the LTS-20 MIP mode software. Chapter 11 describes using the drivers and link manager with LTS-20 NSI mode. Chapter 12 discusses using the DOS driver with LTS-20 MIP mode. Chapter 13 explains how to create an LTS-20 MIP mode driver. l Chapter 14 discusses initialization and installation. l l l l l l l Chapter 15 explains how to use the LST-20 with a modem. Chapter 16 discusses using the host connect utility with the LTS-20 MIP mode. Chapter 17 details using a programmable serial gateway. Chapter 18 details modem troubleshooting. Appendix A lists the default communications parameters for LTS-20-based products. Appendix B describes the Windows DLL files supplied with the LTS-20. Appendix C includes a copy of the software license agreements. ii Preface

5 Related Manuals Web Access The following Echelon documents are suggested reading for more information: TheLNSm DDE Server User s Guide is a manual for developers on how to create user interface, monitoring, and control applications that communicate with LONWORKS networks from computers running Microsoft Windows. The LonMakef for Windows Integration Tool User s Guide is a manual for users on how to install networks using the integration tool. The LonBuilder@ User s Guide describes how to develop LONWORKS applications with the LonBuilder Developer s Workbench. The NodeBuilderm User s Guide describes how to develop LONWORKS applications with the NodeBuilder Development Tool. The LONWORKS Host Application Programmer s Guide describes how to write a host application that can be used with a serial adapter. The Neuron Chip Data Book describes the LonTalk message formats that can be used with a serial adapter. It also describes the network management and network diagnostic messages that can be sent with such an adapter. Engineering bulletins and data sheets supporting this product are available on the Echelon Web site. General information regarding Echelon, its business, and its products also are located on the site at The Developer s Toolbox located at the Web site includes drivers for the LTS-20. LTS-20 User s Guide

6 Preface

7 Contents Preface Audience Content Related ManuaIs Web and FTP Access ii ii LTS-SO Introduction l-l 2 LTS-20 Overview 2-1 Mechanical Description 2-2 Power Requirements 2-5 Power Supply Decoupling and Filtering 2-5 Low Voltage Protection 2-5 Electrical Interface 2-5 NSI/MIP Mode Jumper R2 2-7 Autobaud 2-7 Baud(2..0) 2-7 CFGO 2-7 CFGl 2-8 CFG2 2-8 CFG3 2-8 CLK OUT 2-8 CP(4..0) 2-8 -CTS 2-8 -DCD IN 2-8 -DCD OUT 2-9 DCE 2-9 -DSR 2-9 -DTR 2-9 PKT 2-9 -RESET 2-9 -RI IN RI OUT RTS 2-10 SERIAL IN 2-10 SERIAL OUT SERVICE TEST 2-11 XID(4..0) 2-11 LTS-20 Software Configuration Options Developing an SLTA with the LTS-20 Module Overview Using Predefined Transceivers TPT/XF-78 and TPT/XF-1250 Twisted Pair Transceivers FTT-1OA Free Topology and LPT-10 Link Power Transceivers LTS-20 User s Guide

8 PLT Power Line Transceiver 3-6 Using Custom Transceivers LTS-20 Design Issues EM1 Design Issues Designing Systems for EMC (Electromagnetic Compatibility EMC Design Tips ESD Design Issues Designing Systems for ESD Immunity The LTS-20 Software 5-l Software Overview 5-2 Installing LTS-20 Software 5-2 Installing the Windows DLL Software Creating an LTS-20 MIP Mode Network Driver 6-1 Purpose of the Network Driver 6-2 Example Network Drivers 6-2 Implementing an SLTA Network Driver 6-2 Network Interface Protocol 6-5 Link Layer Protocol 6-5 ALERT/ACK Link Protocol 6-5 Buffered Link Protocol 6-7 Transport Layer Protocol 6-8 SLTA Timing Data 6-9 Downlink Byte-to-Byte Receive Timeout 6-10 Uplink Message Life 6-10 ACK/NACK Receive Timeout 6-10 Uplink Timeout Message Retry Count 6-10 Session Layer Protocol 6-10 Downlink Buffer Request Protocol 6-10 Uplink Flow Control Protocol 6-12 Presentation Layer Protocol Using the DOS Network Driver Installing the SLTA Network Driver for DOS Buffer Options Serial Bit Rate Options DOS Device Options Timing Options Network Interface Protocol Options Calling the Network Driver from a Host Application Using the SLTA Driver under Microsoft Windows 7-l Using the UNIX Network Driver 8-l Installing the SLTA Network Driver for UNIX 8-2 Calling the Network Driver from a Host Application 8-2 ldv-open0 8-3 ldv-read0 8-3 ldv-write0 8-3 vi Preface

9 ldv-post-events0 ldv-close0 9 Using the LTS-20 NSI Mode Software LTS-20 NSI Mode Software Overview Windows 95 and Windows NT Software Installation Procedure Windows 95,98, and NT Software Installation Instructions 10 The LTS-20 MIP Mode Software LTS-20 MIP Mode Software Overview Installing the LTS-20 MIP Mode Adapter Software Installing the Windows 3.1x DLL Software Other Drivers a l Using the Windows 95 or NT Driver and SLTALink Manager with LTS-20 NSI Mode Software Overview Establishing a Communications Line for Dialing in to a Network 11-l Establishing a Communications Line for Calls Dialed Out to the PC 11-5 Establishing Remote and Local Network Sites 11-6 SLTALink Configuration Script Formats 11-7 Example 11-8 Name of Link 11-8 Remote Identifier 11-8 Link Type 11-9 Configuring the Modem Line 11-9 SLTA Password 11-9 Invoking an Application 11-9 Enabling a Callback Configuration Security Password Enable Callback Timers Hangup Timer, minutes Guard Time, seconds Modem Settings Initialization String Dial Prefix Clear EE Poll on Apply Dial Directories Auto-dialout Configuration NV Connect NSI Connect Diagnostics The SLTALink Manager Programmatic Interface Using the DOS Stub Driver Characteristics of a Well-Designed System Call Initiation Dial-In to the Network Only Dial-Out to the Remote PC Only LTS-20 User s Guide vii

10 Dial-In/Dial-Out Callback Call Termination Monitoring: Application Termination Strategy Monitoring: Missing Messages after a Dial-Out Monitoring: LNS Application Design Issues Good Practices/Schemes that Work 12 Using the DOS Driver with LTS-20 MIP Mode Installing the LTS-20 MIP Mode Driver for DOS Buffer Options Serial Bit Rate Options DOS Device Options Timing Options Network Interface Protocol Options Calling the Network Driver from a Host Application Using the LTS-20 MIP Mode under Microsoft Windows 3.1x, Creating an LTS-20 MIP Mode Driver 13-1 Purpose of the Network Driver 13-2 Example Network Drivers 13-2 Implementing an LTS-20 MIP Mode Network Driver 13-2 Network Interface Protocol 13-5 Link Layer Protocol 13-5 ALERT/ACK Link Protocol 13-5 Buffered Link Protocol 13-7 Transport Layer Protocol 13-8 LTS-20 Timing Data Downlink Byte-to-Byte Receive Timeout Uplink Message Life ACK/NACK Receive Timeout Uplink Timeout Message Retry Count Session Layer Protocol Downlink Buffer Request Protocol Uplink Flow Control Protocol Presentation Layer Protocol Initialization and Installation Initializing an LTS-20-based Node Installing an LTS-20-based Node on a Network Installing with LNS, the LonMaker for Windows Integration Tool, or the LNS DDE Server Installing with the LonBuilder Tool Installing an LTS-20-based Node with LonManager API, the DOS-based LonManager LonMaker for DOS Installation Tool, or the LonManager DDE Server Preface

11 15 Using the LTS-20 with a Modem Overview LTS-20 Connection States Command Set Assumptions Translated Characters DTE Connections Network Management Messages EEPROM String Pool Management Product Query Send Modem String Modem Response Query Connection Status Query Install Directory Entry Dial from Directory Hang-up Install Password Install Modem Configuration String Install Hangup String (MIP Mode only) Install Dial Prefix Install Hangup Timer Configure Modem Request/Release SLTA Clear EEPROM Pool Install NVConnect (NSI mode only) Install NSIConnect (NSI mode only) Install CallbackEnable (NSI mode only) Report SLTAEE (NSI mode only) Modem Compatibility Remote LTS-20 Deployment Configuration Software Setup SLTALink Manager 16 Using the Host Connect Utility with the LTS-20 MIP Mode HCU Usage Theory of Operation Usage Examples Suggested Modem Configurations Status and Error Reporting 17 Using a Programmable Serial Gateway Creating a Serial Gateway LTWPSG History Programmable Serial Gateway Hardware Resources Developing a PSG Application with the NodeBuilder Development Tool PSG Software Installation PSGBOR.DTM Firmware Library Support Usage LTS-20 User s Guide ix

12 Code Development and Debugging 17-7 PSG.LIB Functions 17-7 Advanced Applications 17-9 UART Registers PROM/FLASH Specification Differences Between PSG-10 and PSG Porting PSG-10 Code to the PSG Modem Troubleshooting Troubleshooting LTS-20-based Node and Modem Do Not Answer or Pick Up Modems Will Not Connect LTS-20-based Node-to-Host Link Fails Completely LTS-20-based Node-to-Host Link Fails Partially LTS-20-based Node Sends Modem Configuration String, But It Has No Effect Appendix A Communications Parameters A-l Appendix B Windows DLL Files for LTS-20 MIP Mode B-l ldv-close B-2 ldvget-version B-3 ldv-open B-4 ldv-read B-5 ldv-write B-6 Appendix C Software License Agreements C-l X Preface

13 LTS-20 Introduction The LTS-20 LonTalk Serial Adapter Module is a network interface that enables any host processor with an EIA-232 serial interface to connect to a LONWORKS network. A replacement for the previous generation LTS-10 Core Module, the LTS-20 is supplied with both Network Services Interface (NSI) firmware to support LNS - the standard LONWORKSB network operating system - as well as Microprocessor Interface Program (MIP) firmware to support older API-based tools. The LTS-20 extends the reach of LONWORKS technology to a variety of hosts, including desktop, laptop, and palmtop PCs, workstations, embedded microprocessors, and microcontrollers. LTS-20 User s Guide l-l

14 The LTS-20 enables the attached host to act as an application node on a LONWORKS network. When used with a PC host and the LonMaker for Windows Integration Tool (or an older generation tool using the LonManager API), or LNS DDE Server, the LTS-20 can also be used to build sophisticated network management, monitoring, and control tools for LONWORKS networks. The LTS-20 is a direct replacement for Echelon s model LTS-10 module. The two modules are pin-for-pin compatible and also have identical physical dimensions. The LTS-20 is equipped with an NSI to enable it to be used in conjunction with LNS - the standard operating system for LONWORK~ control networks. By default the LTS-20 is shipped with the NSI mode enabled. A jumper is provided which, when cut by the customer, disables the NSI and enables the MIP mode for emulating the behavior of the LTS-10. Intended to be embedded within an OEM s product, the LTS-20 and its associated interface logic can be used to connect to a host through a pair of modems and the telephone network. This allows the monitoring, control, or network management application computer to be remote from the network. A node using the LTS-20, associated logic, and modems can initiate a telephone call to a remote host computer, and can be set up to answer incoming calls from a remote host. A Connectivity Starter Kit (Model ) should be ordered for initial development with an LTS-20. The kit includes both software and documentation. The software includes network drivers for Windows@ 95,98, and NT. Supplied as a single in-line module (SIM) form-factor building block, the LTS-20 can be used to create custom serial interfaces to a wide range of network media. l-2 Introduction

15 2 LTS-20 Overview This chapter provides an overview of the model LTS-20 LonTalk Serial Adapter Module. LTS-20 User s Guide 2-l

16 Mechanical Description The LTS-20 Module consists of a 67mm by 28mm by 7mm (2.65 by 1.1 by 0.3 ) module with the core electronics and firmware required to implement a serial LonTalk Adapter. The module is attached to a motherboard using a 40-position, inch spacing SIM socket. Two compatible sockets are available: l l Molex SIM Vertical Connector with metal latches, Centerline Single Row Connector - 40 position. AMP , SIM II Right Angle Connector, Centerline Single Row Connector - 40 position. For information about Molex parts call +l or fax +l Within North America, AMP drawings can be obtained via FAX using the free AMP FAX service. Call l from a touchtone phone and order customer prints using the AMP part number. Additional information on the connectors is available in AMP application note number AMP and reliability information is available in AMP product specification Figure 2.1 illustrates the mechanical footprint for the module and vertically mounted socket. Figure 2.2 shows the recommended PCB pad layout for the vertically mounted socket. Figures 2.3 and 2.4 provide the same information for the right-angle socket. Decisions about component placement on the motherboard must consider electromagnetic interference (EMI) and electrostatic discharge (ESD) issues discussed in Chapter 4 of this document. 2-2 LTS-20 Overview

17 3.17mm ~ LTS-20 Footprint when using Molex Part Number (Component Side, Vertical SIM Mounting) 74.!xh-ml Notes: 1. Dimensions in mm (inches). 2. Tolerances +.13mm (0.0005) 3. Components standing higher that 3.81 mm(.l5) should not be closer than 12.4mm (0.5) to this edge of the socket to allow clearance to insert the module. 4. Allow 33.02mm (1.3) clearance above PCB over the footprint area. Additional clearance required to insert the module. 5. Socket dimensions are subject to change. Contact Molex for the most current information. 6. Alternate AMP part is l. Figure 2.1 LTS-20 Vertical Socket Mechanical Footprint LTS-20 User s Guide 2-3

18 LTS-20 PC6 Footprint when using AMP Part Number O (Component Side, Horizontal Mounting) 4.32mm 9 E&k& Outline 74.93mm f mm (0.670) _i g mm fvbdule &erhang Notes: 1. Dimensions in mm (inches). 2. Tolerances *.13mm (0.0005) 3. Do not position components in the overhang region. 4. Allow 12.7mm (0.5) clearance above PCB over the entire footprint area. Additional clearance required during assembly to insert the module. 5. Socket dimensions are subject to change. Contact AMP for the most current information. Figure 2.2 LTS-20 Horizontal Socket Pad Layout 2-4 LTS-20 Overview

19 Power Requirements The modules require a +5VDC *lo% power source with a minimum of 15OmA of current capacity. Power Supply Decoupling and Filtering The design for the module power supply must consider filtering and decoupling requirements of the module. The power supply filter must prevent noise generated by the core module from conducting onto external wires. Switching power supply designs must also consider the effects of radiated EMI. The modules require a clean power supply to prevent RF noise from conducting onto the network through active drive circuits. Power supply noise near the network transmission frequency may degrade network performance. The modules include 2.2pF and O.lpF power supply bypass capacitors close to pins 1,9, and 31. In general, high-frequency decoupling capacitors valued at O.lpF or O.OlpF placed near pins 1,9, and 31 on the motherboard are necessary to reduce EMI. L 0 w Voltage Pro tee tion It is necessary to include a low voltage indicator (LVI) circuit on the module motherboard to drive the -RESET line of the core module. See the Neuron C~QJ Data Book for details. Failure to include such protection may cause data corruption to configuration data maintained in EEPROM on the module s Neuron Chip. In the sample circuit of figure 3.1, protection is provided via a Motorola MC Electrical Interface The pinout of the modules is shown in table 2.1. LTS-20 User s Guide 2-5

20 Table 2.1 Pinout of the LTS-20 Name Function Pin # AUTOBAUD Automatic serial bit rate detect enable input 19 BAUD0 Serial bit rate 0 input (LSB) 16 BAUD1 Serial bit rate 1 input 15 BAUD2 Serial bit rate 2 input (MSB) 21 CFGO EIA-232 interface option (1 = 8 wire, 0 = 3 wire) 17 CFGl Network Disable (1 = disable after reset) 14 CFG2 Modem Support (1 = remote host; 0 = local host) 20 CFG3 Interface link protocol (1 = Buffered; 0 = ALERT/ACK) 18 CLK OUT Neuron Chip CLK2 output 11 CPO Network communication port 0 6 CPl Network communication port 1 5 CP2 Network communication port 2 4 CP3 Network communication port 3 7 CP4 Network communication port 4 3 -CTS EIA-232 clear to send output from UART 36 -DCD IN EIA-232 serial data carrier detect input (DTE only) 35 -DCD OUT EIA-232 serial data carrier detect output (DCE only) 40 DCE Indicates whether connected as DCE 22 -DSR EIA-232 data set ready output from UART 38 -DTR EIA-232 data terminal ready input to UART 37 PKT Packet transmitted output 13 -RESET Neuron Chip reset input and output 8 -RI IN EIA-232 ring indicator input (DTE only) 33 -RI OUT EIA-232 ring indicator output (DCE only) 34 -RTS EIA-232 request to send input to UART 39 SERIAL IN EIA-232 serial data input to UART 26 SERIAL OUT EIA-232 serial data output to UART 27 -SERVICE Neuron Chip service pin input and output 12 -TEST Manufacturing test pin, tie to Vcc in final product 30 XIDO Transceiver ID 0 input (LSB) 25 XIDl Transceiver ID 1 input 23 XID2 Transceiver ID 2 input 29 XID3 Transceiver ID 3 input 28 XID4 Transceiver ID 4 input 24 vcc +5VDC input 1,9,31 GND Ground 2, 10, LTS-20 Overview

21 NSI/MIP MODE JUMPER R2 The NSI/MIP jumper R2 (a 2200 resistor) determines the start-up mode of the module. The module is shipped in the NSI mode, with the jumper intact. Cutting jumper R2 disables the NSI mode and enables the MIP mode (for emulating the LTS-10 module). DO NOT cut the jumper while the module is powered - only cut the jumper with the module unpowered. Observe appropriate ESD protection suitable for CMOS devices when handling the module or cutting jumper R2. To ensure reliable operation, RJ should be removed in its entiretv and not simnlv cut at one end. Figure 2.3 R2Jumper AUTOBAUD BAUD[2..0] CFGO The AUTOBAUD input signal enables automatic baud rate detection on the LTS-20 as described in Chapter 7. The input is a floating CMOS input and must be asserted high to enable automatic baud rate detection or be asserted low to disable automatic baud rate detection. The BAUD[2..01 input signals set the EIA-232 serial bit rate on the LTS-20 module as described in Chapter 7 and summarized in Table 2.2. The inputs are not used when AUTOBAUD is enabled. The inputs are floating CMOS inputs and must be asserted high to select a 1 and asserted low to select a 0. Table 2.2 LTS-20 Baud Rate Inputs BAUD[2..0] E Serial Bit Rate 14,400 bps 1,200 bps 2,400 bps 9,600 bps 19,200bps 38,400 bps 57,600 bps 115,200bps The CFGO input signal selects a full B-wire interface or 3-wire interface for the LTS-20 module as described in Chapter 7. The input is a floating CMOS input and must be asserted high to select a full B-wire interface or asserted low to select a 3-wire interface. LTS-20 User s Guide 2-7

22 CFGl The CFGl input signal enables or disables network communications after reset for the LTS-20 module as described in Chapter 7. The input is a floating CMOS input and must be asserted high to disable network communications after reset or asserted low to enable network communications after reset. CFG2 The CFG2 input signal controls the use of the LTS-20 module with a modem as described in Chapter 12. The input is a floating CMOS input and must be asserted high to enable modem support for a remote host or asserted low to enable local host support. CFG3 CLK OUT CP(4..0) -CTS The CFG3 input signal controls the network interface link protocol used between the LTS-20 module and a local host as described in Chapter 11. The input is a floating CMOS input and must be asserted high to select the buffered link protocol or asserted low to select the ALERT/ACK link protocol. The CLK OUT output signal is driven by the CLK2 pin of the core module Neuron Chip. It can drive one HCMOS load, and can be used to interface to the FTT-1OA Free Topology Transceiver or the LPT-10 Link Power Transceiver. The CP[4..0] signals are connected to the CP[4..0] pins of the core module Neuron Chip. The function of these pins is described in the Neuron Chip Data Book. EIA-232 clear to send output when the LTS-20 is connected as a DCE device. This output should be used as the EIA-232 request to send (-RTS) output when the LTS-20 is connected as a DTE device. The output is driven by the core module UART and must be connected to an EIA-232 driver if EIA-232 voltage levels are required, or can be ignored for a 3-wire serial interface. -DCD IN EIA-232 data carrier detect input when the LTS-20 is connected as a DTE device. This input is not used when the LTS-20 is connected as a DCE device. This input is not used by the firmware when connected to a local host, and is used to detect incoming calls when used with a remote host (i.e. when CFG2 is set to the Remote Host state). The input is connected to the core module UART and must be externally connected to an EIA-232 receiver if EIA-232 voltage levels are used, or should be connected to ground for a 3-wire serial interface. 2-8 LTS-20 Overview

23 -DCD OUT EIA-232 data carrier detect output when the LTS-20 is connected as a DCE device. This output is not used when the LTS-20 is connected as a DTE device. This output is always asserted high by the firmware. The output is driven by the core module UART and must be connected to an EIA-232 driver if EIA-232 voltage levels are required, or can be ignored for a 3-wire serial interface. DCE The input is a floating CMOS input. It is not used by the firmware. It should be pulled high or low by the motherboard. -DSR EIA-232 data set ready output when the LTS-20 is connected as a DCE device. This output should be used as the EIA-232 data terminal ready (-DTR) output when the LTS-20 is connected as a DTE device. This output is always asserted high by the firmware when used with a local host and is asserted low for 500ms to hang up the modem when used with a remote host (i.e., when CFG2 is set to the Remote Host state). The output is driven by the core module UART and must be connected to an EIA-232 driver if EIA-232 voltage levels are required, or can be ignored for a 3-wire serial interface. -DTR EIA-232 data terminal ready input when the LTS-20 is connected as a DCE device. This input should be used as the EIA-232 data set ready (-DSR) input when the LTS- 20 is connected as a DTE device. The input is connected to the core module UART and must be externally connected to an EIA-232 receiver if EIA-232 voltage levels are used, or should be externally connected to ground for a 3-wire serial interface. PKT -RESET The PKT output signal is asserted high when interface buffers are passed from the host to LTS-20 module. PKT can be used to drive an activity LED, as in the example circuit shown in figure 3.1. The output is controlled by writing to the memory mapped I/O at location OxE7EOwrite 0x01 to drive the signal high, and 0x00 to drive the signal low. PKT can source 2mA with VCH 2 2.4V, and it can sink 8mA with VCL I 0.45V. The -RESET signal is connected to the -RESET pin of the core module Neuron Chip. The function of the -RESET pin is described in the Neuron Chip Data Book. The core modules include a reset circuit as shown in figure 2.5. The -RESET signal should be driven (open collector or open drain only) by a low voltage protection circuit (LVI) on the core module motherboard as described under Low Voltage Protection earlier in this chapter. The use of an LVI is critical for reliable operation of the LTS-20. LTS-20 User s Guide 2-9

24 Figure 2.4 LTS-20 Reset Circuit -RI IN -RI OUT -RTS SERIAL IN SERIAL OUT EIA-232 ring indicator input when the LTS-20 is connected as a DTE device. This input is not used when the LTS-20 is connected as a DCE device. The output is connected to the core module UART and must be externally connected to an EIA-232 receiver if EIA-232 voltage levels are used, or should be externally connected to ground for a 3-wire serial interface. EIA-232 ring indicator output when the LTS-20 is connected as a DCE device. This output is not used when the LTS-20 is connected as a DTE device. This output is always set to the inactive state by the firmware. The output is driven by the core module UART and must be connected to an EIA-232 driver if EIA-232 voltage levels are required, or can be ignored for a 3-wire serial interface. EIA-232 request to send input when the LTS-20 is connected as a DCE device. This input should be used as the EIA-232 clear to send (-CTS) output when the LTS-20 is connected as a DTE device. The input is connected to the core module UART and must be externally connected to an EIA-232 receiver if EIA-232 voltage levels are used, or should be externally connected to ground for a S-wire serial interface. EIA-232 received data (RXD) input. The input is connected to the core module UART and must be externally connected to an EIA-232 receiver if EIA-232 voltage levels are used. EIA-232 transmitted data (TXD) output. The output is driven by the core module UART and must be connected to an EIA-232 driver if EIA-232 voltage levels are required LTS-20 Overview

25 -SERVICE -TEST XID(4..0) The -SERVICE signal is connected to the -SERVICE pin of the module s Neuron Chip. The function of the -SERVICE pin is described in the Neuron Chip Data Book. The internal pullup resistor for the service pin is enabled. A service LED will reflect the firmware status: blinking means that the module is unconfigured, offmeans that it is configured, and on steadily means that it is applicationless. If the service LED is on steadily, a critical error has been detected by the firmware. A push-button connected to this pin may be used during installation to broadcast the 4%bit Neuron ID on the network. Typical applications do not require debounce conditioning of momentary push buttons attached to the -SERVICE pin. The software response time associated with this input is long enough to effectively provide a software debounce for switches with a contact bounce settling time as long as 20 milliseconds. The -TEST input signal is used to put an LTS-20 module in test mode during manufacturing test. Use of this signal is described in the LTSMFT.NC Neuron C file in the manufacturing test directory (MFT) of the software. This signal should be tied high in a shipping, production-level node. The LTS-20 comes preconfigured with many common LONWORKS transceiver parameters. The XID[4..01 input signals specify a transceiver identification (ID) to select the appropriate transceiver type. The transceiver ID inputs eliminate a manufacturing step by automatically configuring the LTS-20 for most transceivers. A special transceiver ID is reserved for programming any custom transceiver type. This value causes the communication port pins to be configured as all inputs so that no line will be driven by both the transceiver and LTS-20 Neuron Chip before the chip can be properly configured. The LTS-20 firmware reads the transceiver ID inputs on both power-up and on reset. If it is being powered-up for the first time, or if the transceiver ID is different from the last time it was powered-up, the parameters specified in table 2.3 are loaded. If it is being repowered-up, and the transceiver ID is not 30, the LTS-20 firmware compares the network bit rate and input clock for the specified transceiver to the current transceiver parameters. If these parameters don t match, then all transceiver parameters are reinitialized. This allows a network management tool to change parameters, such as the number of priority slots, without the new values being overwritten by the LTS-20 firmware. LTS-20 User s Guide 2-l 1

26 Table 2.3 LTS-20 Transceiver IDS ID I XlD[4..0] I Name Media Bit Rate (bps) TPiXF-78 Isolated Twisted Pair 78k TP/XF-1250 Isolated Twisted Pair 1.25M FT-10 Free Topology, Link Power 78k TP/RS RS-485 Twisted Pair 39k PL-10 Power Line (FCC-band) 10k TP/RS RS-485 Twisted Pair 625k TP/RS RS-485 Twisted Pair 1.25M TP/RS RS-485 Twisted Pair 1 78k PL90A 1 Power Line (narrow band A-band) 3.6k PL-POC Power Line (C-band - CENELEC) 5k PL90N Power Line (C-band - non-cenelec) 5k PL-30 Power Line (A-band) 2k FO-10 Fiber Optic 1.25M DC-78 Direct Connect 78k DC-625 Direct Connect 625k DC-l 250 Direct Connect 1.25M / 30* Ill110 Custom Custom Notes: Type 30 can be used for any transceiver type; the communications port is initially defined as all inputs to prevent circuit conflicts. When using type 30, the transceiver parameters must be reprogrammed by establishing communication over the serial port, as described in the next chapter. See Appendix A for a listing of the communications parameters for each transceiver type. LTS-20 Software Configuration Options The types of messages passed between the host and the LTS-20 are determined by EEPROM configuration options. These options are described under Network Interface Configuration Options in Chapter 3 of the LONWORKS Host Application Programmer s Guide. The Network Disable Option affects whether or not the LTS-20 can send and receive application messages. This option is described in Chapter 7 under Initializing an SLTA. The buffer configuration parameters can be changed at any time by sending Write Memory network management messages to the LTS-20, either from a host (using local network management messages) or over the network from a network management tool. See the Neuron Chip Data Book, Appendix A, for details of the data structures within the Neuron Chip that control the partitioning of RAM for buffers LTS-20 Overview

27 The following table summarizes the memory usage of the default configuration. The table also lists the maximum size of the buffer memory pool. If the LTS-20 is configured to use more bytes than are available in the pool, it will most likely crash or behave erratically since the remaining RAM is used by the system firmware. The default MIP mode EEPROM configuration settings for the LTS-20 are as follows: I Configuration Parameters I Default Setting I I Initial State I Unconficlured Explicit addressing Network variable processing Program ID string Enabled Host Selection 1 SLTA These values apply to LTS-20 Neuron Chip application version 7 only These values are fmed and cannot be modified The amount of RAM memory available for buffers in the MIP mode is bytes. This total includes both on-chip and off-chip RAM. When calculating the total RAM requirement for a given configuration, remember that there will be a fragmentation boundary when going to the off-chip RAM as buffers are built. This fragmentation may be up to a single buffer size in unusable RAM. LTS-20 User s Guide 2-13

28 Physblsgt; x Part RAM NA,M..O, Ad&m WFF Neuron Chip MIP Memory Map 64KR Total lsyl%, AddrssS Lower H6a&fTi$cal ROM sas 2575KB J Figure 2.5 LTSPO MIP Mode Memory Map 2-14 LTS-20 Overview

29 The default NSI mode EEPROM configuration settings for the LTS-20 are as follows: Configuration Parameters Default Setting Initial State Unconfigured I Explicit addressing Network variable processing Enabled Host Selection Program ID string 1 SLTA I Buffer Parameter Default Count Default Size Default Total Receive transaction buffers Transmit transaction buffers 2 28 ~ 56 Application input buffers Application output buffers Network input buffers Network output buffers Priority app. output buffers Priority net. output buffers Total bytes used for buffers 2,955 These values apply to LTS-20 Neuron Chip application version 7 only 2These values are fixed and cannot be modified The amount of RAM memory available for buffers in the NSI mode is 2,955 bytes. This total includes both on-chip and off-chip RAM. When calculating the total RAM requirement for a given configuration, remember that there will be a fragmentation boundary when going to the off-chip RAM as buffers are built. This fragmentation may be up to a single buffer size in unusable RAM. LTS-20 User s Guide 2-15

30 Neuron Chip NSI Memory Map 64KB Total ilxyhhss Upper f4dftpogical ROM Expand I : I Figure 2.6 LTS-20 NSI Memory Map The NODEUTIL node utility application available from the Developer s Toolbox on the Echelon web site ( can be used to modify the buffer configuration from a PC host. See the README.TXT file included with NODEUTIL for details LTS-20 Overview

31 3 Developing an SLTA with the LTS-20 module This chapter describes the process of developing a Serial LonTalk Adapter based on the LTS-20 Module. LTS-20 User s Guide 3-l

32 Overview To create a complete serial interface (SLTA), with functions similar to Echelon s SLTA-10 Serial LonTalk Adapter, based on the LTS-20 Module, follow these steps: Build an SLTA motherboard according to the specifications described in Chapter 2 and the guidelines described in Chapter 4. The motherboard may be part of custom application hardware, or may be a standalone board. Figure 3.1 is a sample motherboard schematic for an SLTA based on the use of the SMXTM transceivers. Additional transceiver interfaces are described in the rest of this chapter. Ensure that the communications parameters in the LTS-20 are compatible with the transceiver. The transceivers listed in table 2.3 are supported directly by the LTS-20 as predefined types. Set the transceiver ID lines to select the proper transceiver type. For custom transceivers, modify the communications parameters as described under Using Custom Transceivers in this chapter. Install the SLTA on a network as described in Chapter 7. The network may be a development network for initial testing, a manufacturing network for configuration during manufacture, or a production network for field installation. Using Predefined Transceivers The LTS-20 includes pre-defined transceiver parameters for the transceivers listed in table 2.3. When using any of these transceivers, the communications parameters are automatically programmed as described in Chapter 2. The following sections describe the hardware interface for standard LONWORKS transceivers available from Echelon for twisted pair, link power, and power line communications. The user s guide for each transceiver contains documentation on the interface requirements. The following sections provide additional information on using these transceivers with the LTS-20. TPT/XF-78 and TPT/XF Twisted Pair Transceivers The TPTKF-78 and TPTKF-1250 Twisted Pair Transceiver Modules support transformer-isolated communications over a twisted pair cable. The transceiver ID should be set to 1 for the TPTKF-78, and to 3 for the TPT/XF See the LONWORKS TPT Twisted Pair Transceiver Module User s Guide for details on these channel types. 3-2 Developing an SLTA with the LTS-20

33 +SVDC Regulated +IP DC Unregulated Figure 3.1 LTSPO Evaluation Board LTS-20 User s Guide 3-3

34 Figure 3.2 LTS-20 Evaluation Board Power Supply 3-4 Developing an SLTA with the LTS-20

35 JTJXPER BLOCK mm LEFI JUMPER BLOCK TOWARD RIGHT CLTS-20 I OCE, tms-20 = DTE) CONNECT To PC (DTE) CONNECT TO MODEM (DCE) a > Figure 3.3 LTS-20 Evaluation Board Serial LTS-20 User s Guide 3-5

36 FV- 70A Free Topology and LPT- 70 Link Power Transceivers The FTT-1OA Free Topology Transceiver provides 78kbps signaling without regard for cabling topology, and is by far the most popular twisted pair medium for LONWORKS networks. The LPT-10 Link Power Transceiver Module supports free topology communications over the same twisted pair cable that carries power for application nodes. Power is supplied from a 48VDC power supply and is coupled to the network via an LPI-10 Link Power Interface Module. Both a power supply and an LPI-10 module are required to operate LPT-10 transceivers. The LPT-10 transceiver does not provide sufficient power for the LTS-20, which must be locally powered and optically isolated from the LPT-10 transceiver. The transceiver ID input must be set to 4 to support the LPT-10 and FTT-1OA transceivers. Note that an FTT-1OA transceiver equipped with decoupling capacitors can operate on a link power segment, but an LPT-10 transceiver cannot operate on an unpowered FTT-1OA segment. PLT Power Line Transceiver A PLT Power Line Transceiver Module supports communications over AC or DC power mains. It may be connected to the LTS-20 module and a coupling circuit as shown in figure 3.2. The transceiver ID input must be set to support the correct PLT transceiver. See the pertinent LONWORKS PLT power line transceiver module user s guide for additional information, including a description of the coupling circuits. CPl CP2 CP4-1 CPO CPI cp2 CP4 PLT Transceiver TXOUT RXIN 0 Power 0 Line Media 0 LTS-20 Module -RESET XID4 XID3 XID2 XIDI XIDO Figure 3.4 Sample PLT Power Line Transceiver Interface 3-6 Developing an SLTA with the LTS-20

37 Using Custom Transceivers The LTS-20 module can be used with transceivers not listed in table 2.3 as long as the communications parameters are programmed to match the custom transceiver. Since network communication is not possible before these parameters are set, they must be programmed by the host over the EIA-232 link. The steps for programming a custom transceiver type are: 1 Determine the appropriate transceiver parameters for your channel. A discussion of transceiver modes and parameters may be found in Chapter 6 and Appendix A, section 6 of the Neuron Ch@ Data BOOK. Transceiver parameters may be modeled and fine-tuned using LonBuilder. 2 Select a transceiver ID of 30 (custom) on the LTS-20 transceiver ID inputs. The pins should remain set to this value in the production SLTA. 3 Install the transceiver parameters using a network management tool such as the LonMaker for Windows Integration Tool. The transceiver parameters are programmed into non-volatile EEPROM so the module will retain the new parameters after power is removed. LTS-20 User s Guide 3-7

38 3-8 Developing an SLTA with the LTS-20

39 LTS-20 Design Issues This chapter examines a number of design issues, including a discussion of electromagnetic interference (EMI) and electrostatic discharge (ESD). These issues should be considered when designing hardware based on the LTS-20 module. LTS-20 User s Guide 4-l

40 EMI Design Issues The high-speed digital signals associated with microcontroller designs can generate unintentional Electromagnetic Interference (EMI). High-speed voltage changes generate RF currents that can cause radiation from a product with a length of wire or piece of metal that can serve as an antenna. Products that use the LTS-20 module will generally need to demonstrate compliance with EM1 limits enforced by various regulatory agencies. In the USA, the FCC requires that unintentional radiators comply with Part 15 level A for industrial products, and level B for products that can be used in residential environments. Similar regulations are imposed in most countries throughout the world. Echelon has designed the LTS-20 module with low enough RF noise levels for design into level B products. This section describes design considerations to enable products based on the core modules to meet EM1 regulations. Designing Systems for EMC (Electromagnetic Compatibility) EMC Design Tips The LTS-20 module has been designed so that products using them should be able to meet both FCC and, based on radiated emissions, EN55022 level B limits. Careful system design is important to ensure that a product based on the core modules will achieve the desired EMC. Information on designing products for EMC is available in several forms including books, seminars, and consulting services. This section provides useful design tips for EMC. l l l l l Most of the EM1 will be radiated by the network cable and the power cable. Filtering is generally necessary to keep RF noise from getting out on the power cable. EM1 radiators should be kept away from the LTS-20 module to prevent internal RF noise from coupling onto the radiators. The LTS-20 module must be well grounded. Early EM1 testing of prototypes at a certified outdoor range is an extremely important step in the design of level B products. This testing ensures that grounding and enclosure design questions are addressed early enough to avoid most last-minute changes. ESD Design Issues Electrostatic Discharge (ESD) is encountered frequently in industrial and commercial use of electronic systems. Reliable system designs must consider the effects of ESD and take steps to protect sensitive components. Static discharges occur frequently in low-humidity environments when operators touch electronic equipment. The static 4-2 LTS-20 Design Issues

41 voltages generated by humans can easily exceed 1OkV. Keyboards, connectors, and enclosures provide paths for static discharges to reach ESD sensitive components such as the Neuron Chip. This section describes techniques to design ESD immunity into products based on the LTS-20 modules. Designing Systems for ESD Immunity ESD hardening includes the following techniques: l l l Provide adequate creepage and clearance distances to prevent ESD hits from reaching sensitive circuitry; Provide low impedance paths for ESD hits to ground; Use diode clamps or transient voltage suppression devices for accessible, sensitive circuits The best protection from ESD damage is circuit inaccessibility. If all circuit components are positioned away from package seams, the static discharges can be prevented from reaching ESD sensitive components. There are two measures of distance to consider for inaccessibility: creepage and clearance. Creepuge is the shortest distance between two points along the contours of a surface. Clearance is the shortest distance between two points through the air. An ESD hit generally arcs farther along a surface than it will when passing straight through the air. For example, a 20 kv discharge will arc about 0.4 inches (10 mm) through dry air, but the same discharge can travel over 0.8 inches (20mm) along a clean surface. Dirty surfaces can allow arcing over even longer creepage distances. When ESD hits to circuitry cannot be avoided through creepage, clearance, and ground guarding techniques, i.e., at external connector pins, explicit clamping of the exposed lines is required to shunt the ESD current. Consult Protection of Electronic Circuits from Overvoltages, by Ronald B. Standler, for advice about ESD and transient protection for exposed circuit lines. In general, exposed lines require diode clamps to the power supply rails or zener clamps to chassis ground in order to shunt the ESD current to ground while clamping the voltage low enough to prevent circuit damage. The Neuron Chip s communications port lines are connected directly to the LTS-20 edge connector without any ESD protection beyond that provided by the chip itself. If these lines will be exposed to ESD in a custom SLTA, protection must be added to the motherboard. LTS-20 User s Guide 4-3

42 4-4 LTS-20 Design Issues

43 5 The LTS-20 Software This chapter describes the LTS-20 software that is shipped with the Connectivity Starter Kit. LTS-20 User s Guide 5-l

44 Software Overview The LTS-20 software includes ANSI C source code for HA, a sample host application for MS-DOS that can be used as a basis for a user-developed host application on other host platforms. This application provides examples of sending and receiving network variable messages, as well as allowing a node based on an LTS-20 to be installed and bound by a network management tool such as the LonManager LonMaker for Windows Integration Tool or the LonBuilder network manager. Two network drivers (Windows 95/98 and Windows NT) are included so that an LTS- 20 may be immediately used with LNS applications. Source code for DOS and UNIX network drivers is also provided as a basis for a user-developed network driver for other hosts or operating systems using the MIP. DLL software is provided to make it easier to use the network driver under the Microsoft@ Windows operating system. An executable program and source code is also provided for a Host Connection Utility (HCU), which may be used to initiate and terminate the host to serial connection when the LTS-20 is used with a remote host. An example written in Neuron C is also provided as a basis for user-developed nodes on a LONWORKS network that need to initiate outgoing calls to a remote host. The LTS-20 includes NSI firmware that moves the upper layers of the LonTalk Protocol off the Neuron Chip within a node onto a host processor. This firmware allows the LTS-20 to be used by a host application to send and receive LonTalk messages. The host application may be a custom application as described in the LNS for Windows Developer s Kit or LNS DDE Server User s Guide. When using the LTS- 20 in the MIP mode, the host application may also be a network management application based on tools using the now-discontinued LonManager API. The firmware in an LTS-20 is fixed in ROM and need not be reprogrammed to use any of the module s capabilities. Installing LTS-20 Software The LTS-20 software is supplied on a diskette, together with an installation To install the LTS-20 software, follow these steps: program. 1. Place the diskette in one of the disk drives of your PC. This will typically be the A: or B: drive. 2. Start the automatic installation procedure by entering: A: INSTALL [ENTER] Substitute your disk drive name for the A: if you are using a different drive. 3. You will be asked to enter the name of your LONWORKS installation directory The default is: C:\ECHELON 5-2 LTS-20 Software

45 If you have other Echelon software products installed in the \LONWORKS directory, rather than the \ECHELON directory, enter \LONWORKS in place of the default directory name. The LTS-20 software will be installed in the LTS sub-directory of your LONWORKS directory, with the exception of the DOS network driver LDVSLTA. SYS. This file will be installed in the BIN sub-directory of your LONWORKS directory. To install the DOS network driver into your CONFIG. SYS file, follow the instructions in Chapter 9. The SLTA directory will contain the following files: l Read-Me File. The README. TXT file includes a list of all the files on the distribution disk, and also includes any updates to the documentation that occurred since the documentation was printed. l DOS Network Driver Sources. The DOS network driver source code is contained in the LDVSLTA directory. These files can be used as the basis for creating drivers for hosts other than PCs running DOS (see also the UNIX network driver sources). See the README. TXT file for a description of the driver files. See Chapter 8 for a description of the DOS network driver and Chapter 7 for a description of how to write a network driver for other hosts. See Chapter 4 of the LOhWORKS Host Application Programmer s Guide for a description of the services that must be supplied by a LONWORKS network driver. The source files to build the DOS driver are: LDVSLTA.CFG Configuration file for Borland C. MAKEFILE Make file script for Borland C. MDV-T1ME.C MDV-T1ME.H MSD-DEFS.H MSDmD1FC.C MSD-DRVR.H MSD-EXEC.C MSD-FRST.C Code to manage the PC timer. External interface definitions for the timer handler. Data structure and literal definitions. DOS driver interface functions. DOS driver interface and literal definitions. Main open, close, read, and write processing. Module to be linked first in the network driver. MSD-IRQC.ASM Serial I/O interrupt procedure. MSD-LAST.C MSD-RAW.C MSD-SEGD.ASM MSD-SI0.C MSD-TXRX.C MSD-UART.H Module to be linked last in the network driver. Direct serial I/O (modem) processing. Defines data segment register for driver. PC/AT UART interface processing. Single byte link layer processing. Defines PC/AT UART registers. l UNIX Network Driver Sources. The UNIX network driver source code is contained in the UNIX directory. These files can be used as the basis for creating drivers for any UNIX host, and can also be used as the basis for developing drivers for other hosts. See Chapter 10 for a description of the UNIX network driver and Chapter 8 for a description of how to write a network driver for other LTS-20 User s Guide 5-3