SLED New Features

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1 DOLPHIN INTEGRATION SLED Dolphin Integration 39 Avenue du Granier - BP 65 - Inovallee MEYLAN - FRANCE Phone : Fax : contact@dolphin.fr

2 SLED COPYRIGHT Dolphin Integration. All rights reserved. No part of this document may be transmitted, reproduced, or transcribed in a retrieval system without prior written consent of Dolphin Integration. The information in this manual is subject to change without notice and does not represent a commitment on the part of Dolphin Integration. Except as may be explicitly set forth in a written agreement between Dolphin Integration and its customer, Dolphin Integration does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Dolphin Integration reserves the right to revise this document without any obligation to notify any person of such revision or change. The software described in this manual is supplied under a license agreement between you and Dolphin Integration. The license agreement authorizes the number of copies that may be made and the computer systems on which they may be used. Any unauthorized duplication or use in whole or part is forbidden. DOLPHIN INTEGRATION is a brand of Dolphin Design. SMASH is a registered trademark of Dolphin Design. Mac OS is a registered trademark of Apple Inc. Microsoft Windows is a registered trademark of Microsoft Corporation. Verilog is a registered trademark of Cadence Design Systems Inc. Page 2/9

3 Contents Contents 3 THANKS 4 WEB SITE 4 SLED 5 PSL Assertion-Based Verification 5 SUPPORTED PLATFORMS 6 Microsoft Windows Linux on Intel x64 platform CREDITS & COPYRIGHTS 7 Qt : A C++ framework for cross-platform programming Scintilla Source Code Editor Component LIBJSON Component SLED 8 SLED Enhancements Bug fixing SLED API Enhancements Bug fixing SLED DRC Enhancements Bug fixing Page 3/9

4 SLED THANKS As always for new releases, we would like to thank those customers who take the time to report problems and/or to suggest improvements (please remember that the best way to do so is by sending an to or with an accurate description of your problem or suggestion, together with the relevant files if any). As you will see in the new features, we do our best to take remarks into account. And even if your suggestion does not appear this time, don t think it was lost or disregarded. Simply, it means that its implementation could not fit into the development plan for this particular release, but be assured that we will try to take it into account in a future release. WEB SITE Our web site is a source of information on our EDA solutions. Aside from evaluation kits for our products, a number of application notes, courses or upgrades are available for download. Page 4/9

5 SLED SLED is a hierarchical schematic entry solution of the third generation which delivers the long awaited dual capability for Graphic Entry and Scriptability at once. It blends efficiently the feasibility of linking components and of writing scripts for configuring a netlist hierarchically. Interoperability with other schematic entry tools is ensured for capitalizing on legacy designs and cooperative work, and interoperability in the Design Chains is ensured through standard design exchange formats and scriptability for customization by CAD managers. PSL Relevant options of SMASH include native support for simulation of PSL 1 properties, both assertions and coverage, with very low time and memory overhead. The integration of PSL is complete with source code syntax coloring, association of verification units with Verilog or VHDL models or instances, logging of PSL assertion violations, reporting of PSL sequence coverage results, and breaking into the source level debugger for investigation of design defects. Assertion-Based Verification The SLED SDG 2 option enables conversion of PSL assertions into synthesizable RTL models. This makes it possible for the designer to automatically integrate PSL verification units into a Design Under Test in an FPGA for emulation or in a testchip. Embedding hardware verification units in prototypes increases verification speed by several orders of magnitude. Automated generation of synthesizable models from PSL assertions can also be used as an efficient alternative to writing safety related parts of a design directly in RTL. These hardware verification units are integrated for embedded monitoring. 1 Property Specification Language 2 Synthesizable Detector Generator Page 5/9

6 SLED SUPPORTED PLATFORMS Microsoft Windows SLED is designed to run on Microsoft Windows Vista / 7 / 8 / 10 on x86_64 platforms. Linux on Intel x64 platform SLED is designed to run under X-Window on RedHat Enterprise Linux 6 (RHEL6) and supports compatible Linux distributions on x86_64 platforms. Page 6/9

7 CREDITS & COPYRIGHTS Qt : A C++ framework for cross-platform programming Qt Development Frameworks creates application development platforms for desktop and mobile device innovation. Qt Development Frameworks igia Oyj, Valimotie 21, Helsinki Finland Digia. Legal and Privacy Scintilla Source Code Editor Component License for Scintilla and SciTE Copyright by Neil Hodgson <neilh@scintilla.org> All Rights Reserved Permission to use, copy, modify, and distribute this software and its documentation for any purpose and without fee is hereby granted, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. NEIL HODGSON DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL NEIL HODGSON BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLI- GENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. LIBJSON Component Copyright 2010 Jonathan Wallace. All rights reserved. THIS SOFTWARE IS PROVIDED BY JONATHAN WALLACE AS IS AND ANY EXPRESS OR IM- PLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MER- CHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL JONATHAN WALLACE OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIA- BILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted as representing official policies, either expressed or implied, of Jonathan Wallace. Page 7/9

8 SLED SLED SLED Enhancements Parameter definition is now allowed only on cell (DDIsa SLED 3.3.0) Implemented the ability to display only the parameters that are relevant to the current design configuration (DDIsa SLED 3.3.0) Implemented the abilty to set a background color and pattern on symbol instance (DDIsa SLED 3.3.0) Improved the SLASH device library to take into account units and descriptions of the parameters, as well as colorization of instances (DDIsa SLED 3.3.0) Bug fixing Corrected the handling of the selection by the Duplicate Tool (DDIsa SLED 3.3.0) Corrected the text case handling in the hierarchical name information of the Project Manager items (DDIsa SLED 3.3.0) Corrected the application crash when creating a new cell with a name that contains the % character (DDIsa SLED 3.3.0) Fixed the display of modified views which are multiple displayed (DDIsa SLED 3.3.0) Corrected the backannotation results display when a schematic view doesn t have the same name as its cell (DDIsa SLED 3.3.0) Fixed the modification of the background color of power port (DDIsa SLED 3.3.0) Set the Read-Only status for the Description widget, when the description text has the HTML format (DDIsa SLED 3.3.0) SLED API Enhancements Implemented custom API functions to ease the objects retrieval (DDIsa12664, DDIsa SLED 3.3.0) Implemented the SLED API function SLED_AddDisciplineCompatibilityRule for adding a discipline compatibility rule (DDIsa SLED 3.3.0) Implemented SLED API function SLED_DesignImportConfiguration for importing a configuration file into the design (DDIsa SLED 3.3.0) Page 8/9

9 Bug fixing Corrected the management of Url parameter in the SLED Hooks (DDIsa SLED 3.3.0) SLED DRC Enhancements Completed the Incorrect object name rule for checking that no instances have the same name as a net name (DDIsa SLED 3.3.0) Implemented means to add new erc rules defined in tcl script (DDIsa SLED 3.3.0) Implemented means to define erc rules for cell with the SLED API (DDIsa SLED 3.3.0) Implemented the Erc rule Hierarchical parameter not defined which checks that hierarchical parameter used in instance parameter value is defined at the upper level (DDIsa SLED 3.3.0) Bug fixing Corrected application crash when an ERC is performed on schematic which contains instance with hierarchical parameter (DDIsa SLED 3.3.0) Corrected the result of a heriarchical which can be not consistent (DDIsa SLED 3.3.0) Corrected the selection of net when a rule violation net link is activated (DDIsa SLED 3.3.0) Corrected the un-expected violation of the Net not driven rule when a net is connected to ignored instance pin (DDIsa SLED 3.3.0) Corrected the behavioral of the Net not driven rule when not has no wire (DDIsa SLED 3.3.0) Renamed the ERC rule "Hidden nets" to "Hidden propagated instance pins" and fixed the link associated with the violation item (DDIsa SLED 3.3.0) Corrected the behavior of links associated with nets which violate the Implicit connection in schematic rule (DDIsa SLED 3.3.0) Modified the list of items provided by the violation of the rule Implicit connection in sheet (DDIsa SLED 3.3.0) Corrected the wrong violation of the rule Duplicated pin number when the symbol to check has several pins with the same name (DDIsa SLED 3.3.0) Renamed the Erc rule Duplicated pin name to Pin name conflict (DDIsa SLED 3.3.0) Corrected the behavior of links associated to instances which violate the rule Empty instance property value (DDIsa SLED 3.3.0) Corrected the behavioral of Unconnected input pin rule when it is applied on instance which has several propagated pins (DDIsa SLED 3.3.0) Corrected the behavioral of Unconnected Input/Output/Bidirectional port matrix rules when they are applied on schematic with instance(s) (DDIsa SLED 3.3.0) Page 9/9