MCF51JF128 Reference Manual. Supports the MCF51JF32, MCF51JF64, and MCF51JF128

Transcription

1 MCF51JF128 Reference Manual Supports the MCF51JF32, MCF51JF64, and MCF51JF128 Document Number: MCF51JF128RM Rev. 5, 08/2012

2 Appendix A Release Notes A.1 About This Document chapter changes A.2 Introduction chapter changes Removed references to discontinued QF and QH families A.3 Chip Configuration chapter changes A.4 Memory Map chapter changes Added the new section "Read-after-write sequence and required serialization of memory operations" A.5 Clock Distribution chapter changes MCF51JF128 Reference Manual, Rev. 5, 08/2012 Freescale Semiconductor, Inc. 1321

3 Reset and Boot chapter changes A.6 Reset and Boot chapter changes A.7 Power Management chapter changes A.8 Security chapter changes A.9 Signal Multiplexing and Signal Descriptions chapter changes A.10 MXC changes A.11 V1 ColdFire Core changes A.12 EMAC changes MCF51JF128 Reference Manual, Rev. 5, 08/ Freescale Semiconductor, Inc.

4 Appendix A Release Notes A.13 SIM changes A.14 Crossbar switch module changes A.15 INTC V1 changes Removed the unnecessary section "Device-Specific Exception and Interrupt Vector Tables" because the information is not included in this chapter. In the "Interrupt Request Level and Priority Assignments" section, revised the description of the location of information. A.16 LLWU changes A.17 RCM changes A.18 SMC changes For the RUN to VLPR transition trigger conditions in the "Power mode transition triggers" table, removed the specific maximum frequency numbers and made a reference to the chip-specific Power Management chapter. A.19 PMC changes MCF51JF128 Reference Manual, Rev. 5, 08/2012 Freescale Semiconductor, Inc. 1323

5 DMA Controller changes A.20 DMA Controller changes Reorganized the description of DSR_BCR[CE]. Throughout: Changed "byte, word, longword" references to "8-bit, 16-bit, 32-bit" or "1-byte, 2-byte, 4-byte" In the "Programming the DMA Controller Module" section: Clarified the cautionary note about programming the DMA module's registers during channel execution Under the list item "TCDn is initialized": subordinated multiple subsequent list items In the "Advanced Data Transfer Controls: Auto-Alignment" section's example description: Reorganized the sample register/bitfield values as a list A.21 MCG changes For the IRCST field in the MCG Status Register, changed references to the fast clock from "fast clock (2 MHz IRC)" to "fast clock (4 MHz IRC)". A.22 OSC changes A.23 FMC changes A.24 FTFL changes Improved flash reliability specs per module certification results Fix Flash Command note to indicate that FlexRAM or Programming Acceleration RAM is used during PGMSEC command for all devices MCF51JF128 Reference Manual, Rev. 5, 08/ Freescale Semiconductor, Inc.

6 Appendix A Release Notes A.25 Mini-FlexBus changes Minor editorial changes and reorganization of sections: Many sections were divided into multiple subsections. Changed Overview section name to Definition. Moved data from signal description subsections into the signal description table. Removed Chip Select Operation section. Moved Modes of operation section to Functional description section. Combined Bus Cycle execution and data transfer cycle states sections into the Data transfer states section. Changed the Note in the CSMR[V] bitfield description to say: "At reset, FB_CS0 will fire for any access to the FlexBus memory region. CSMR0[V] must be set as part of the chip select initialization sequence to allow other chip selects to function as programmed." A.26 EzPort changes A.27 CAU changes A.28 RNGB changes A.29 CRC changes No substantial content changes A.30 ADC changes In ADC Signal Descriptions section: Added note to refer to chip configuration for inputs supported. MCF51JF128 Reference Manual, Rev. 5, 08/2012 Freescale Semiconductor, Inc. 1325

7 CMP changes A.31 CMP changes Updated SE value in 'Sampled, Filtered (# 4B): Sampling point internally derived' diagram. A.32 DAC changes A.33 VREF changes A.34 PDB changes In the memory map, changed Channel n Status Register access to R/W. A.35 MTIM changes A.36 LPTMR changes Updated the following sentence: "If CSR[TFC] is cleared, then the CNR is also reset whenever CSR[TCF] is set." A.37 CMT changes MCF51JF128 Reference Manual, Rev. 5, 08/ Freescale Semiconductor, Inc.

8 Appendix A Release Notes A.38 FTM changes A.39 SPI changes A.40 USB changes In "Host mode operation examples", corrected the "Data toggle" in the first bullet of Step 11 for the "To complete a control transaction to a connected device" procedure. A.41 USBDCD changes A.42 USB VREG changes Removed the number specified for the STANDBY regulator output load current. Corrected the figure "Ideal Relation Between the Regulator Output and Input Power Supply". A.43 I2C changes In description of F[ICR], added new final sentence and table containing examples of MULT and ICR field settings. In description of C2[SBRC], added sentence describing an example of a "very fast" I2C mode. In "Clock stretching" section, added new final sentence to clarify the effect of clock stretching. Clarified that the reserved bit 7 of the Programmable Input Glitch Filter register can be written but that writing it has no effect. In the "SCL high timeout" section, removed references to detection of a HIGH timeout after a STOP condition appears on the bus. Reorganized the "Address matching wakeup" section, and added in the final note the sentence "The main purpose is not communication." MCF51JF128 Reference Manual, Rev. 5, 08/2012 Freescale Semiconductor, Inc. 1327

9 UART changes Reorganized the "Address matching" section, and clarified the sources of a 7-bit and 10-bit address, including the involvement of ADEXT and AD[10:8] in Control Register 2. In "Address matching wakeup" section: Combined the two notes and expanded the note text In the Status register: Added added a new note to the description of the RAM bit In the "Address matching wakeup" section: Clarified the note text In "I2C divider and hold values" section: Added note preceding the table, and shaded table cells containing ICR values of 00h to 0Fh A.44 UART changes A.45 I2S/SAI changes Removed the section "Multiple SAI Synchronous Mode" and references to that mode in descriptions of the SYNC, BCS, and BCI fields in the TCR2 and RCR2 registers For both TCSR[TE] and RCSR[RE] fields, clarified the description for field value of 1. In "Introduction" section: Clarified support for TDM mode. Revised descriptions of BCS and BCI fields in TCR2. Clarified descriptions of TCE field in TCR3 and RCE field in RCR3. In "FIFO pointers" section: Clarified 8-bit and 16-bit accesses to the FIFOs. In "Frame sync configuration" section: Clarified various configuration options. Removed references to "received" from description of TCR4[MF] Removed references to "transmitted" from description of RCR4[MF] In the "Bit clock" section of the "Clocking" section, added a new final paragraph: "If the SAI transmitter or receiver is using an externally generated bit clock in asynchronous mode and that bit clock is generated by an SAI that is disabled in stop mode, then the transmitter or receiver should be disabled by software before entering stop mode. This issue does not apply when the transmitter or receiver is in a synchronous mode because all synchronous SAIs are enabled and disabled simultaneously." A.46 RGPIO changes In "Initialization Information" section, revised sequence and text of list items. A.47 EGPIO changes MCF51JF128 Reference Manual, Rev. 5, 08/ Freescale Semiconductor, Inc.

10 A.48 Port Control changes A.49 TSI changes A.50 IRQ changes In "Exit from Low-Power Modes" section: standardized references to low-power modes, and, in second sentence, changed "low" to "asserted" In "Stop modes" section: Changed "stop mode" to "stop modes," and revised first sentence A.51 Debug changes In table of "Overview" section: added row for debug revision CF1_B+_no_PSTB In the "Program Counter Breakpoint/Mask Registers (PBR0 3, PBMR)" section: In the Note preceding the PBR0 diagram and table, simplified the final sentence MCF51JF128 Reference Manual, Rev. 5, 08/2012 Freescale Semiconductor, Inc. 1329

11 MCF51JF128 Reference Manual, Rev. 5, 08/ Freescale Semiconductor, Inc.

12 How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL East Elliot Road Tempe, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen Muenchen, Germany (English) (English) (German) (French) Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo Japan or support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing China support.asia@freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-rohs-complaint and/or non-pb-free counterparts. For further information, see or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. Document Number: MCF51JF128RM Rev. 5, 08/2012

13 MCF51JU128 Reference Manual Supports the MCF51JU32, MCF51JU64, and MCF51JU128 Document Number: MCF51JU128RM Rev. 3, 08/2012

14 Appendix A Release Notes A.1 About This Document chapter changes A.2 Introduction chapter changes Removed references to discontinued QF and QH families A.3 Chip Configuration chapter changes A.4 Memory Map chapter changes Added the new section "Read-after-write sequence and required serialization of memory operations" A.5 Clock Distribution chapter changes MCF51JU128 Reference Manual, Rev. 3, 08/2012 Freescale Semiconductor, Inc. 1279

15 Reset and Boot chapter changes A.6 Reset and Boot chapter changes A.7 Power Management chapter changes A.8 Security chapter changes A.9 Signal Multiplexing and Signal Descriptions chapter changes A.10 MXC changes A.11 V1 ColdFire Core changes A.12 EMAC changes MCF51JU128 Reference Manual, Rev. 3, 08/ Freescale Semiconductor, Inc.

16 Appendix A Release Notes A.13 SIM changes A.14 Crossbar switch module changes A.15 INTC V1 changes Removed the unnecessary section "Device-Specific Exception and Interrupt Vector Tables" because the information is not included in this chapter. In the "Interrupt Request Level and Priority Assignments" section, revised the description of the location of information. A.16 LLWU changes A.17 RCM changes A.18 SMC changes For the RUN to VLPR transition trigger conditions in the "Power mode transition triggers" table, removed the specific maximum frequency numbers and made a reference to the chip-specific Power Management chapter. A.19 PMC changes MCF51JU128 Reference Manual, Rev. 3, 08/2012 Freescale Semiconductor, Inc. 1281

17 DMA Controller changes A.20 DMA Controller changes Reorganized the description of DSR_BCR[CE]. Throughout: Changed "byte, word, longword" references to "8-bit, 16-bit, 32-bit" or "1-byte, 2-byte, 4-byte" In the "Programming the DMA Controller Module" section: Clarified the cautionary note about programming the DMA module's registers during channel execution Under the list item "TCDn is initialized": subordinated multiple subsequent list items In the "Advanced Data Transfer Controls: Auto-Alignment" section's example description: Reorganized the sample register/bitfield values as a list A.21 MCG changes For the IRCST field in the MCG Status Register, changed references to the fast clock from "fast clock (2 MHz IRC)" to "fast clock (4 MHz IRC)". A.22 OSC changes A.23 FMC changes A.24 FTFL changes Improved flash reliability specs per module certification results Fix Flash Command note to indicate that FlexRAM or Programming Acceleration RAM is used during PGMSEC command for all devices MCF51JU128 Reference Manual, Rev. 3, 08/ Freescale Semiconductor, Inc.

18 Appendix A Release Notes A.25 Mini-FlexBus changes Minor editorial changes and reorganization of sections: Many sections were divided into multiple subsections. Changed Overview section name to Definition. Moved data from signal description subsections into the signal description table. Removed Chip Select Operation section. Moved Modes of operation section to Functional description section. Combined Bus Cycle execution and data transfer cycle states sections into the Data transfer states section. Changed the Note in the CSMR[V] bitfield description to say: "At reset, FB_CS0 will fire for any access to the FlexBus memory region. CSMR0[V] must be set as part of the chip select initialization sequence to allow other chip selects to function as programmed." A.26 EzPort changes A.27 CRC changes No substantial content changes A.28 ADC changes In ADC Signal Descriptions section: Added note to refer to chip configuration for inputs supported. A.29 CMP changes Updated SE value in 'Sampled, Filtered (# 4B): Sampling point internally derived' diagram. A.30 DAC changes MCF51JU128 Reference Manual, Rev. 3, 08/2012 Freescale Semiconductor, Inc. 1283

19 VREF changes A.31 VREF changes A.32 PDB changes A.33 MTIM changes A.34 LPTMR changes Updated the following sentence: "If CSR[TFC] is cleared, then the CNR is also reset whenever CSR[TCF] is set." A.35 CMT changes A.36 FTM changes A.37 SPI changes MCF51JU128 Reference Manual, Rev. 3, 08/ Freescale Semiconductor, Inc.

20 Appendix A Release Notes A.38 USB changes In "Host mode operation examples", corrected the "Data toggle" in the first bullet of Step 11 for the "To complete a control transaction to a connected device" procedure. A.39 USBDCD changes A.40 USB VREG changes Removed the number specified for the STANDBY regulator output load current. Corrected the figure "Ideal Relation Between the Regulator Output and Input Power Supply". A.41 I2C changes In description of F[ICR], added new final sentence and table containing examples of MULT and ICR field settings. In description of C2[SBRC], added sentence describing an example of a "very fast" I2C mode. In "Clock stretching" section, added new final sentence to clarify the effect of clock stretching. Clarified that the reserved bit 7 of the Programmable Input Glitch Filter register can be written but that writing it has no effect. In the "SCL high timeout" section, removed references to detection of a HIGH timeout after a STOP condition appears on the bus. Reorganized the "Address matching wakeup" section, and added in the final note the sentence "The main purpose is not communication." Reorganized the "Address matching" section, and clarified the sources of a 7-bit and 10-bit address, including the involvement of ADEXT and AD[10:8] in Control Register 2. In "Address matching wakeup" section: Combined the two notes and expanded the note text In the Status register: Added added a new note to the description of the RAM bit In the "Address matching wakeup" section: Clarified the note text In "I2C divider and hold values" section: Added note preceding the table, and shaded table cells containing ICR values of 00h to 0Fh A.42 UART changes MCF51JU128 Reference Manual, Rev. 3, 08/2012 Freescale Semiconductor, Inc. 1285

21 I2S/SAI changes A.43 I2S/SAI changes Removed the section "Multiple SAI Synchronous Mode" and references to that mode in descriptions of the SYNC, BCS, and BCI fields in the TCR2 and RCR2 registers For both TCSR[TE] and RCSR[RE] fields, clarified the description for field value of 1. In "Introduction" section: Clarified support for TDM mode. Revised descriptions of BCS and BCI fields in TCR2. Clarified descriptions of TCE field in TCR3 and RCE field in RCR3. In "FIFO pointers" section: Clarified 8-bit and 16-bit accesses to the FIFOs. In "Frame sync configuration" section: Clarified various configuration options. Removed references to "received" from description of TCR4[MF] Removed references to "transmitted" from description of RCR4[MF] In the "Bit clock" section of the "Clocking" section, added a new final paragraph: "If the SAI transmitter or receiver is using an externally generated bit clock in asynchronous mode and that bit clock is generated by an SAI that is disabled in stop mode, then the transmitter or receiver should be disabled by software before entering stop mode. This issue does not apply when the transmitter or receiver is in a synchronous mode because all synchronous SAIs are enabled and disabled simultaneously." A.44 RGPIO changes In "Initialization Information" section, revised sequence and text of list items. A.45 EGPIO changes A.46 Port Control changes A.47 TSI changes MCF51JU128 Reference Manual, Rev. 3, 08/ Freescale Semiconductor, Inc.

22 A.48 IRQ changes In "Exit from Low-Power Modes" section: standardized references to low-power modes, and, in second sentence, changed "low" to "asserted" In "Stop modes" section: Changed "stop mode" to "stop modes," and revised first sentence A.49 Debug changes In table of "Overview" section: added row for debug revision CF1_B+_no_PSTB In the "Program Counter Breakpoint/Mask Registers (PBR0 3, PBMR)" section: In the Note preceding the PBR0 diagram and table, simplified the final sentence MCF51JU128 Reference Manual, Rev. 3, 08/2012 Freescale Semiconductor, Inc. 1287

23 MCF51JU128 Reference Manual, Rev. 3, 08/ Freescale Semiconductor, Inc.

24 How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL East Elliot Road Tempe, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen Muenchen, Germany (English) (English) (German) (French) Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo Japan or support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing China support.asia@freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-rohs-complaint and/or non-pb-free counterparts. For further information, see or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. Document Number: MCF51JU128RM Rev. 3, 08/2012

25 MCF51QM128 Reference Manual Supports the MCF51QM32, MCF51QM64, and MCF51QM128 Document Number: MCF51QM128RM Rev. 4, 08/2012

26 Appendix A Release Notes A.1 About This Document chapter changes A.2 Introduction chapter changes Removed references to discontinued QF and QH families A.3 Chip Configuration chapter changes A.4 Memory Map chapter changes Added the new section "Read-after-write sequence and required serialization of memory operations" A.5 Clock Distribution chapter changes MCF51QM128 Reference Manual, Rev. 4, 08/2012 Freescale Semiconductor, Inc. 1211

27 Reset and Boot chapter changes A.6 Reset and Boot chapter changes A.7 Power Management chapter changes A.8 Security chapter changes A.9 Signal Multiplexing and Signal Descriptions chapter changes A.10 MXC changes A.11 V1 ColdFire Core changes A.12 EMAC changes MCF51QM128 Reference Manual, Rev. 4, 08/ Freescale Semiconductor, Inc.

28 Appendix A Release Notes A.13 SIM changes A.14 Crossbar switch module changes A.15 INTC V1 changes Removed the unnecessary section "Device-Specific Exception and Interrupt Vector Tables" because the information is not included in this chapter. In the "Interrupt Request Level and Priority Assignments" section, revised the description of the location of information. A.16 LLWU changes A.17 RCM changes A.18 SMC changes For the RUN to VLPR transition trigger conditions in the "Power mode transition triggers" table, removed the specific maximum frequency numbers and made a reference to the chip-specific Power Management chapter. A.19 PMC changes MCF51QM128 Reference Manual, Rev. 4, 08/2012 Freescale Semiconductor, Inc. 1213

29 VREG changes A.20 VREG changes Removed the number specified for the STANDBY regulator output load current. Corrected the figure "Ideal Relation Between the Regulator Output and Input Power Supply". A.21 DMA Controller changes Reorganized the description of DSR_BCR[CE]. Throughout: Changed "byte, word, longword" references to "8-bit, 16-bit, 32-bit" or "1-byte, 2-byte, 4-byte" In the "Programming the DMA Controller Module" section: Clarified the cautionary note about programming the DMA module's registers during channel execution Under the list item "TCDn is initialized": subordinated multiple subsequent list items In the "Advanced Data Transfer Controls: Auto-Alignment" section's example description: Reorganized the sample register/bitfield values as a list A.22 MCG changes For the IRCST field in the MCG Status Register, changed references to the fast clock from "fast clock (2 MHz IRC)" to "fast clock (4 MHz IRC)". A.23 OSC changes A.24 FMC changes A.25 FTFL changes Improved flash reliability specs per module certification results Fix Flash Command note to indicate that FlexRAM or Programming Acceleration RAM is used during PGMSEC command for all devices MCF51QM128 Reference Manual, Rev. 4, 08/ Freescale Semiconductor, Inc.

30 Appendix A Release Notes A.26 Mini-FlexBus changes Minor editorial changes and reorganization of sections: Many sections were divided into multiple subsections. Changed Overview section name to Definition. Moved data from signal description subsections into the signal description table. Removed Chip Select Operation section. Moved Modes of operation section to Functional description section. Combined Bus Cycle execution and data transfer cycle states sections into the Data transfer states section. Changed the Note in the CSMR[V] bitfield description to say: "At reset, FB_CS0 will fire for any access to the FlexBus memory region. CSMR0[V] must be set as part of the chip select initialization sequence to allow other chip selects to function as programmed." A.27 EzPort changes A.28 CAU changes A.29 RNGB changes A.30 CRC changes No substantial content changes A.31 ADC changes In ADC Signal Descriptions section: Added note to refer to chip configuration for inputs supported. MCF51QM128 Reference Manual, Rev. 4, 08/2012 Freescale Semiconductor, Inc. 1215

31 CMP changes A.32 CMP changes Updated SE value in 'Sampled, Filtered (# 4B): Sampling point internally derived' diagram. A.33 DAC changes A.34 VREF changes A.35 PDB changes In the memory map, changed Channel n Status Register access to R/W. A.36 MTIM changes A.37 LPTMR changes Updated the following sentence: "If CSR[TFC] is cleared, then the CNR is also reset whenever CSR[TCF] is set." A.38 CMT changes MCF51QM128 Reference Manual, Rev. 4, 08/ Freescale Semiconductor, Inc.

32 Appendix A Release Notes A.39 FTM changes A.40 SPI changes A.41 I2C changes In description of F[ICR], added new final sentence and table containing examples of MULT and ICR field settings. In description of C2[SBRC], added sentence describing an example of a "very fast" I2C mode. In "Clock stretching" section, added new final sentence to clarify the effect of clock stretching. Clarified that the reserved bit 7 of the Programmable Input Glitch Filter register can be written but that writing it has no effect. In the "SCL high timeout" section, removed references to detection of a HIGH timeout after a STOP condition appears on the bus. Reorganized the "Address matching wakeup" section, and added in the final note the sentence "The main purpose is not communication." Reorganized the "Address matching" section, and clarified the sources of a 7-bit and 10-bit address, including the involvement of ADEXT and AD[10:8] in Control Register 2. In "Address matching wakeup" section: Combined the two notes and expanded the note text In the Status register: Added added a new note to the description of the RAM bit In the "Address matching wakeup" section: Clarified the note text In "I2C divider and hold values" section: Added note preceding the table, and shaded table cells containing ICR values of 00h to 0Fh A.42 UART changes A.43 RGPIO changes In "Initialization Information" section, revised sequence and text of list items. MCF51QM128 Reference Manual, Rev. 4, 08/2012 Freescale Semiconductor, Inc. 1217

33 EGPIO changes A.44 EGPIO changes A.45 Port Control changes A.46 TSI changes A.47 IRQ changes In "Exit from Low-Power Modes" section: standardized references to low-power modes, and, in second sentence, changed "low" to "asserted" In "Stop modes" section: Changed "stop mode" to "stop modes," and revised first sentence A.48 Debug changes In table of "Overview" section: added row for debug revision CF1_B+_no_PSTB In the "Program Counter Breakpoint/Mask Registers (PBR0 3, PBMR)" section: In the Note preceding the PBR0 diagram and table, simplified the final sentence MCF51QM128 Reference Manual, Rev. 4, 08/ Freescale Semiconductor, Inc.

34 How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL East Elliot Road Tempe, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen Muenchen, Germany (English) (English) (German) (French) Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo Japan or support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing China support.asia@freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-rohs-complaint and/or non-pb-free counterparts. For further information, see or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. Document Number: MCF51QM128RM Rev. 4, 08/2012

35 MCF51QU128 Reference Manual Supports the MCF51QU32, MCF51QU64, and MCF51QU128 Document Number: MCF51QU128RM Rev. 3, 08/2012

36 Appendix A Release Notes A.1 About This Document chapter changes A.2 Introduction chapter changes Removed references to discontinued QF and QH families A.3 Chip Configuration chapter changes A.4 Memory Map chapter changes Added the new section "Read-after-write sequence and required serialization of memory operations" A.5 Clock Distribution chapter changes MCF51QU128 Reference Manual, Rev. 3, 08/2012 Freescale Semiconductor, Inc. 1167

37 Reset and Boot chapter changes A.6 Reset and Boot chapter changes A.7 Power Management chapter changes A.8 Security chapter changes A.9 Signal Multiplexing and Signal Descriptions chapter changes A.10 MXC changes A.11 V1 ColdFire Core changes A.12 EMAC changes MCF51QU128 Reference Manual, Rev. 3, 08/ Freescale Semiconductor, Inc.

38 Appendix A Release Notes A.13 SIM changes A.14 Crossbar switch module changes A.15 INTC V1 changes Removed the unnecessary section "Device-Specific Exception and Interrupt Vector Tables" because the information is not included in this chapter. In the "Interrupt Request Level and Priority Assignments" section, revised the description of the location of information. A.16 LLWU changes A.17 RCM changes A.18 SMC changes For the RUN to VLPR transition trigger conditions in the "Power mode transition triggers" table, removed the specific maximum frequency numbers and made a reference to the chip-specific Power Management chapter. A.19 PMC changes MCF51QU128 Reference Manual, Rev. 3, 08/2012 Freescale Semiconductor, Inc. 1169

39 VREG changes A.20 VREG changes Removed the number specified for the STANDBY regulator output load current. Corrected the figure "Ideal Relation Between the Regulator Output and Input Power Supply". A.21 DMA Controller changes Reorganized the description of DSR_BCR[CE]. Throughout: Changed "byte, word, longword" references to "8-bit, 16-bit, 32-bit" or "1-byte, 2-byte, 4-byte" In the "Programming the DMA Controller Module" section: Clarified the cautionary note about programming the DMA module's registers during channel execution Under the list item "TCDn is initialized": subordinated multiple subsequent list items In the "Advanced Data Transfer Controls: Auto-Alignment" section's example description: Reorganized the sample register/bitfield values as a list A.22 MCG changes For the IRCST field in the MCG Status Register, changed references to the fast clock from "fast clock (2 MHz IRC)" to "fast clock (4 MHz IRC)". A.23 OSC changes A.24 FMC changes A.25 FTFL changes Improved flash reliability specs per module certification results Fix Flash Command note to indicate that FlexRAM or Programming Acceleration RAM is used during PGMSEC command for all devices MCF51QU128 Reference Manual, Rev. 3, 08/ Freescale Semiconductor, Inc.

40 Appendix A Release Notes A.26 Mini-FlexBus changes Minor editorial changes and reorganization of sections: Many sections were divided into multiple subsections. Changed Overview section name to Definition. Moved data from signal description subsections into the signal description table. Removed Chip Select Operation section. Moved Modes of operation section to Functional description section. Combined Bus Cycle execution and data transfer cycle states sections into the Data transfer states section. Changed the Note in the CSMR[V] bitfield description to say: "At reset, FB_CS0 will fire for any access to the FlexBus memory region. CSMR0[V] must be set as part of the chip select initialization sequence to allow other chip selects to function as programmed." A.27 EzPort changes A.28 CRC changes No substantial content changes A.29 ADC changes In ADC Signal Descriptions section: Added note to refer to chip configuration for inputs supported. A.30 CMP changes Updated SE value in 'Sampled, Filtered (# 4B): Sampling point internally derived' diagram. A.31 DAC changes MCF51QU128 Reference Manual, Rev. 3, 08/2012 Freescale Semiconductor, Inc. 1171

41 VREF changes A.32 VREF changes A.33 PDB changes In the memory map, changed Channel n Status Register access to R/W. A.34 MTIM changes A.35 LPTMR changes Updated the following sentence: "If CSR[TFC] is cleared, then the CNR is also reset whenever CSR[TCF] is set." A.36 CMT changes A.37 FTM changes A.38 SPI changes MCF51QU128 Reference Manual, Rev. 3, 08/ Freescale Semiconductor, Inc.

42 Appendix A Release Notes A.39 I2C changes In description of F[ICR], added new final sentence and table containing examples of MULT and ICR field settings. In description of C2[SBRC], added sentence describing an example of a "very fast" I2C mode. In "Clock stretching" section, added new final sentence to clarify the effect of clock stretching. Clarified that the reserved bit 7 of the Programmable Input Glitch Filter register can be written but that writing it has no effect. In the "SCL high timeout" section, removed references to detection of a HIGH timeout after a STOP condition appears on the bus. Reorganized the "Address matching wakeup" section, and added in the final note the sentence "The main purpose is not communication." Reorganized the "Address matching" section, and clarified the sources of a 7-bit and 10-bit address, including the involvement of ADEXT and AD[10:8] in Control Register 2. In "Address matching wakeup" section: Combined the two notes and expanded the note text In the Status register: Added added a new note to the description of the RAM bit In the "Address matching wakeup" section: Clarified the note text In "I2C divider and hold values" section: Added note preceding the table, and shaded table cells containing ICR values of 00h to 0Fh A.40 UART changes A.41 RGPIO changes In "Initialization Information" section, revised sequence and text of list items. A.42 EGPIO changes A.43 Port Control changes MCF51QU128 Reference Manual, Rev. 3, 08/2012 Freescale Semiconductor, Inc. 1173

43 TSI changes A.44 TSI changes A.45 IRQ changes In "Exit from Low-Power Modes" section: standardized references to low-power modes, and, in second sentence, changed "low" to "asserted" In "Stop modes" section: Changed "stop mode" to "stop modes," and revised first sentence A.46 Debug changes In table of "Overview" section: added row for debug revision CF1_B+_no_PSTB In the "Program Counter Breakpoint/Mask Registers (PBR0 3, PBMR)" section: In the Note preceding the PBR0 diagram and table, simplified the final sentence MCF51QU128 Reference Manual, Rev. 3, 08/ Freescale Semiconductor, Inc.

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