AMD Opteron Processor. Architectures for Multimedia Systems A.Y. 2009/2010 Simone Segalini

Transcription

1 AMD Opteron Processor Architectures for Multimedia Systems A.Y. 2009/2010 Simone Segalini

2 A brief of history Released on April 22, 2003 (codename SledgeHammer) First processor to implement AMD64 instruction set architecture Quad-core configuration released on September 10, 2007 (codename Barcelona) Latest release: 8- and 12- core Socket G34 Opteron (codename MagnyCours), March

3 AMD Opteron processor family

4 AMD Opteron Processor Two important capabilities: Native execution of legacy x86 32-bit applications without speed penalties Native execution of x bit applications Integrated memory controller supporting DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM In multiprocessor systems, CPUs communicate through Direct Connect Architecture over high-speed HyperTransport links Non-Uniform Memory Access (NUMA) architecture: each CPU has its own memory

5 Magny-Cours die Six x86-64 cores Shared L3 cache Four HyperTransport3 ports Two DDR3 memory channels Three-way superscalar processor: fetch and decode up to three x86-64 instructions each cycle Two indipendent schedulers: Integer scheduler Floating-point and multimedia scheduler

6 Multichip package Two dies coupled in a multi chip module (MCM) 12-core processor architecture Four HyperTransport ports 12-Mbytes L3 cache Four DDR3 memory channels New socket G34 HT3 ports for server topologies

7 Cache Hierarchy L1: separate instruction and data caches two-way associative latency of three clock cycles 64 kbytes L2: victim cache for L1 instruction and data caches - 16-way associative latency of 12 clock cycles Kbytes L3: 6-Mbytes Inclusive cache keeping a copy if the data is being accessed by multiple cores Exclusive cache removing the data from L3 and placing it into L1 creating space for L2 victim data if the data is accessed by a single core (no overlaps between L3 and L2) Shared cache data can be used at the same time by all the cores without loading it again from RAM Subdivision into two, three, four subcaches of 1 or 2 Mbytes

8 AMD Opteron processor features Direct Connect Architecture Front-side bus eliminated Better perfomance and efficiency by eliminating traditional bottlenecks related to front-side bus architecture Processor core directly connected to the memory, the I/O subsystem, any other processors by using HyperTransport links

9 AMD Opteron processor features HyperTransport Technology Narrow, high-speed, low power I/O bus HT links capable of very fast signaling up to 800 MHz clock speed Full compatibility with Peripheral Component Interconnect (PCI) Packetized bus: addresses, data and commands are sent along the same wires allowing narrower links easier to route Supporting multiple connection topologies including daisy chain, switch and star topologies

10 AMD Opteron processor features AMD Virtualization AMD-V allows multiple operating systems to run simultaneously on a single computer system The Hypervisor separates the operating systems from the underlying hw and controls all operations performed by a guest AMD-V offers a hardware-assisted virtualization (Rapid Virtualization Indexing) RVI introduces a second level of translation via and additional Nested Page Table (NPT) to translate guest addresses into system physical addresses Now the Hypervisor specifies how the processor should handle guest operations without transferring control to the Hypervisor itself Better efficiency of switching between VMs Better performances Better isolation of the VMs for secure operations

11 AMD Opteron processor features AMD Power Technology Dual Dynamic Power Management: separate power supplies to the cores and integrated memory controller (cores operate indipendently from the memory controller) Indipendent Dynamic Core Technology: each core is allowed to operate at different frequencies indipendently of each other AMD CoolCore Technology: reduction of processor Energy consumption by turning off unused parts of the processor AMD PowerCap: reduction overall power processor consumption AMD Smart Fetch Technology: inactive cores enter a halt state and draw less power AMD CoolSpeed Technology: processors drop into a lower power mode if thermal specifications are exceeded

12 References Pat Convay, Nathan Kalyanasundharam, Gregg Donley, Kevin Lepak, Bill Hughes (2010), Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor, IEEE Micro, March/April 2010, pp Pat Convay, Bill Hughes (2007), The AMD Opteron Northbridge Architecture, IEEE Micro, vol. 27, no. 2, March/April 2007, pp Opteron, from Wikipedia, the free enciclopedia, Daniele Magliozzi (2008), AMD Opteron Quad-Core, Politecnico di Milano Direct Connect Architecture, from AMD website, AMD Virtualization, from AMD website, AMD-P, from AMD website, AMD HyperTransport Technology, from AMD website,

13 Thank you for your attention!