Agilent U1083A-005. Acqiris SVM3500 High-Speed 6U VME/VXS Digitizer. 12-bit, 4 ch, 500 MS/s 12-bit, 2 ch, 1 GS/s 12-bit, 1 ch, 2 GS/s

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1 Agilent U1083A-005 Acqiris SVM3500 High-Speed 6U VME/VXS Digitizer 12-bit, 4 ch, 12-bit, 2 ch, 1 GS/s 12-bit, 1 ch, 2 GS/s

2 Main Features 6U single slot VME/VXS (VITA 41) module Quad-channel 12-bit Dual 12-bit 1GS/s and single 12-bit 2GS/s configuration possibilities External clock distributed by an in-house developed low jitter chipset One Xilinx Virtex-5 FPGA providing on board FIR for interleaving mismatch correction Lookup table providing data correction Two Xilinx Virtex-4 FPGAs for real-time signal processing and data flow control Two on-board DDR2 SDRAM banks, 32 Mwords, each 64-bit wide, for a total of 512 MB processing memory Tundra TSI148 VME bus interface, VME64x and 2eSST compliant VXS VITA 41.0 compliant, 8x Gbps serial I/O links on P0 connector Two front panel SFP slots for up to Gbps fiber or copper transceivers Auxiliary I/O mezzanine with multipurpose 12-bit 65 MS/s, 12-bit 130 MS/s DAC, and 14 digital front-panel I/O ports External trigger input High-speed digital I/O on P0 and P2 user-defined I/O Firmware Development Kit containing FPGA interface cores, software, and reference design FPGA-based VXS and optical data link interfaces for easier adaptation to different protocols Local FLASH memory to store multiple FPGA bitstreams for complex, multimode applications Device drivers for Windows, VxWorks, and Linux 2

3 High-Resolution, High-Sample-Rate Data Conversion with Real-Time Processing The Agilent Acqiris SVM3500 is based on a modular VME/ VXS platform common to all U1083A family products and features a quad-channel 12-bit coupled with a processing engine capable of up to 300 GigaMAC/s. The U1083A board family features two Xilinx Virtex-4 FPGAs, one SX55 targeted at digital signal processing, and one FX100 for data flow control. The embedded 128 MB FLASH memory allows the platform to be easily reconfigured to perform user defined applications. This architecture makes the new platform ideal for wideband, high-dynamic-range, demanding applications such as electronic warfare (EW), radar digital receiver, telecommunications, and semiconductor testing, where high resolution, high sample rate, high data-processing capabilities, and high throughput are mandatory. The SVM3500 module provides an analog mezzanine, based on four single-channel, 12-bit, state-of-the-art Texas Instruments ADS5463 s, and supports its full capabilities and performance. To allow channel interleaving and get dual-channel, 1 GS/s or single-channel, 2 GS/s acquisition modes, the MCK, a clock distribution chipset, is able to distribute four clock signals throughout the mezzanine either in phase, in anti-phase, or in quadrature with very low added jitter. Thanks to an externally accessible Lookup Table (LUT) correcting static offset and gain errors for each channel, and an implemented Finite Impulse Response (FIR) filter providing frequency dependent s gain and delay mismatch correction, outstanding interleaved analog performance can be reached from 10 MHz to 1 GHz input signal 1. The board supports eight Gbps serial links on the VXS backplane and two optical links on the front panel supporting up to Gbps, providing a substantial aggregate data bandwidth of more than 3.5 GB/s. It also includes a fully compliant VME64x interface supporting the 2eSST protocol. A comprehensive Firmware Development Kit (FDK), software drivers, and application examples make it easier to develop your applications. Distributed clock mode Maximum sampling rate Number of channels Module configuration In phase 4 Standard In anti-phase 1 GS/s 2 With external splitter In quadrature 2 GS/s 1 With external splitter Figure 1 : Block diagram showing the use of an external splitter in the case of the quadrature mode, resulting in a single-channel, 12-bit, 2 GS/s digitizer. 1) Requires the use of adequate external splitter. Please contact factory for more information. 3

4 Extended Functionality Trigger The external trigger circuitry includes a switchable 50 Ω/1 M Ω front end coupled with a very high-speed comparator chip and a 12-bit DAC for threshold adjustment. Processing clock distribution The COS201, a sophisticated proprietary clock distribution circuit, is used to synchronize all internal resources and allows fine control of processing and I/O synchronization. Analog mezzanines The SVM3500 features a four channel 12-bit, mezzanine based on four Texas Instruments ADS5463 s with an AC-coupled analog front end. Clock distribution An external clock input provides direct access to the MCK, a proprietary clock distribution circuit with very low added jitter. The MCK is able to generate four clocks, either in phase (4 channels at 500 MHz), in anti-phase (equivalent to 2 channels at 1 GS/s), or in quadrature (equivalent to 1 channel at 2 GS/s) 2. Data correction filter The mezzanine also includes a Finite Impulse Response (FIR) filter implemented on a Xilinx Virtex-5 SX50T FPGA. This filter is used in interleaved mode (anti-phase or quadrature clock) to correct frequency-dependant phase and amplitude mismatches between s. JTAG The SVM3500 features a JTAG connector that can be used for on board firmware debug using a ChipScope probe (requires option U1091A-CB1). Auxiliary I/O mezzanine The SVM3500 features an auxiliary I/O mezzanine to support control and command functions. It includes one 12-bit 65 MS/s, one 12-bit 130 MS/s DAC, and 14 digital I/Os. On-board processing FPGA The SVM3500 offers on-board, high-performance, real-time data processing by means of two very large FPGAs, one Xilinx Virtex-4 SX55 and one Xilinx Virtex-4 FX100. The SX55 FPGA is capable of executing 512 multiplications/accumulations (18x18) at up to 450 MHz, leading to an impressive processing power of 230 GigaMAC/s, while offering more than 55,000 logic cells and up to 5 Mbits of on-chip RAM. Optical data links Two SFP front-panel optical transceivers provide for data transfer at rates of up to Gbps per link. The link layer implemented by the provided firmware is based on Xilinx Aurora Protocol. 4

5 VME 2eSST interface The SVM3500 is fully VME64x and 2eSST compliant. Designed to benefit from fast data interfaces, it can be integrated with other state-of-the-art VME boards. Fast data throughput with large memories The MAC200 memory and acquisition controller is a digital CMOS integrated circuit. A high-speed data multiplexer/ demultiplexer with on-board memory, it is designed for the capture and memorization of 10-bit or 20-bit digital data, at speeds of up to 2 GS/s or the generation of 20-bit data streams at up to 1.2 GS/s. VXS VITA 41 interface The VXS VITA 41.0 standard gives the SVM3500 the veryhigh-data-throughput capability needed in EW, Radar, or ATE equipment. The eight serial links available on the P0 connector support up to Gbps each, for an aggregate throughput of up to 2.5 GBytes/s. Protocols such as RapidIO, PCI-EXPRESS, Infiniband, or Gigabit Ethernet, as defined in the VITA 41 dot-standards, can be supported through off-the-shelf FPGA IP cores. On-board communication controller FPGA The Xilinx Virtex-4 FX100 FPGA is capable of executing up to 160 multiplications/accumulation (18x18) at up to 450 MHz, leading to an impressive processing power of 70 GigaMAC/s while offering more than 94,000 logic cells and up to 6.7 Mbits of on-chip RAM. Moreover, the FX100 includes two PPC cores and four 10/100/1000 Ethernet MAC blocks. The on-board FPGA-based Signal Processing Unit allows the platforms to be easily reconfigured to perform user-defined, on-board, realtime signal processing Large memory The Xilinx Virtex-4 FX100 interfaces to two banks of DDR2-533 SDRAM, 32 MWords, each 64-bit wide, for a total of 512 MB. Figure 2 : Agilent SVM3500 quad-channel digitizer. 2) Please contact factory for more information. 5

6 Data-Flow-Optimized Architecture The VME/VXS board family has been designed to optimize both internal and external data throughput. Associated with other members of the family, the SVM3500 allows the construction of complete systems with fewer resources. ExtTrig COS201 CLK CLR SC SC PCI Interface FPGA + FLASH C TSI148 VME 2eSST VXS P0 P0/P2 I/O MCK FPGA SX50T Data Mux FIR Correction Analog Mezzanine A C C C SerDes IO B MAC200 D D1 Y Processing FPGA Communication FPGA SX55 FX100 C A B MAC200 D D2 Y AuxIO SerDes Hsbus 1 to 4 Hsbus 1 to 4 DDR2 SDRAM 32MW 64-bit DDR2 SDRAM 32MW 64-bit Auxiliary I/O Std: (/DAC/Digital) Optical Data Links 2 x SFP Standard [LNK]: Gbit/s [L25 Option]: 2.5 Gbit/s Figure 3 : SVM3500 architecture. High-Resolution, High-Sample-Rate Data Acquisition Mezzanine The SVM3500 digitizer s analog mezzanine implements four 12-bit, Texas Instruments ADS5463 s. The presence of the MCK, distributing the external clock throughout the mezzanine either in phase, in anti-phase, or in quadrature with very low added jitter and the implementation of a dynamic data correction filter (FIR) in a Xilinx Virtex-5 SX50T FPGA provide sensational performance. Coupled with the use of an external splitter, they allow channel interleaving to get a dual-channel, 12-bit, 1 GS/s or a single-channel, 12-bit, 2 GS/s acquisition mode, while maintaining outstanding analog operation. In 4 AC-Coupled Input Flash Xilinx XCF32P DAC In 3 AC-Coupled Input D0 SelectMap B0PORT Ext Clk AC-Coupled Input MCK DAC DAC D1 MCK D2 SX50T FPGA FE0_SPI B1PORT In 2 AC-Coupled Input D3 FE1_SPI C0SCLK DAC In 1 AC-Coupled Input 66 MHz Figure 4 : Analog mezzanine architecture. Analog Mezzanine 6

7 Easy Custom Application Development Firmware development kit The U1083A board family is available with an optional Firmware Development Kit (FDK) to make application development easier on the SX55 and FX100 FPGAs. The FDK includes a set of cores to easily interface to the underlying hardware, a base design for each family member to provide very simple, ready-to-use designs, and a test-bench environment for design and simulation. An embedded FLASH memory can store up to seven bitstreams for each FPGA for complex, multimode applications. SX55 FX100 Optical Data Links VXS Links O Bus 1 O Bus 2 D Port Interface A D Port Interface B Auxiliary I/O Resources User Defined Processing Block High Speed Bus 1 to 4 High Speed Bus 1 to 4 TX FIFO MGT RX FIFO Link Controller TX FIFO MGT User Defined Communications Block RX FIFO Aurora Controller Data Link Interface DDR2 SDRAM controller A WR Buffer DDR2 SDRAM controller A WR Buffer RD Buffer RD Buffer DDR2 SDRAM bank A DDR2 SDRAM bank B Local Bus Interface User Reg. Sys Reg. Local Bus Interface User Reg. Sys Reg. Digital I/O C Bus Figure 5 : Firmware development kit architecture. C Bus MicroDriver Software The SVM3500, is supplied with MicroDriver, a C standard compliant software driver. It runs on standard operating systems, as well as on Real-Time operating systems: MicroDriver supports VxWorks (Pentium and PowerPC), Linux (Pentium and PowerPC), and Windows (Pentium). MicroDriver has been specially designed for the U1083A family products so that every single line of code is useful, implying a very low footprint driver, that can even be reduced further to include only the needed SVM3500 module functionalities. MicroDriver is provided as full source code and gives direct access to the module registers, as well as main components, including FLASH and DDR2 memories, FPGAs, and back-plane and front-panel links. MicroDriver works in conjunction with the PCI to VME bridge device driver of the host to provide VME burst transfers (including 2eSST) and interrupts. 7

8 High-Fidelity Frequency-Related Measurements Agilent know-how in digitizer development combined with extensive use of application specific technologies provides high-fidelity measurement over the full input bandwidth. Innovative design, careful circuit layout and custom ICs are all used to optimize analog performance. SFDR [dbc] Dynamic range in standard configuration SNR [dbc] Noise in standard configuration Figure 6 : Typical SFDR for each channel at SR and -1 dbfs input signal as a function of frequency. THD [dbc] Harmonic distortion in standard configuration Figure 7 : Typical harmonic distortion for each channel at SR and -1 dbfs input signal as a function of frequency. Figure 8 : Typical SNR for each channel at SR and -1 dbfs input signal as a function of frequency. ENOB [LSB] Effective bits in standard configuration Figure 9 : Typical ENOB for each channel at SR and -1 dbfs input signal as a function of frequency. Gain [db] Frequency response Figure 10 : Typical analog input bandwidth. 8

9 Dynamic range in interleaved configuration Noise in interleaved configuration SFDR [dbc] SNR [dbc] Figure 11 : Typical SFDR in interleaved mode at 2 GS/s SR and -1 dbfs input signal as a function of frequency. The action of the FIR is remarkable. 50 Figure 13 : Typical SNR in interleaved mode at 2 GS/s SR and -1 dbfs input signal as a function of frequency. THD [dbc] Harmonic distortion in interleaved configuration -85 Figure 12 : Typical harmonic distortion in interleaved mode at 2 GS/s SR and -1 dbfs input signal as a function of frequency. ENOB [LSB] Effective bits in interleaved configuration Figure 14 : Typical ENOB in interleaved mode at 2 GS/s SR and -1 dbfs input signal as a function of frequency. The action of the FIR is remarkable. 9

10 Acqiris High-Speed VME/VXS Data Converters Model SVM3500 Quad-channel, 12-bit, digitizer Signal input Bandwidth (-3 db) 1 MHz to >2 GHz Input voltage ± 1.1 V DC (10.83 dbm) Coupling AC (1 MHz LF limit) VSWR (typ.) < 1.5 DC to 3 GHz Impedance 50 Ω ± 1% at 10 MHz Connectors SMA, gold-plated System performance All values for signal input frequencies from 10 MHz to 925 MHz In-phase mode (max. ) SFDR (typ.) >56 dbc THD (typ.) >56 db SNR (typ.) >61 dbc ENOB (typ.) >10 for f in = 10 MHz to 500 MHz >8.7 for f in = 500 MHz to 925 MHz External clock input Input amplitude > 500 mv pk-pk into 50 Ω Maximum input voltage ±2 V DC Ext. clock frequency from 500 MHz to 2 GHz Connector SMA, nickel-plated Time base Acquisition modes Continuous / software triggered Digital conversion Sample rate External clock only: 500 MHz to 2 GHz Acquisition modes - In phase: Sampling Rate = ¼ external clock - In anti-phase: Sampling Rate = ½ external clock - In quadrature: Sampling Rate = external clock Channels Four Two (with external splitter) One (with external splitrer) Resolution 12 bits (1:4096) Anti-phase mode 3 (max.1 GS/s) SFDR (typ.) >56 dbc THD (typ.) >56 db SNR (typ.) >59 dbc ENOB (typ.) >9.6 for f in = 10 MHz to 500 MHz >8.6 for f in = 500 MHz to 925 MHz Quadrature mode 3 (max.2 GS/s) SFDR (typ.) >56 dbc THD (typ.) >56 db SNR (typ.) >59 dbc ENOB (typ.) >9.6 for f in = 10 MHz to 500 MHz >8.6 for f in = 500 MHz to 925 MHz Trigger (external) Sensitivity Sensitivity > 5% Full Scale DC to 1 GHz at 50 Ω DC to 300 MHz at 1 MΩ Impedance 50 Ω ±1%, 1 MΩ at DC Connector SMA, gold-plated Full scale ±5 V Modes Edge, positive and negative 10 3) Performances in interleaved modes require an external calibration process and are measured at calibrated temperature.

11 Auxiliary I/O Digital signals 14 I/O configurable as 7 LVDS pairs μdb15 connector One digital I/O LVTTL 3.3V, 5V tolerant, MMCX, gold-plated connector (I/O P1) Analog input 12-bit 65 MS/s ± 1 V DC 50 Ω input MMCX, gold-plated connector Analog output 12-bit 130 MS/s DAC ± 1 V DC into 50 Ω MMCX, gold-plated connector On board memory FLASH 128 MB SDRAM 2 x 256 MB DDR2 533 Optical data links Transceiver 2 x Small Form Pluggable Multimode 850 nm Connector LC Duplex Throughput Gbps/link Option 2.5 Gbps/link Host interface VME Full VME64x and 2eSST compliance VXS 8 x serial links on P Gbps/link Aggregate: up to 25 Gbps Option 2.5 Gbps/link Digital IO 12 LVDS pairs on P0 20 LVDS pairs on P2 One SPI interface on P2 Supported host and OS 4 Single board computers Kontron : PowerNode3, PowerEngine (Linux, VxWorks) PentXM, PentXM2 (Linux) Concurent Technologies: VP337 (Linux) VP426 (WinXP) GE Fanuc: V7812 (WinXP) Interfaces GE Fanuc Bus Adapter 810 (WinXP) General and physical Power consumption < 80 W typ. Dimensions 6U VME standard mm x 160 mm x mm Front panel complies with IEEE Certification and Compliance Current requirements (typ.) V 0.8 A +5 V 7.1 A +3.3 V 8.4 A -12 V A EMC Complies with European EMC directive 2004/108/EC - IEC/EN CISPR Pub 11 Group 1, class A - AS/NZS CISPR 11 - ICES/NMB-001 This ISM device complies with Canadian ICES-001. Cet appareil ISM est conforme à la norme NMB-001 du Canada. Warranty 1 year Environmental 6 Operating temperature 0 to 60 C Non operating temperature -40 to 85 C Required airflow >2 m/s at sea level Altitude -1,000 to 15,000 ft Shock/Vibration - Operating random vibration - type tested at 5 to 2000 Hz, 7.6 g RMS (VITA 47 Class V2) - Survival random vibration - type tested at 5 to 500 Hz, 2.09 g RMS - Functional shock - type tested, halfsine, 30 g, 11 ms Humidity Relative Humidity type-tested at 95%, +40 C (non-condensing) 4) For other configurations, please contact factory. 5) SVM3500 sampling at, FPGA with base design. Depending on FPGA customer usage. 6) Samples of this product have been type tested in accordance with the Agilent Environmental Test Manual and verified to be robust against the environmental stresses of Storage, Transportation and End-use; those stresses include but are not limited to temperature, humidity, shock, vibration, altitude and power line conditions. Test Methods are aligned with IEC and levels are similar to MIL-PRF-28800F Class 3. 11

12 Contacts Ordering Information Americas Canada (877) Latin America United States (800) Asia Pacific Australia China Hong Kong India Japan 0120 (421) 345 Korea Malaysia Singapore Taiwan Thailand Model U1083A-005 U1083A-FDK Options U1083A-LNK U1083A-L25 Accessories U1092A-CB1 U1091A-CB1 Description Quad-channel, 12-bit SVM3500 digitizer module Firmware development kit for VME-VXS platform Standard data link 2.5 Gbps VXS and front panel links MMCX to BNC, 1 m cable Chipscope cable and connector Europe & Middle East Austria Belgium 32 (0) Denmark Finland 358 (0) France * *0.125 /minute Germany Ireland Israel /544 Italy Netherlands 31 (0) Spain 34 (91) Sweden Switzerland United Kingdom 44 (0) Other European Countries: Revised: July 2, 2009 For more information on Acqiris product line, sales or services, see our website at: For more information on Agilent, go to: Windows is a U.S. registered trademark of Microsoft Corporation. Pentium is a U.S. registered trademark of Intel Corporation. PCI Express and PCIe are registered trademarks of PCI-SIG. Product specifications and descriptions in this document subject to change without notice. Agilent Technologies, Inc Printed in USA, August 14, EN