Specification of Vacuum Fluorescent Display NORITAKE ITRON CORPORATION Sheet 1/19 DS25404

Transcription

1 Specification of Vacuum Fluorescent Display NORITAKE ITRON CORPORATION Sheet 1/19 DS2544 Rev. Spec. No. Date(M-D-Y) Item No. P-R Aug-1-7 DS1625M 1 P-R1 Dec P-R2 Dec T-R Dec T-R1 Jan T-R2 May-15-8 Index 1. Absolute Maximum Ratings 2. Recommended Operating Conditions 3. Electrical and Optical Characteristics 4. Example of Drive Circuit 5. PIN Description 6. Pin Assignment 7. Functional Descriptions 7.1. Instruction table 7.2. Display Clear 7.3. Cursor Home 7.4. Entry Mode Set 7.5. Display ON/OFF 7.6. Cursor / Display shift 7.7. Function Set Brightness Control 7.8. Set CG RAM Address 7.9. Set DD RAM Address 7.1. Write Data Read Data Read Busy Flag/Address Counter 8. Other Features 8.1. CG RAM 8.2. Power-on reset 9. Character Font 9.1. Japanese Character 9.2. European Character 1. Serial Data Transfer 11. Interface Timing 12. Pattern Assignment 13. Outer Dimension

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3 DS1625M Sheet 3/19 3. Electrical and Optical Characteristics At typical operating condition, all segments turned on, Ef=3Vdc, VDD1=5Vdc, VDD2=4, Ek=1.5Vdc, Vss=V unless otherwise noted. Ratings Parameter Symbol Test Condition Unit MIN TYP MAX Filament Current If VDD1=VDD2=V madc Logic Supply Current 1) IDD1 VDD1=5Vdc ma Display Supply Current 1) IDD2 Average ma High Level Input Current IIH VIN=VDD1 2-5 μa Low Level Input Current IIL VIN=GND 2-5 μa Logic H-Level Output Voltage VOH IOH=4mA VDD V Logic L-Level Output Voltage VOL IOL=4mA V Operation Frequency fosc R=2KΩ C=.1μF KHz HOSC1 Output Frequency fhosc /8 fosc - KHz HOSC2 Output Frequency fhosc /12 fosc - KHz Luminance 2) L [G] Ta=2 35 (7) - cd/m 2 Color of illumination Green [G] Notes: 1) After ES is verified, the value might be reviewed. Please acknowledge it beforehand. 2) ( ) : The numerical value in parentheses is a reference value. 3) Slow rise up power supply may cause a failure of Power-on reset which is explained in "8.2 Power-on reset". Caution Avoiding unexpected working because of rising environmental temperature, consider to dissipate the heat. Precautions should be taken to minimize the possibility of static charges occurring during handling and assembly of the VFDs. Avoiding burn-in problem because of fixed pattern, scroll, screen saver or sleep functions are recommended. Announcement This specification is subject to change without prior notice.

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5 DS1625M 5. PIN Description Function Strobe Pin Symbol STB Description Strobe Input Pin. STB signal needs to input each cycle. Reset Pin RST When this pin is set to "", all internal registers and commands are initialized. Internal pull-up resister Oscillation Frequency Control Pin Frequency Output Pin 1 Frequency Output Pin 2 OSCI HOSC1 HOSC2 When display ON, it's output 1/8 fosc. When display OFF/Reset, it's output LOW level. When display ON, it's output 1/12 fosc. When display OFF/Reset, it's output LOW level. Filament Voltage Input F(+), F(-) Logic Supply Voltage Input Display Supply Voltage Input Test Pin T1 This pin must be connected to VDD1. Ground Vss No Connection NC No Pin NP No Pin 6. Pin Assignment F(+) F(+) F(+) NP HOSC2 HOSC1 T1 NC OSCI RST SI/SO STB SCK VDD1 Vss Vss VDD2 NP NP F(-) F(-) F(-)

6 DS1625M 7. Functional Descriptions 7.1. Instruction table Code Instructions RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB Clear Display 1 Time 1s MAX. Description Clear all Display and sets DDRAM address at H. Cursor Home 1 J/E 1s Entry Mode Setting 1 I/D S 1s Display ON/OFF 1 D C B 1s Cursor or Display Shift 1 S/C R/L * * 1s (2s) Set DDRAM address at H. Also returns the display being shifted to the original position. DDRAM contents remain unchanged. Sets the cursor direction and specifies display shift. These operations are performed during writing/reading data. Sets all display ON/OFF (D), cursor ON/OFF (C), cursor blink of character position (B). Shifts display or cursor, keeping DDRAM contents. Function Setting 1 1 BR3 BR2 BR1 BR 1s CG RAM Address Setting DD RAM Address Setting Read Busy Flag & Address Write Data to CGRAM or DDRAM Read Data from CG RAM or DD RAM 1 1 ACG ADD 1s (2s) 1s (2s) 1 BF ACC 1s 1 Write Data 1s 1 1 Read Data 1s Sets the CG RAM address. Sets the DD RAM address. Reads busy flag (BF) and address counter. Writes data into CG RAM or DD RAM. Reads data from CG RAM or DD RAM. J/E="1" : 8HFFH set to Japanese font J/E="" : 8HFFH set to European font I/D = 1 : Increment BF = 1 : Busy I/D = : Decrement BF = : Not busy S = 1 : Display shift enabled S = : Cursor shift enabled DD RAM : Display data RAM S/C = 1 : Display shift CG RAM : Character generator RAM S/C = : Cursor move ACG : CG RAM address R/L = 1 : Shift to the right ADD : DD RAM address R/L = : Shift to the left ACC : Address Counter * : Don't care. ( ) : If RAM read is a next operation, needs execution time indicated by ( ).

7 DS1625M 7.2. Display Clear DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB 1 RS = 1. Fills all location in the display data (DD) RAM with 2H (Blank character). 2. Clears the contents of the address counter to H. 3. Sets the display for zero character shift. 4. Sets the address counter to point to the DD RAM. 5. If the cursor is displayed, moves the cursor to the left most character in the top line (Line 1). 6. Sets the address counter to increment on each access of DD RAM or CG RAM Cursor Home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB 1 J/E RS= 1. Clears the contents of the address counter to H. 2. Sets the address counter to point to the DD RAM. 3. Sets the display for zero character shift. 4. If the cursor is displayed, moves the left most character in the top line. (Line 1). 5. J/E bit could select Japanese or European font as below. J/E="1" : 8H to FFH set to Japanese font. J/E="" : 8H to FFH set to European font Entry Mode Set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB 1 I/D S RS = The I/D bit selects the way in which the contents of the address counter are modified after every access to DD RAM or CG RAM. I/D = 1 : The address counter is incremented. I/D = : The address counter is decremented. The S bit enables display shift, instead of cursor shift, after each write or read to the DD RAM. S = 1 : Display shift enabled. S = : Cursor shift enabled. The direction in which the display is shifted is opposite in sense to that of the cursor. For to DD RAM. However if S=1 and I/D=1, the display would shift one character to the left and the cursor would maintain its position on the panel.

8 DS1625M The cursor has already be shifted in the direction selected by I/D during reads of the DD RAM, irrespective of the value of S. Similarly reading and writing the CG RAM always shifts the cursor. Also both lines are shifted simultaneously. I/D S After writing DD RAM data The cursor moves one character to the left. The cursor moves one character to the right. The display shifts one character to the right without cursor s move. The display shifts one character to the left without cursor s move. After reading DD RAM data The cursor moves one character to the left. The cursor moves one character to the right. The cursor moves one character to the left. The cursor moves one character to the right Display ON/OFF DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB 1 D C B RS = This instruction controls various features of the display. The D bit turns the entire display on or off. D = 1 : Display on D = : Display off The C bit turns the cursor on or off. C = 1 : Cursor on C = : Cursor off The B bit enables blinking of the character the cursor coincides with. B = 1 : Blinking on B = : Blinking off Blinking is achieved by alternating between a normal and all on display of a character. The cursor blinks with a frequency of about 1 Hz and DUTY 5% Cursor / Display shift DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB 1 S/C R/L * * RS = *: Don t care This instruction shifts the display and/or moves the cursor, on character to the left or right, without reading nor writing DD RAM. The S/C bit selects movement of the cursor or movement of both the cursor and the display. S/C = 1 : Shift both cursor and display. S/C = : Shift cursor only.

9 DS1625M Sheet 9/19 The R/L bit selects leftward or rightward movement of the display and/or cursor. R/L = 1 : Shift one character right. R/L = : Shift one character left. Cursor move and Display shift by the Cursor/Display Shift. S/C R/L Cursor shift Display shift Move one character to the left Move one character to the right Shift one character to the left with display Shift one character to the right with display No shift No shift Shift one character to the left Shift one character to the right 7.7. Function Set Brightness Control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB 1 1 BR3 BR2 BR1 BR RS = *: Don t care BR3 to BR flags are used to modulate the pulse width of the internal BK thereby controlling the VFD brightness, please refer setting as below: BR3 BR2 BR1 BR Brightness 1.% Default % % % 1 75.% % % % 1 5.% % % % % % % %

10 DS1625M Sheet 1/ Set CG RAM Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB 1 ACG RS = 1. Loads a new 6-bit address into the address counter. 2. Sets the address counter to address CG RAM. Once the Sets CG RAM Address has been executed, the contents of the address counter will be automatically modified after every access of CG RAM, as determined by the 7.4 Entry Mode Set instruction. The active width of the address counter, when it is addressing CG RAM, is 6-bits so the counter will wrap around to H from 3FH if more than 64 bytes of data are written to CG RAM Set DD RAM Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB 1 ADD RS = 1. Loads a new 7-bit address into the address counter. 2. Sets the address counter to point to the DD RAM. Once the Set DD RAM Address instruction has been executed, the contents of the address counter will be automatically modified after each access of DD RAM, as selected by the 7.4 Entry Mode Set instruction. Valid DD RAM Address Ranges 1st line 2nd line Number of Characters 4 4 Address H to 27H 4H to67h 7.1. Write Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB DATA WRITE RS = 1 This instruction writes the data in DB7 to DB into either the CG RAM or the DD RAM. The RAM space (CG or DD), and the address in that space, that is accessed depends on whether a Set CG RAM Address or Set DD RAM Address instruction was last executed, and on the parameters of that instruction. The contents of the address counter will be automatically modified after each Write Data, as determined by the 7.4 Entry Mode Set. When data is written to the CG RAM, the DB7, DB6 and DB5 bits are not displayed as characters.

11 DS1625M Sheet 11/ Read Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB DATA READ RS = 1 This instruction reads data from either CG RAM or DD RAM, depending on the type of Set RAM Address instructions last sent. The address in that space depends on the Set RAM Address instruction parameters. Immediately before executing Read Data, Set CG RAM Address or Set DD RAM Address must be executed. The contents of the address counter are modified after each Read Data, as determined by the 7.4 Entry Mode Set. Display shift is not executed, as described at of the 7.4 Entry Mode Set Read Busy Flag/Address Counter DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB BF ACC RS = Reading the instruction register yields the current value of the address counter and the busy flag. This instruction must be executed prior to any other instructions. ACC, the address counter value, will point to a location in either CG RAM or DD RAM, depending on the type of Set RAM Address instruction last sent. In Busy Flag Check immediately after executing Write Data instruction, a valid address counter value can be ready as soon as BF goes low. The BF bit shows the status of the busy flag. BF = 1 : busy. BF = : ready for next instruction, command receivable.

12 DS1625M Sheet 12/19 8. Other Features 8.1. CG RAM The display module has CG RAM of 32 bit = (5x8 bit /char) x 8 chars which is for user definable character fonts. The character fonts consist of 5x7 dots. The number 1-35 corresponds to character fonts. Character Code H or (8H) 1H or (9H) CG RAM address CG RAM data (Character pattern) DB5 DB4 DB3 DB2 DB1 DB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB * * * * * * * * * * * * * * * * * * * * * * * * 36 1 * * * * * * * * * * * * * * * * * * * * * * * * 36 REMARKS; * : Don t care : Turned off 1 : Turned on Dot assignment

13 DS1625M Sheet 13/ Power-on reset Internal status of the VFD is initialized, when the controller detects the rising of power supply up. The status are as follows: 1. Display clear Fills the DD RAM with 2Hex (Space code). During executing of Display Clear (Max 1 μs), the busy flag (BF) is Sets the address counter to H. Sets the address counter to point the DD RAM. 3. Display ON/OFF D = : display OFF C = : Cursor OFF B = : Blink OFF 4. Entry Mode Set I/D = 1 : Increment (+1) S = : No display shift 5. Brightness Control BR to BR3 = : 1% Parameter Reset Time VDD1 Rising Time VDD1 OFF Width Detecter Voltage Symbol Min. Typ. Max. Unit tres μs trdd 1-1 ms toff ms Vdet V VDD1 trdd Vdet tres toff Busy Flag Remarks There is a possibility that reset doesn't work by slow start power supply. Therefore the initializing by commands needs.

14 DS1625M 9. Character Font 9.1. Japanese Character (J/E bit = "1") Sheet 14/19 D3 D2 D1 D D7 D6 D5 D A B C D E F A B 1 1 C D E F

15 DS1625M Sheet 15/ European Character (J/E bit = "") D3 D2 D1 D D7 D6 D5 D A B C D E F A B C D E F

16 DS1625M Sheet 16/19 1. Serial Data Transfer DATA WRITE STB SCK SI "1" "1" "1" "1" "1" R/W RS "" D7 D6 D5 D4 D3 D2 D1 D SYNCHRONUS BITS START BYTE INSTRUCTION/DATA DATA READ STB WAIT TIME : twait 1µs SCK SI/SO "1" "1" "1" "1" "1" R/W RS "" BF IR6 IR5 IR4 IR3 IR2 IR1 IR SYNCHRONUS BITS START BYTE READ DATA NOTE: STB signal needs to input each cycle. When STB signal is changed from "H" to "L", the data and command's access is began; When STB signal is changed from "L" to "H", the data and command's access is finished. So when you do not access any data or command, we suggest that you can keep the STB state in "H". The display might be flickered if character-codes are written very fast(nearby minimum value of the shift clock).

17 DS1625M Sheet 17/ Interface Timing Parameter Symbol Condition Min. Typ. Max. Unit Shift Clock Cycle High Level Shift Clock Pluse Width Low Level Shift Clock Pulse Width Shift Clock Hold Time Data Setup Time Data Hold Time STB Hold Time STB Pulse Width Wait Time Output Data Delay Time Output Data Hold Time Reset Pulse Width tcyk twhk twlk thstbk tds tdh tdkstb twstb twait todd todh twre SCK SCK SCK STB SCK Data SCK SCK Data SCK STB 8th CLK 1st CLK SCK Data SCK Data ns ns ns ns ns ns ns ns ns ns ns ns INPUT twstb STB thstbk tcyk twhk twlk tdkstb SCK tds tdh SI OUTPUT twstb STB thstbk tcyk twhk twlk tdkstb SCK todd todh SO

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