MAS060X. SATA III To Flash Controller. Data Sheet 2015 年 10 月. Document No.: DAT-0151-A01

Transcription

1 MAS060X SATA III To Flash Controller Data Sheet Document No.: DAT-0151-A 年 10 月

2 DAT-0151-A01 March 10, 2015, Maxio Technology (Hangzhou) Ltd. All Rights Reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the written permission of Maxio technology (Hangzhou) Ltd. Disclaimer Maxio reserves the right to make changes to its products, including the contents of this document, or to discontinue any product or service without notice. Maxio advises its customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied upon is current. Every effort has been made to keep the information in this document current and accurate as of the date of this document s publication or revision. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN AS IS BASIS. In no event will Maxio be liable for damages arising directly or indirectly from any use of the information contained in this document. For more information on Maxio products, please send to sales@maxio-tech.com. For product application support, please send to fae@maxio-tech.com. If you have signed a Disclosure Agreement that includes this document as part of its subject matter, please use this document in accordance with the terms of the agreement. If not, please destroy the document. Maxio Technology (Hangzhou) Ltd. 9F, E Building, No. 307, Liuhe Road, Binjiang District, Hangzhou, , Zhejiang, China. Tel: Fax: Page 1

3 1 General Description The MAS060X is a single chip, SATA III to NAND flash interface that supports external DDR3 DRAM. It was designed to provide a higher bandwidth for flash memory access. The MAS060X supports the latest NAND flash memory, including Toshiba/Sandisk 19 nm Type A/B/C/A19, IMFT 25 nm, 20 nm, and 16 nm. It also features an embedded hardware error correction code (ECC), wear-leveling, and bad block management technology. In order to resolve possible compatibility issues, the MAS060X possesses the ability to upgrade its firmware online. The MAS060X is composed of an embedded processor, an internal masked ROM, data SRAM, a SATA link/transport layer, and a SATA PHY. Data swap between different interfaces can be done very efficiently via DMA without the need for a CPU. 2 Features 2.1 SATA Compliant with Serial ATA International Organization: Serial ATA Revision 3.1 Supports 1-port 1.5/3.0/6.0 Gb/s SATA I/II/III interface Support ATA-8 Command Set 2.2 CPU 32 bits Embedded processor 32 KB Embedded masked program ROM 192 KB Embedded system RAM with ITCM 2.3 Flash Supports 8 CEs Flash per channel (max) Supports Toshiba 19 nm/a19 Flash Supports Intel and Micron 25/20/16 nm Flash Supports Toggle 2.0 and ONFi 3.0 mode Flash Enhanced endurance by dynamic/static wear-leveling Supports 8K/16K bytes page size Supports dynamic power management SMART (Self-Monitoring, Analysis, and Reporting Technology) Data integrity under power-cycling Supports BCH 40/60/72 bits ECC Support Shift read feature of NAND flash when ECC fail 2.4 SDRAM Supports one module DDR3 Support up-to 4Gbits 2.5 SYSTEM Integrated SATA III port and 4-channels Flash controller. LED indicator for SATA read/write access. (optional) Page 2

4 H/W Accelerator LED indicator for SATA PHY link up. (optional) Provides 22 GPIO pins for customer. Provides UART and JTAG for S/W debugging. Built-in power-up self-test (BIST). Manual and automatic self-diagnostics. Provides voltage low detect interrupt. 288-ball TFBGA package 2.6 Firmware Supports online SATA firmware update. Support 1/2/4/8 banks selected free. Support 1/2/3/4 channels selected free. 3 Block Diagram MAS060X JMF667 Flash I/F Flash Controller 1 & ECC engine SATA III I/F Bus SATA Controller SATA III PHY XTALI Flash I/F Flash Controller 4 & ECC engine GPIO Chip Configuration DRAM Controller CPU DATA RAM Mask RAM Program RAM GPIO Chip Config. DDR3 DRAM Figure 1 Block Diagram of MAS060X Page 3

5 4 Total Capacity Table 1 Total Capacity Table Density/per flash Support CE pins/per flash Maximum flash number Total capacity 1G x 8 Bits (8 Gb) 1 CE pin 4 32G Bytes 2G x 8 Bits (16 Gb) 1 / 2 CE pin 8 64G Bytes 4G x 8 Bits (32 Gb) 1 / 2 / 4 CE pin G Bytes 8G x 8 Bits (64 Gb) 1 / 2 / 4 CE pin G Bytes Density/per flash Support CE pins/per flash Maximum flash number Total capacity 2G x 8 Bits (16 Gb) 1 CE pin 4 64G Bytes 4G x 8 Bits (32 Gb) 1 / 2 CE pin 8 128G Bytes 8G x 8 Bits (64 Gb) 1 / 2 / 4 CE pin G Bytes 16G x 8 Bits (128 Gb) 1 / 2 / 4 CE pin G Bytes Page 4