How Good Is Your Memory? An Architect s Look Inside SSDs
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1 How Good Is Your Memory? An Architect s Look Inside SSDs Michael Abraham (mabraham@micron.com) Business Line Manager Micron Technology, Inc. August
2 Early Storage Optimizations µc NAND Camera SmartMedia Slow Early obsolescence Inexpensive solution Faster Upgradeable Slightly more expensive µc/ SRAM NAND CF/USB/SD August
3 High-Level SSD Architecture Firmware SATA / PCIe x2 / PCIe x4 C O N N E C T O R Host Vcc Power Management Ch0 µc NAND Ch(n-1) DRAM USA August
4 The Past Decade of Planar NAND Process Node (nm) Q1-06 Q2-06 Q1-07 Q2-07 Q1-08 Q2-08 Q1-09 Q3-09 Volume Production Dates The industry went through 7-9 NAND lithography transitions Q1-10 Q3-10 Q1-11 Q3-11 Q1-12 Q3-12 Q1-13 Q3-13 Q1-14 Q3-14 August Data based on publicly known information.
5 What Happened in That Decade? Density: 2Gb 128Gb per die Interface: 40MHz SDR 266MHz DDR Bits per Cell: SLC MLC TLC Planes: Page size: 2KB 16KB Block size: 128KB 8+MB Packaging: 1ch TSOP-48 4ch BGA ECC: 1-bit Hamming RS?/BCH LDPC Electrons per Cell State: > Engineering skill: 1 college kid 3+ PhDs August
6 Could We Scale Planar NAND Beyond 16nm? Lower cost per bit Higher ECC Longer array operations Less data retention Less endurance More PhDs August 18, 2015
7 3D NAND: Standing NAND on Its Head 3D NAND cell architecture enables significant performance improvement 3D NAND cost improvement over planar expands with subsequent nodes August 18, 2015
8 Electrons per level 1024 Distribution of cells August 18, D NAND Reliability Relative to Planar NAND Planar 3D 90nm 70nm 50nm 34nm 25nm 20nm 16nm Node 2D NAND (scaled) 3D NAND 3D NAND cell design simultaneously improves performance and reliability Vertical stacking allows large number of electrons per cell independent of scaling No longer relying on lithography to continue scaling Decreased interference between cells translates into higher cycling endurance Uses familiar memory materials CT or FG Vt
9 100% 3D NAND Enables New Die Densities NAND Flash TAM by Density (Units) 3D NAND in earnest here (256Gb) 90% 512Gb (64GB) 80% 256Gb (32GB) 70% 128Gb (16GB) 60% 64Gb (8GB) 50% 32Gb (4GB) 40% 16Gb (2GB) 30% 8Gb (1GB) 4Gb 20% 2Gb 10% 1Gb 0% Source: isuppli 2Q15 August
10 3D TLC NAND Goes Mainstream 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% SLC MLC TLC Standalone SLC is nearly non-existent Source: isuppli 2Q15 August
11 3D NAND Improves Array Performance Faster write bandwidth a result of larger number of data bytes per operation and a reduction in tprog SLC MLC-2 MLC-3 Data Bytes per Operation (Page Size * # of Planes) Sequential Programming Throughput (MB/s) August
12 ONFI 4 Results in Lower Energy MT/s Single Channel Package 1,600 1,400 1,200 1, Dual Channel Package ONFI 4.0 to be introduced with 3D NAND Interface up to 800MT/s throughput Reduces energy per bit with 1.2V interface 0 ONFI 1.0 ONFI 2.x ONFI 3.0 ONFI 4.0 NV-SDR NV-DDR NV-DDR2 NV-DDR3 August
13 What s New? Density: Introduction of 256Gb Interface: ONFI 4.0, 1.2V Bits per Cell: MLC, TLC with SLC modes Electrons per Cell State: ~200 Page/block/plane architecture follow traditional NAND scaling path Engineering skill: 1 college kid 3+ PhDs August
14 Why So Long to 3D NAND?! NAND Cost of Transition requires considerably new tooling Transition CapEx/Wafer 25nm 20nm 16nm 3D Gen A USA August
15 Questions? August
16 About Michael Abraham Business Line Manager in the Storage Business Unit at Micron Former NAND Architect Covers emerging memories and 3D XPoint IEEE Senior Member BS degree in Computer Engineering from Brigham Young University Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron s production data sheet specifications. Information, products and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. August
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