Intel 925X and 925XE Express Chipset Memory Configuration Guide

Transcription

1 ntel 925X and 925XE Express Chipset emory Configuration Guide White Paper November 24 ocument Number:

2 NFORATON N THS OCUENT S PROVE N CONNECTON WTH NTEL PROUCTS. NO LCENSE, EXPRESS OR PLE, BY ESTOPPEL OR OTHERWSE, TO ANY NTELLECTUAL PROPERTY RGHTS S GRANTE BY THS OCUENT. EXCEPT AS PROVE N NTEL S TERS AN CONTONS OF SALE FOR SUCH PROUCTS, NTEL ASSUES NO LABLTY WHATSOEVER, AN NTEL SCLAS ANY EXPRESS OR PLE WARRANTY, RELATNG TO SALE AN/OR USE OF NTEL PROUCTS NCLUNG LABLTY OR WARRANTES RELATNG TO FTNESS FOR A PARTCULAR PURPOSE, ERCHANTABLTY, OR NFRNGEENT OF ANY PATENT, COPYRGHT OR OTHER NTELLECTUAL PROPERTY RGHT. ntel products are not intended for use in medical, life saving, or life sustaining applications. ntel may make changes to specifications and product descriptions at any time, without notice. esigners must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." ntel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The ntel 925X and 925XE Express chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local ntel sales office or your distributor to obtain the latest specifications and before placing your product order. Φ ntel Extended emory 64 Technology (ntel E64T) requires a computer system with a processor, chipset, BOS, operating system, device drivers and applications enabled for ntel E64T. Processor will not operate (including 32-bit operation) without an ntel E64T-enabled BOS. Performance will vary depending on your hardware and software configurations. See for more information including details on which processors support E64T or consult with your system vendor for more information. ntel, Pentium and the ntel logo are trademarks or registered trademarks of ntel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 24, ntel Corporation 2

3 Contents Overview emory Technology Supported llegal Configurations Valid Front Side Bus and emory Speeds ECC Support Latency Support ntel 925X and 925XE Express Chipset emory Organization and Operating odes... 9 Figures 2. Single-Channel ual-channel Asymmetric ual-channel Symmetric ixed RA emory Speeds... 2 Figure. Single-Channel emory ode... Figure 2. ual-channel Asymmetric emory ode... Figure 3. ual-channel Symmetric emory ode... Figure 4. System emory ode Styles... 2 Tables Table. emory Technology Support... 6 Table 2. Valid emory Configurations... 6 Table 3. emory Latency Configurations

4 Revision History Revision Number escription Revision ate - nitial public release June 24-2 Added ntel E64T Support nformation August 24-3 Added ntel 925XE Express chipset information November 24 4

5 Overview The ntel 925X and 925XE Express chipset emory Controller Hub (CH) is ntel s first dualchannel R2 emory Controller Hub with ntel Flex emory Technology. ntel has enhanced its memory architecture design to allow for maximum configuration flexibility while providing optimal performance when combined with R2-533 and an ntel Pentium 4 processor in the Land Grid Array 775 (LGA775) package with 8 Hz front side bus. Note: nformation pertaining only to the ntel 925XE Express chipset emory Controller Hub (CH) features will be italicized in this document. For great workstation application flexibility, the ntel 925X and 925XE Express chipset is specifically designed to support ntel Extended emory 64 Technology Φ (ntel E64T) enabling 64-bit memory addressability. Select versions of the Pentium 4 processor support ntel E64T as an enhancement to ntel's A-32 architecture on workstation platforms. This enhancement enables the processor to execute operating systems and applications written to take advantage of ntel E64T. Further details on the 64-bit extension architecture and programming model can be found in the ntel Extended emory 64 Technology Software eveloper Guide at Φ ntel Extended emory 64 Technology (ntel E64T) requires a computer system with a processor, chipset, BOS, operating system, device drivers and applications enabled for ntel E64T. Processor will not operate (including 32-bit operation) without an ntel E64T-enabled BOS. Performance will vary depending on your hardware and software configurations. See for more information including details on which processors support E64T or consult with your system vendor for more information. This document details the 925X and 925XE Express chipset CH memory configurations and organization. t is intended for a technical audience interested in learning about the simplified population rules introduced by ntel Flex emory Technology and the 925X and 925XE Express chipset CH platform. This document will provide background regarding the supported memory technologies and configurations, and then discuss styles of memory organization and operation.. emory Technology Supported The 925X and 925XE Express chipset emory Controller Hub (CH) supports R2 ECC and non-ecc s and memory technologies in the following configurations R2-4 (PC32), R2-533 (PC43) 5

6 Table. emory Technology Support RA Technology Smallest ncrements (One SS ) Largest ncrements (One S ) aximum Capacity (Four S s) 256 b 28 B 52 B 248 B 52 b 256 B 24 B 496 B Gb 52 B 2 B 8 B (Note ) NOTES:. This exceeds a 32-bit address limit of 4 GB. n a 32-bit system, only the first 4 GB of memory will be accessible..2 llegal Configurations The following configurations are not valid with the 925X and 925XE Express chipset CH: 64-b, 28-b, 2-Gb, and 4-Gb emory Technologies for R2 x4, x32 s ouble-sided x6 s Registered s R s.3 Valid Front Side Bus and emory Speeds Table 2. Valid emory Configurations FSB RA ata Rate RA Type Single Channel Peak Bandwidth ual Channel Peak Bandwidth 8 Hz 4 T/s R2 - RA 3.2 GB/s 6.4 GB/s 8 Hz 533 T/s R2 - RA 4.25 GB/s 8.5 GB/s.4 ECC Support The 925X and 925XE Express chipset CH supports single-bit Error Correcting Code (or Error Checking and Correcting) on the main memory interface. The CH generates an 8-bit code for each 64-bit qword of memory..5 Latency Support The 925X and 925XE Express chipset CH supports the following latency timings on the main memory interface. 6

7 Table 3. emory Latency Configurations RA ata Rate tcl trc trp Units Notes 4 T/s tck 925XE only () 4 T/s tck 533 T/s tck 925XE only () 533 T/s tck 533 T/s tck NOTES: VCCS voltage must be.9 V nominal in order to support latency timings of for 533 T/s 7

8 8 R

9 2 ntel 925X and 925XE Express Chipset emory Organization and Operating odes The 925X and 925XE Express chipset CH memory interface is designed with Flex emory Technology where it can be configured to support single-channel or dual-channel R2 memory configurations. epending upon how the s are populated on each system memory channel, a number of different configurations can exist for R2: Single Channel only one channel of memory is routed and populated, or if two-channels of memory are routed, but only one channel is populated; can be either channel A or channel B. ual Channel Asymmetric both channels are populated, but each channel has a different amount (B) of total memory. ual Channel Symmetric both channels are populated where each channel has the same amount (B) of total memory. The following sections explain and show the different memory configurations that are supported by the 925X and 925XE Express chipset. 9

10 2. Single-Channel The system will enter single-channel mode when only one channel of memory is routed on the motherboard, or if two-channels of memory are routed, but only one channel is populated. n this configuration, all memory cycles are directed to a single channel. Figure. Single-Channel emory ode 2.2 ual-channel Asymmetric This mode is entered when both memory channels are routed and populated with different amounts (B) of total memory. This configuration allows addresses to be accessed in series across the channels starting in channel A until the end of its highest rank, then continue from the bottom of channel B to the top of the rank. Real world applications are unlikely to make requests that alternate between addresses that sit on opposite channels with this memory organization, so in most cases, bandwidth will be limited to that of a single channel. Figure 2. ual-channel Asymmetric emory ode ntel 925X & 925XE CH 52 B B 52 B 256 B ntel 925X & 925XE CH 52 B 52 B GB 52 B B 256 B B 52 B

11 2.3 ual-channel Symmetric This mode allows the end user to achieve maximum performance on real applications by utilizing the full 64-bit dual-channel memory interface in parallel across the channels with the aid of ntel Flex emory Technology. The key advantage this technology brings is that the end user is only required to populate both channels with the same amount (B) of total memory to achieve this mode. The RA component technology, device width, device ranks, and page size may vary from one channel to another. Addresses are ping-ponged between the channels, and the switch happens after each cache line (64-byte boundary). f two consecutive cache lines are requested, both may be retrieved simultaneously, since they are guaranteed to be on opposite channels. Figure 3. ual-channel Symmetric emory ode ntel 925X & 925XE CH 52 B B 52 B 52 B ntel 925X & 925XE CH 256 B 256 B 52 B 52 B B 52 B B 52 B

12 Figure 4. System emory ode Styles 2.4 ixed RA emory Speeds The 925X and 925XE Express chipset CH will accept mixed R2 speed populations, assuming the SPs on the s are programmed with the correct information and the BOS is programmed as outlined in ntel s BOS reference code. n all operating modes (Single-Channel, ual Channel Asymmetric, and ual-channel Symmetric) the frequency of the System emory will be set to the lowest frequency of all s populated in the system, as determined through the SP registers on the s. Example number one, a R2-533 installed with a R2-4 should run at 4 Hz. The R2-533 should downshift to R2-4 timings, thus allowing the system to run at 4 Hz speeds. The R2-533 will only downshift to R2-4, if the timings for R2-4 are programmed in the R2-533 s SP. Example number two, a R installed with a R should run at 533 Hz with timings with VCCS set at.8v nominal. The R should downshift to timings and the VCCS voltage on the platform should run at.8 V nominal. 2