R8C/11 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER. 1. Overview. 1.1 Applications

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1 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.50 Apr 27, Overview This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated itructio featuring a high level of itruction efficiency. With 1M bytes of address space, it is capable of executing itructio at high speed. 1.1 Applicatio Electric household appliance, office equipment, housing equipment (seor, security), general industrial equipment, audio, etc. Rev.1.50 Apr 27, 2005 page 1 of 26

2 1. Overview 1.2 Performance Outline Table 1.1. lists the performance outline of this MCU. Table 1.1 Performance outline Item Performance CPU Number of basic itructio 89 itructio Shortest itruction execution time 50 (f(xin) = 20 MHZ, CC = 3.0 to 5.5 ) 100 (f(xin) = 10 MHZ, CC = 2.7 to 5.5 ) Operating mode Single-chip Address space 1M bytes Memory capacity See Table 1.2. Peripheral Interrupt Internal: 11 factors, External: 5 factors, function Software: 4 factors, Priority level: 7 levels Watchdog timer 15 bits x 1 (with prescaler) Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel, Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel Circuits of input capture and output compare. Serial Interface 1 channel Clock synchronous, UART 1 channel UART A/D converter 10-bit A/D converter: 1 circuit, 12 channels Clock generation circuit 2 circuits Main clock generation circuit (Equipped with a built-in feedback resistor) On-chip oscillator (high speed, low speed) On high-speed on-chip oscillator the frequency adjustment function is usable. Oscillation stop detection function Stop detection of main clock oscillation oltage detection circuit Included Power on reset circuit Included Port Input/Output: 22 (including LED drive port), Input: 2 (LED drive I/O port: 8) Electrical Power supply voltage CC = 3.0 to 5.5 (f(xin) = 20 MHZ) characteristics CC = 2.7 to 5.5 (f(xin) = 10 MHZ) Power coumption Typ. 9 ma (CC = 5.0, (f(xin) = 20 MHZ, High-speed mode) Typ. 5 ma (CC = 3.0, (f(xin) = 10 MHZ, High-speed mode) Typ. 35 µa (CC = 3.0, Wait mode, Peripheral clock stops) Typ. 0.7 µa (CC = 3.0, Stop mode) Flash memory Program/erase voltage CC = 2.7 to 5.5 Number of program/erase 100 times Operating ambient temperature -20 to 85 C -40 to 85 C (D-version) Package 32-pin plastic mold LQFP Rev.1.50 Apr 27, 2005 page 2 of 26

3 1. Overview 1.3 Block Diagram Figure 1.1 shows this MCU block diagram I/O port Port P0 Port P1 Port P3 Port P4 Peripheral functio Timer Timer X (8 bits) Timer Y (8 bits) Timer Z (8 bits) Timer C (16 bits) A/D converter (10 bits 12 channels) UART or Clock synchronous serial I/O (8 bits 1 channel) UART (8 bits 1 channel) R8C Series CPU core System clock generator XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator Memory Watchdog timer (15 bits) R0H R1H R2 R3 R0L R1L A0 A1 FB SB USP ISP INTB PC FLG ROM (Note 1) RAM (Note 2) Multiplier Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. Figure 1.1 Block Diagram Rev.1.50 Apr 27, 2005 page 3 of 26

4 1. Overview 1.4 Product List Table 1.2 lists the products. Table 1.2 Product List Type No. R5F21112FP R5F21113FP R5F21114FP R5F21112DFP R5F21113DFP R5F21114DFP As of April 2005 ROM capacity RAM capacity Package type Remarks 8K bytes 12K bytes 16K bytes 8K bytes 12K bytes 16K bytes 512 bytes 768 bytes 1K bytes 512 bytes 768 bytes 1K bytes PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A Flash memory version D version Type No. R 5 F D FP Package type: FP : PLQP0032GB-A Shows characteristics and others. D: Operating ambient temperature 40 C to 85 C No symbol: Operating ambient temperature 20 C to 85 C ROM capacity: 2 : 8 KBytes. 3 : 12 KBytes. 4 : 16 KBytes. R8C/11 group R8C/Tiny series Memory type: F: Flash memory version Renesas MCU Renesas semiconductors Figure 1.2 Type No., Memory Size, and Package Rev.1.50 Apr 27, 2005 page 4 of 26

5 1. Overview 1.5 Pin Configuration Figure 1.3 shows the pin configuration (top view). PIN CONFIGURATION (top view) R8C/11 Group P45/INT0 P10/KI0/AN8/CMP00 P11/KI1/AN9/CMP01 P12/KI2/AN10/CMP02 P13/KI3/AN11 P14/TxD0 P15/RxD0 P16/CLK P37/TxD10/RxD1 CNSS RESET XOUT/P47 (Note 1) SS XIN/P46 CC P17/INT1/CNTR0 P07/AN0 ICC P30/CNTR0/CMP10 ASS P31/TZOUT/CMP11 ACC/REF P32/INT2/CNTR1/CMP12 P33/INT3/ TCIN P06/AN1 P05/AN2 P04/AN3 MODE P03/AN4 P02/AN5 P01/AN6 P00/AN7/TxD11 Notes: 1. P47 functio only as an input port. 2. When using On-chip debugger, do not use pi P00/AN7/TxD11 and P37/TxD10/RxD1. 3. Do not connect Icc to cc. Package: PLQP0032GB-A (32P6U-A) Figure 1.3 Pin Configuration (Top iew) Rev.1.50 Apr 27, 2005 page 5 of 26

6 1. Overview 1.6 Pin Description Table 1.3 shows the pin description Table 1.3 Pin description Signal name Pin name I/O type Power supply cc, I input ss Icc Icc O Analog power Acc, Ass I supply input Reset input RESET I CNss CNss I MODE MODE I Main clock input XIN I Main clock output XOUT INT interrupt input INT0 to INT3 I Key input interrupt KI0 to KI3 I Timer X CNTR0 I/O CNTR0 O Timer Y CNTR1 I/O Timer Z TZOUT O Timer C TCIN I CMP00 to CMP03, O CMP10 to CMP13 Serial interface CLK0 I/O RxD0, RxD1 I TxD0, TxD10, O TxD11 Reference voltage REF I input A/D converter AN0 to AN11 I I/O port P00 to P07, I/O P10 to P17, P30 to P33, P37, P45 Input port P46, P47 I O Function Apply 2.7 to 5.5 to the cc pin. Apply 0 to the ss pin. This pin is to stabilize internal power supply. Connect this pin to ss via a capacitor (0.1 µf). Do not connect to cc. These are power supply input pi for A/D converter. Connect the Ass pin to ss. Connect a capacitor between pi Acc and Ass. L on this input resets the MCU. Connect this pin to ss via a resistor. Connect this pin to cc via a resistor. These pi are provided for the main clock generating circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pi. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. These are INT interrupt input pi. These are key input interrupt pi. This is the timer X I/O pin. This is the timer X output pin. This is the timer Y I/O pin. This is the timer Z output pin. This is the timer C input pin. These are the timer C output pi. This is a trafer clock I/O pin. These are serial data input pi. These are serial data output pi. This is a reference voltage input pin for A/D converter. These are analog input pi for A/D converter. These are 8-bit CMOS I/O ports. Each port has an input/output select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pullup resistor or not by program. P10 to P17 also function as LED drive ports. These are input only pi. Rev.1.50 Apr 27, 2005 page 6 of 26

7 2. Central Processing (CPU) 2. Central Processing (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 R2 R3 b15 b8 b7 b0 R0H(R0's high bits) R0L(R0's low bits) R1H(R1's high bits)r1l(r1's low bits) R2 Data registers (Note 1) R3 A0 A1 FB Address registers (Note 1) Frame base registers (Note 1) b19 b15 INTBH INTBL The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b0 Interrupt table register b19 PC b0 Program counter b15 USP ISP SB b0 User stack pointer Interrupt stack pointer Static base register b15 FLG b0 Flag register b15 b8 b7 b0 IPL U I O B S Z D C Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Note 1: These registers comprise a register bank. There are two register banks. Figure 2.1. Central Processing Register 2.1 Data Registers (R0, R1, R2 and R3) The R0 register coists of 16 bits, and is used mainly for trafers and arithmetic/logic operatio. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32- bit data register (R2R0). R3R1 is the same as R2R0. Rev.1.50 Apr 27, 2005 page 7 of 26

8 2. Central Processing (CPU) 2.2 Address Registers (A0 and A1) The register A0 coists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for trafers and logic/logic operatio. A1 is the same as A0. In some itructio, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an itruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. 2.7 Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. 2.8 Flag Register (FLG) FLG coists of 11 bits, indicating the CPU status Carry Flag (C Flag) This flag retai a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to Zero Flag (Z Flag) This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is Sign Flag (S Flag) This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is Overflow Flag (O Flag) This flag is set to 1 when the operation resulted in an overflow; otherwise, it is Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is cleared to 0 when the interrupt request is accepted Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is 0 ; USP is selected when the U flag is 1. The U flag is cleared to 0 when a hardware interrupt request is accepted or an INT itruction for software interrupt Nos. 0 to 31 is executed Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled Reserved Area When write to this bit, write "0". When read, its content is indeterminate. Rev.1.50 Apr 27, 2005 page 8 of 26

9 3. Memory 3. Memory Figure 3.1 is a memory map of this MCU. The address space extends the 1M bytes from address to FFFFF16. The internal ROM is allocated in a lower address direction beginning with address 0FFFF16. For example, a 16-Kbyte internal ROM is allocated to the addresses from 0C00016 to 0FFFF16. The fixed interrupt vector table is allocated to the addresses from 0FFDC16 to 0FFFF16. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address For example, a 1-Kbyte internal RAM is allocated to the addresses from to 007FF16. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. Special function registers (SFR) are allocated to the addresses from to 002FF16. Peripheral function control registers are located here. Of the SFR, any space which has no functio allocated is reserved for future use and cannot be used by users FF16 SFR (See Chapter 4 for details.) XXXX16 Internal RAM 0YYYY16 0FFFF16 Internal ROM 0FFDC16 0FFFF16 Undefined itruction Overflow BRK itruction Address match Single step Watchdog timer,oscillation stop detection,oltage detection (Reserved) (Reserved) Reset Expanding area FFFFF16 Type name R5F21114FP, R5F21114DFP R5F21113FP, R5F21113DFP R5F21112FP, R5F21112DFP NOTES : 1. Blank spaces are reserved. No access is allowed. Internal ROM Size Address 0YYYY16 16K bytes 0C K bytes 0D K bytes 0E00016 Internal RAM Size Address 0XXXX16 1K bytes 007FF bytes 006FF bytes 005FF16 Figure 3.1 Memory Map Rev.1.50 Apr 27, 2005 page 9 of 26

10 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functio. Tables 4.1 to 4.4 list the SFR information Table 4.1 SFR Information(1) (1) Address Register After reset A16 000B16 000C16 000D16 000E16 000F A16 001B16 001C16 001D16 001E16 001F A16 002B16 002C16 002D16 002E16 002F A16 003B16 003C16 003D16 003E16 003F16 Processor mode register 0 PM Processor mode register 1 PM System clock control register 0 CM System clock control register 1 CM High-speed on-chip oscillator control register 0 HR Address match interrupt enable register AIER XXXXXX002 Protect register PRCR 00XXX0002 High-speed on-chip oscillator control register 1 HR Oscillation stop detection register OCD Watchdog timer reset register WDTR XX16 Watchdog timer start register WDTS XX16 Watchdog timer control register WDC Address match interrupt register 0 RMAD X016 Address match interrupt register 1 RMAD X016 oltage detection register 1 2 CR oltage detection register 2 2 CR INT0 input filter select register INT0F XXXXX0002 oltage detection interrupt register 2 D4INT X : Undefined NOTES: 1. Blank colum are all reserved space. No access is allowed. 2. Software reset or the watchdog timer reset does not affect this register. 3. Owing to Reset input. 4. In the case of RESET pin = H retaining. Rev.1.50 Apr 27, 2005 page 10 of 26

11 4. Special Function Register (SFR) Table 4.2 SFR Information(2) (1) Address Register After reset A16 004B16 004C16 004D16 004E16 004F A16 005B16 005C16 005D16 005E16 005F A16 006B16 006C16 006D16 006E16 006F A16 007B16 007C16 007D16 007E16 007F16 Key input interrupt control register KUPIC XXXXX0002 AD conversion interrupt control register ADIC XXXXX0002 Compare 1 interrupt control register CMP1IC XXXXX0002 UART0 tramit interrupt control register S0TIC XXXXX0002 UART0 receive interrupt control register S0RIC XXXXX0002 UART1 tramit interrupt control register S1TIC XXXXX0002 UART1 receive interrupt control register S1RIC XXXXX0002 INT2 interrupt control register INT2IC XXXXX0002 Timer X interrupt control register TXIC XXXXX0002 Timer Y interrupt control register TYIC XXXXX0002 Timer Z interrupt control register TZIC XXXXX0002 INT1 interrupt control register INT1IC XXXXX0002 INT3 interrupt control register INT3IC XXXXX0002 Timer C interrupt control register TCIC XXXXX0002 Compare 0 interrupt control register CMP0IC XXXXX0002 INT0 interrupt control register INT0IC XX00X0002 X : Undefined NOTES: 1. Blank colum are all reserved space. No access is allowed. Rev.1.50 Apr 27, 2005 page 11 of 26

12 4. Special Function Register (SFR) Table 4.3 SFR Information(3) (1) Address Register After reset Timer Y, Z mode register TYZMR Prescaler Y PREY FF Timer Y secondary TYSC FF Timer Y primary TYPR FF Timer Y, Z waveform output control register PUM Prescaler Z PREZ FF Timer Z secondary TZSC FF Timer Z primary TZPR FF A16 Timer Y, Z output control register TYZOC B16 Timer X mode register TXMR C16 Prescaler X PREX FF16 008D16 Timer X register TX FF16 008E16 Timer count source set register TCSS F Timer C register TC External input enable register Key input enable register INTEN KIEN A16 Timer C control register 0 TCC B16 Timer C control register 1 TCC C16 009D16 Capture, compare 0 register TM E16 009F16 00A016 Compare 1 register UART0 tramit/receive mode register TM1 U0MR FF16 FF A116 UART0 bit rate register U0BRG XX16 00A216 00A316 UART0 tramit buffer register U0TB XX16 XX16 00A416 UART0 tramit/receive control register 0 U0C A516 UART0 tramit/receive control register 1 U0C A616 00A716 UART0 receive buffer register U0RB XX16 XX16 00A816 UART1 tramit/receive mode register U1MR A916 UART1 bit rate register U1BRG XX16 00AA16 00AB16 UART1 tramit buffer register U1TB XX16 XX16 00AC16 UART1 tramit/receive control register 0 U1C AD16 UART1 tramit/receive control register 1 U1C AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16 UART1 receive buffer register UART tramit/receive control register 2 U1RB UCON XX16 XX X : Undefined NOTES: 1. Blank colum are all reserved space. No access is allowed. 2. When the output compare mode is selected (the TCC13 bit in the TCC1 register = 1), the value is set to FFFF16. Rev.1.50 Apr 27, 2005 page 12 of 26

13 4. Special Function Register (SFR) Table 4.4 SFR Information(4) (1) Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 03FA16 00FB16 00FC16 00FD16 00FE16 00FF16 Register After reset AD register AD XX16 XX16 AD control register 2 ADCON AD control register 0 ADCON XXX2 AD control register 1 ADCON Port P0 register P0 XX16 Port P1 register P1 XX16 Port P0 direction register PD Port P1 direction register PD Port P3 register P3 XX16 Port P3 direction register PD Port P4 register P4 XX16 Port P4 direction register PD Pull-up control register 0 PUR0 00XX00002 Pull-up control register 1 PUR1 XXXXXX0X2 Port P1 drive capacity control register DRR 0016 Timer C output control register TCOUT B316 01B416 01B516 01B616 01B716 Flash memory control register 4 FMR Flash memory control register 1 FMR1 0100XX0X2 Flash memory control register 0 FMR X : Undefined NOTES: 1. Blank colum, to 01B216 and 01B816 to 02FF16 are all reserved space. No access is allowed. Rev.1.50 Apr 27, 2005 page 13 of 26

14 5. Electrical Characteristics 5. Electrical Characteristics Table 5.1 Absolute Maximum Ratings CC ACC Supply voltage O Output voltage Pd Power dissipation Topr=25 C Topr Operating ambient temperature Tstg Storage temperature Condition Rated value CC=ACC -0.3 to 6.5 Analog supply voltage CC=ACC -0.3 to 6.5 I Input voltage -0.3 to CC to CC mw -20 to 85 / -40 to 85 (D version) C -65 to 150 C Table 5.2 Recommended Operating Conditio CC Acc ss Ass IH IL I OH (sum) Supply voltage Min. Typ. Max Analog supply voltage CC 3 Supply voltage Analog supply voltage "H" input voltage "L" input voltage "H" peak all output currents Sum of all pi' IOH (peak) Conditio 0.8CC 0 Note 1: Referenced to CC = ACC = 2.7 to 5.5 at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2: The mean output current is the mean value within 100ms. 3: Hold cc=acc. 0 0 CC 0.2CC ma I OH (peak) "H" peak output current ma I OH (avg) "H" average output current -5.0 ma I OL (sum) "L" peak all Sum of all pi' IOL output currents (peak) 60 ma I OL (peak) "L" peak output Except P10 to P17 10 ma current P10 to P17 Drive capacity HIGH 30 ma Drive capacity LOW 10 ma I OL (avg) "L" average Except P10 to P17 5 ma output current P10 to P17 Drive capacity HIGH 15 ma Drive capacity LOW 5 ma f (XIN) Main clock input oscillation frequency 3.0 cc MHz 2.7 cc < MHz Rev.1.50 Apr 27, 2005 page 14 of 26

15 5. Electrical Characteristics Table 5.3 A/D Conversion Characteristics Measuring condition Min. Typ. Max. Resolution ref =CC 10 Bit Absolute øad=10 MHz, ref=cc= bit mode ±3 LSB accuracy 8 bit mode øad=10 MHz, ref=cc=5.0 ±2 LSB RLADDER Ladder resistance Conversion time 10 bit mode 8 bit mode øad=10 MHz, ref=cc=3.3 3 ±5 LSB øad=10 MHz, ref=cc=3.3 3 ±2 LSB REF=CC øad=10 MHz, ref=cc=5.0 øad=10 MHz, ref=cc= kω 3.3 µs 2.8 µs tcon 10 bit mode 8 bit mode REF Reference voltage CC 4 IA Analog input voltage 0 ref A/D operation Without sample & hold MHz clock frequency 2 With sample & hold MHz Note 1: Referenced to CC=ACC=2.7 to 5.5 at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2: When fad is 10 MHz more, divide the fad and make A/D operation clock frequency (ØAD) lower than 10 MHz. 3: When the Acc is less than 4.2, divide the fad and make A/D operation clock frequency (ØAD) lower than fad/2. 4: Hold cc=ref. P0 P1 30pF P2 P3 P4 Figure 5.1 Port P0 to P4 measurement circuit Rev.1.50 Apr 27, 2005 page 15 of 26

16 5. Electrical Characteristics Table 5.4 Flash Memory ersion Electrical Characteristics td(sr-es) Program/erase cycle Byte program time Block erase time Time delay from suspend request until erase suspend Program, Erase voltage Read voltage Program, Erase temperature Measuring condition cc=5.0, Topr=25 C cc=5.0, Topr=25 C Note 1: Referenced to CC1=Acc=2.7 to 5.5 at Topr = 0 to 60 C unless otherwise specified. Min. Typ. Max 100 cycle µs s ms Erace Suspend Request Interval 10 ms Data-retention duration Topr=55 C 20 year C Table 5.5 oltage Detection Circuit Electrical Characteristics Measuring condition Min. Typ. det oltage detection level na oltage detection circuit self coumption current C27=1, CC= oltage detection interrupt request generating time 2 td(e-a) Waiting time till voltage detection circuit operation starts 3 20 µs ccmin Minimum value of microcomputer operation voltage 2.7 NOTES: 1. The measuring condition is cc=acc=2.7 to 5.5 and Topr= -40 C to 85 C. 2. This shows the time until the voltage detection interrupt request is generated since the voltage passes det. 3. This shows the required time until the voltage detection circuit operates when setting to "1" again after setting the C27 bit in the CR2 register to 0. Max. µs Erase-suspend request (interrupt request) FMR46 td(sr-es) Figure 5.2 Time delay from Suspend Request until Erase Suspend Rev.1.50 Apr 27, 2005 page 16 of 26

17 5. Electrical Characteristics Table 5.6 Reset Circuit Electrical Characteristics (When Using Hardware Reset 2 1, 3 ) Measuring condition Min. Typ. por2 Power-on reset valid voltage 20 C Topr < 85 C det tw(por2- det) Supply voltage rising time when power-on reset is canceled 2 20 C Topr < 85 C, tw(por2) 0s ms NOTES: 1. The voltage detection circuit which is embedded in a microcomputer is a factor to generate the hardware reset 2. Refer to Hardware Reset This condition is not applicable when using with cc When turning power on after the external power has been held below the valid voltage for greater than 10 seconds, refer to Table 16.7 Reset Circuit Electrical Characteristics (When Not Using Hardware Reset 2). 4. tw(por2) is time to hold the external power below effective voltage (por2). Max. Table 5.7 Reset Circuit Electrical Characteristics (When Not Using Hardware Reset 2) por1 tw(por1- det) tw(por1- det) Power-on reset valid voltage Supply voltage rising time when power-on reset is canceled tw(por1- det) Supply voltage rising time when power-on reset is canceled tw(por1- det) Supply voltage rising time when power-on reset is canceled NOTES: 1. When not using hardware reset 2, use with cc tw(por1) is time to hold the external power below effective voltage (por1). Measuring condition 20 C Topr < 85 C 0 C Topr 85 C, tw(por1) 10s 2 Min. Typ. Supply voltage rising time when power-on reset is canceled 20 C Topr < 0 C, tw(por1) 30s ms 20 C Topr < 0 C, tw(por1) 10s 2 0 C Topr 85 C, tw(por1) 1s 2 Max ms ms ms det 3 det 3 por1 tw(por1) tw(por1 det) Sampling time 1,2 cc min por2 tw(por2) tw(por2 det) Internal reset signal ( L effective) 1 fring-s X 32 1 fring-s X 32 NOTES: 1. Hold the voltage of the microcomputer operation voltage range (ccmin or above) within sampling time. 2. A sampling clock is selectable. Refer to 5.4 oltage Detection Circuit of Hardware Manual for details. 3. det shows the voltage detection level of the voltage detection circuit. Refer to 5.4 oltage Detection Circuit of Hardware Manual for details. Figure 5.3 Reset Circuit Electrical Characteristics Rev.1.50 Apr 27, 2005 page 17 of 26

18 5. Electrical Characteristics Table 5.8 High-speed On-Chip Oscillator Circuit Electrical Characteristics td(hroffset) td(hr) High-speed on-chip oscillator frequency 1 / {td(hroffset)+td(hr)} when the reset is released Settable high-speed on-chip oscillator minimum period High-speed on-chip oscillator period adjusted unit High-speed on-chip oscillator temperature dependence(1) High-speed on-chip oscillator temperature dependence(2) NOTES: 1. The measuring condition is cc=acc=5.0 and Topr=25 C. Measuring condition CC=5.0, Topr=25 C Set "4016" in the HR1 register CC=5.0, Topr=25 C Set "0016" in the HR1 register Differences when setting "0116" and "0016" in the HR register Frequency fluctuation in temperature range of -10 C to 50 C Frequency fluctuation in temperature range of -40 C to 85 C Min. Typ. Max MHz 1 ±5 % ±10 % Table 5.9 Power Circuit Timing Characteristics Measuring condition Typ. td(p-r) Time for internal power supply stabilization during powering-on µs td(r-s) STOP release time µs Note 1: The measuring condition is cc=acc=2.7 to 5.5 and Topr=25 C. 2: This shows the wait time until the internal power supply generating circuit is stabilized during power-on. 3: This shows the time until BCLK starts from the interrupt acknowledgement to cancel stop mode. Min. Max. Table 5.10 Electrical Characteristics (1) [cc=5] Measuring condition Min. Typ. Max. "H" output voltage Except XOUT IOH=-5mA CC-2.0 CC OH IOH=-200µA CC-0.3 CC XOUT Drive ability HIGH IOH=-1 ma CC-2.0 CC Drive ability LOW IOH=-500µA CC-2.0 CC "L" output voltage P10 to P17 IOL= 5 ma 2.0 OL Except XOUT IOL= 200 µa 0.45 P10 to P17 Drive capacity HIGH IOL= 15 ma 2.0 Drive capacity LOW IOL= 5 ma 2.0 Drive capacity LOW IOL= 200 µa 0.45 XOUT Drive capacity HIGH IOL= 1 ma 2.0 Drive capacity LOW IOL=500 µa 2.0 T+-T- Hysteresis INTo, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RxD0, RxD1, P45 RESET IIH "H" input current I=5 5.0 µa IIL "L" input current I=0-5.0 µa RPULLUP Pull-up resistance I= kω RfXIN Feedback resistance XIN 1.0 MΩ fring-s Low-speed on-chip oscillator frequency khz RAM RAM retention voltage At stop mode 2.0 Note 1 : Referenced to CC=ACC=4.2 to 5.5 at Topr = -20 to 85 C / -40 to 85 C, f(xin)=20mhz unless otherwise specified. Rev.1.50 Apr 27, 2005 page 18 of 26

19 5. Electrical Characteristics Table 5.11 Electrical Characteristics (2) ICC Power supply current (CC=3.3 to 5.5) In single-chip mode, the output pi are open and other pi are SS [cc=5] High-speed mode Medium-speed mode High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Measuring condition XIN=20 MHz (square wave) No division XIN=16 MHz (square wave) No division XIN=10 MHz (square wave) No division XIN=20 MHz (square wave) Division by 8 XIN=16 MHz (square wave) Division by 8 XIN=10 MHz (square wave) Division by 8 Main clock off High-speed on-chip oscillator on=8 MHz No division Main clock off High-speed on-chip oscillator on=8 MHz Division by 8 Main clock off Division by 8 Min. Typ. Max ma ma ma 3 ma 4 8 ma ma 2 ma 900 ma µa Wait mode Wait mode Stop mode NOTES 1: The power supply current measuring is executed using the measuring program on frash memory. 2: Timer Y is operated with timer mode. Main clock off When a WAIT itruction is executed 2 Peripheral clock operation C27= 0 Main clock off When a WAIT itruction is executed 2 Peripheral clock off C27= 0 Main clock off Low-speed on-chip oscillator off CM10="1" Peripheral clock off C27="0" µa µa µa Rev.1.50 Apr 27, 2005 page 19 of 26

20 5. Electrical Characteristics Timing requirements (Unless otherwise noted: CC = 5, SS = 0 at Ta = 25 C) [CC=5] Table 5.12 XIN input tc(xin) twh(xin) twl(xin) XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width Min. Max Table 5.13 CNTR0 input, CNTR1 input, INT2 input tc(cntr0) twh(cntr0) twl(cntr0) CNTR0 input cycle time CNTR0 input HIGH pulse width CNTR0 input LOW pulse width Min. Max Table 5.14 TCIN input, INT3 input tc(tcin) twh(tcin) twl(tcin) TCIN input cycle time TCIN input HIGH pulse width TCIN input LOW pulse width Min. Max. 400 (1) 200 (2) 200 (2) NOTES 1 :When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source frequency x 3). 2 : When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source frequency x 1.5). Table 5.15 Serial Interface tc(ck) tw(ckh) tw(ckl) td(c-q) th(c-q) tsu(d-c) th(c-d) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Min. Max Table 5.16 External interrupt INT0 input tw(inh) tw(inl) INT0 input HIGH pulse width INT0 input LOW pulse width Min. Max. 250 (1) 250 (2) NOTES 1 : When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. 2 : When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. Rev.1.50 Apr 27, 2005 page 20 of 26

21 5. Electrical Characteristics CC = 5 tc(cntr0) twh(cntr0) CNTR0 input twl(cntr0) tc(tcin) twh(tcin) TCIN input twl(tcin) tc(xin) twh(xin) XIN input twl(xin) tc(ck) tw(ckh) CLKi tw(ckl) th(c-q) TxDi RxDi td(c-q) tsu(d-c) th(c-d) tw(inl) INTi tw(inh) Figure 5.4 cc=5 timing diagram Rev.1.50 Apr 27, 2005 page 21 of 26

22 5. Electrical Characteristics Table 5.17 Electrical Characteristics (3) [cc=3] Measuring condition Min. Typ. Max. "H" output voltage Except XOUT IOH=-1mA CC-0.5 CC OH XOUT Drive capacity HIGH IOH=-0.1 ma CC-0.5 CC Drive capacity LOW IOH=-50 µa CC-0.5 CC "L" output voltage P10 to P17 Except XOUT IOL= 1 ma 0.5 OL P10 to P17 Drive capacity HIGH IOL= 2 ma 0.5 Drive capacity LOW IOL= 1 ma 0.5 XOUT Drive capacity HIGH IOL= 0.1 ma 0.5 Drive capacity LOW IOL=50 µa 0.5 T+-T- Hysteresis INTo, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RxD0, RxD1, P RESET IIH "H" input current I=3 4.0 µa IIL "L" input current I=0-4.0 µa RPULLUP Pull-up resistance I= kω RfXIN Feedback resistance XIN 3.0 MΩ fring-s Low-speed on-chip oscillator frequency khz RAM RAM retention voltage At stop mode 2.0 Note 1 : Referenced to CC=ACC=2.7 to 3.3 at Topr = -20 to 85 C / -40 to 85 C, f(xin)=10mhz unless otherwise specified. Rev.1.50 Apr 27, 2005 page 22 of 26

23 5. Electrical Characteristics Table 5.18 Electrical Characteristics (4) ICC Power supply current (CC=2.7 to 3.3) In single-chip mode, the output pi are open and other pi are SS [cc=3] High-speed mode Medium-speed mode High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Measuring condition XIN=20 MHz (square wave) No division XIN=16 MHz (square wave) No division XIN=10 MHz (square wave) No division XIN=20 MHz (square wave) Division by 8 XIN=16 MHz (square wave) Division by 8 XIN=10 MHz (square wave) Division by 8 Main clock off High-speed on-chip oscillator on=8 MHz No division Main clock off High-speed on-chip oscillator on=8 MHz Division by 8 Main clock off Division by 8 Wait mode Main clock off When a WAIT itruction is executed 2 Peripheral clock operation C27= 0 Wait mode Main clock off When a WAIT itruction is executed 2 Peripheral clock off C27= 0 Stop mode Main clock off Low-speed on-chip oscillator off CM10="1" Peripheral clock off C27="0" Note 1: The power supply current measuring is executed using the measuring program on frash memory. 2: Timer Y is operated with timer mode. Min. Typ. Max ma ma ma 2.5 ma ma ma ma ma µa µa µa µa Rev.1.50 Apr 27, 2005 page 23 of 26

24 5. Electrical Characteristics Timing requirements (Unless otherwise noted: CC = 3, SS = 0 at Ta = 25 C) [CC=3] Table 5.19 XIN input tc(xin) twh(xin) twl(xin) XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width Min. Max Table 5.20 CNTR0 input, CNTR1 input, INT2 input tc(cntr0) twh(cntr0) twl(cntr0) CNTR0 input cycle time CNTR0 input HIGH pulse width CNTR0 input LOW pulse width Min. Max Table 5.21 TCIN input, INT3 input tc(tcin) twh(tcin) twl(tcin) TCIN input cycle time TCIN input HIGH pulse width TCIN input LOW pulse width Min. Max (1) 600 (2) 600 (2) NOTES 1 :When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source frequency x 3). 2 : When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source frequency x 1.5). Table 5.22 Serial Interface tc(ck) tw(ckh) tw(ckl) td(c-q) th(c-q) tsu(d-c) th(c-d) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Min. Max Table 5.23 External interrupt INT0 input tw(inh) tw(inl) INT0 input HIGH pulse width INT0 input LOW pulse width Min. Max. 380 (1) 380 (2) NOTES 1 : When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. 2 : When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. Rev.1.50 Apr 27, 2005 page 24 of 26

25 5. Electrical Characteristics CC = 3 tc(cntr0) twh(cntr0) CNTR0 input twl(cntr0) tc(tcin) twh(tcin) TCIN input twl(tcin) tc(xin) twh(xin) XIN input twl(xin) tc(ck) tw(ckh) CLKi tw(ckl) th(c-q) TxDi RxDi td(c-q) tsu(d-c) th(c-d) tw(inl) INTi tw(inh) Figure 5.5 cc=3 timing diagram Rev.1.50 Apr 27, 2005 page 25 of 26

26 Package Dimeio Package Dimeio JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP32-7x PLQP0032GB-A 32P6U-A 0.2g HD *1 D NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. b1 E H E c bp *2 c 1 Reference Dimeion in Millimeters Min Nom Max 32 9 Z E Terminal cross section D E A HD Z D Index mark 8 HE A A F A A 2 c bp b c e y *3 bp x A1 Detail F L 1 L c 1 e x y ZD 0.7 ZE 0.7 L L1 1.0 Rev.1.50 Apr 27, 2005 page 26 of 26

27 REISION HISTORY R8C/11 Group Datasheet Rev. Date Description Page Summary 1.00 Jun. 19, 2003 First edition issued 1.10 Sep. 08, Table 1.1: Shortest itruction execution time and f(xin) changed 5 Figure 1.3: Pin name changed from TXOUT to CNTR0 6 Table 1.3: Pin name changed from TXOUT to CNTR0 10 The value of HR1 register after reset changed 12 The value of TC register after reset changed 14 Chapter 5. Electrical Characteristics added 1.20 Oct. 31, Table 1.1: Power coumption values added Dec 05, Table 1.2 : ** deleted 15 Table 5.4 revised Table 1.3: Resistor value for CNss and MODE deleted Register name of address modified from CMP2IC to CMP1IC, register name of address 005C16 modified from CMP1IC to CMP0IC Table 5.2: Note 3 and Note 4 deleted tsamp in Table 5.3 deleted Figure 5.1 added Table 5.10: cc changed from 4.2 to 5.5 to 3.3 to 5.5, low-power ring oscillator changed from on 100kHz to 125kHz, XIN=5MHz deleted and XIN=10MHz added in high-speed mode and medium-speed mode, C27= 0 added in stop mode measuring condition, data added and modified Table 11 to Table 15 added Figure 5.2 added Table 5.16: Note 1, f(bclk)=5 MHz changed to 10 MHz Table 5.17: low-power ring oscillator changed from on 100kHz to 125kHz, XIN=5MHz deleted and XIN=10MHz added in high-speed mode and medium-speed mode, C27= 0 added in stop mode measuring condition, data added and modified Table 5.18 to Table 5.22 added Figure 5.3 added 1.40 Sep 30, 2004 all pages Words standardized (on-chip oscillator, serial interface, A/D) 2 Table 1.1 revised 5 Figure 1.3, NOTES 3 added 6 Table 1.3 revised 9 Figure 3.1, NOTES added One body sentence in chapter 4 added ; Title of Table 4.1 to 4.4 added 12 Table 4.3 revised ; Table 4.4 revised 14 Table 5.2 revised 15 Table 5.3 revised 16 Table 5.4 revised ; Table 16.5 revised 17 Table 5.6, 5.7 adn 5.8 revised ; Figure 5.3 revised 18 Table 5.9 revised ; Table 5.10 revised A-1

28 REISION HISTORY R8C/11 Group Datasheet Rev. Date Description Page Summary 1.40 Sep 30, Table 5.12 revised ; Table 5.16 revised 22 Table revised 24 Table revised 1.10 Apr Table 1.2, Figure 1.2 package name revised 5 Figure 1.3 package name revised 10 Table 4.1 revised 12 Table 4.3 revised 15 Table 5.3 partly revised 16 Table 5.4 partly added 17 Table 5.6, Table 5.7 revised 18 Table 5.9, Table 10 partly revised 22 Table 5.17 partly revised 26 Package Dimeio revised A-2

29 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo , Japan Keep safety first in your circuit desig! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due coideration to safety when making your circuit desig, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention agait any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any licee under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no respoibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reaso. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no respoibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various mea, including the Renesas Technology Corp. Semiconductor home page ( 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no respoibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when coidering the use of a product contained herein for any specific purposes, such as apparatus or systems for traportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictio, they must be exported under a licee from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulatio of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Refer to " for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA , U.S.A Tel: <1> (408) , Fax: <1> (408) Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) , Fax: <44> (1628) Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> , Fax: <852> Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) , Fax: <886> (2) Renesas Technology (Shanghai) Co., Ltd Ruijing Building, No.205 Maoming Road (S), Shanghai , China Tel: <86> (21) , Fax: <86> (21) Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore Tel: <65> , Fax: <65> Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 2.0