Efficient scaling in a Task-Based Game Engine

Transcription

1 Efficient scaling in a Task-Based Game Engine Leigh Davies, Intel leigh.davies@intel.com

2 Agenda How do we want to program for multi-core? Introduction to tasking Building a Dependency Graph Typical data flow Overlapping Frames CPU post-processing MLAA Conclusion

3 Why scaling to n cores is important 42% of PCs using Steam have 4+ cores* Up from 26% last year What can we get from more cores? 100% More compute, which means Improved visual fidelity, gameplay 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 1 cores 2 cores 4 cores 6 cores Jul-09 Jan-10 Jul-10 Jan-11 * Physical Cores, data taken from

4 Goal The Utopian Goals Automatic scaling (no algorithm/code changes) with number of cores Algorithmic parallelism decoupled from machine parallelism Engine systems can remain autonomous Performance increases linearly with number of cores

5 Tasking What is it? Thread 0 Thread 1 Thread 2 Thread 3

6 Tasking What is it? Thread 0 Thread 1 Thread 2 Thread 3

7 Data flow for a frame Thread 0 Thread 1 Thread 2 Thread 3

8 Tasking System Implementation Tasking API Application logic Task set 1 Scheduler Task set

9 Tasking API Used in Intel samples to implement a dependency graph, abstracts the base scheduler from the game code allowing alternative schedulers. ( CreateTaskSet Inputs: Task callback function and dependencies Task count, name Returns TASKSETHADLE and begins execution when dependencies are satisfied TASKSETHADLE used in future CreateTaskset calls to express dependency WaitForTaskSet Main thread processes tasks until specified taskset completes Init/Shutdown/ReleaseHandle

10 Creating a Dependency Graph T0 = CreateTaskSet( ); T1 = CreateTaskSet( ); T2 = CreateTaskSet( { T0, T1 }, ); T0 and T1 will execute immediately T2 will not start to execute until T0 and T1 have completed T0 T1 T2

11 Task Function User-defined callback to execute one unit of work Parameters: Data pointer global to the taskset Task id (which task in the set is this) Task count (how many total tasks are in the set) Context ( [0, umthreads] used for lock-free access to threadspecific data) Ex: D3D11DeviceContext for multithreaded rendering

12 Making a good Task function Task length less than 5% of taskset time Allows scheduler to load-balance Scheduling overhead constant per task Experiment with task working set size Be aware of issues with cache contention, etc. Prefer per-context data results to using InterlockedXXX Aggregate per-context data with a dependent taskset if needed InterlockedXXX expensive for memory intensive algorithms

13 Example: Computing average luminance Each task processes n-scanlines InterlockedXAdd causes sync point

14 Example: Computing average luminance Use two tasksets Compute sum per-context id Sum per-context id sums and compute average T0 Main Complex system taskset (parallel) Complex system taskset (1 task) T1 Worker0 T2 Worker1 T3 Worker2

15 Scheduler A scheduler needs to Create and manage task worker threads Manage where tasks get executed It s a complex problem Various options available: Intel Thread Building Blocks (TBB) Microsoft Concurrency Runtime (ConCRT) Roll-your-own using standard threading

16 Main Worker0 Worker1 Worker Simple system taskset (parallel) Complex system taskset (parallel) Complex system taskset (1 task) Simple system taskset (DX11 CmdLists) Execute CmdLists

17 Data flow for a frame Simple system taskset Complex system taskset Complex system taskset DX11 CmdLists Execute CmdLists Simple system taskset Main Worker Worker Worker

18 Data flow for a frame Simple system taskset Complex system taskset Complex system taskset DX11 CmdLists Execute CmdLists Complex System Simple system taskset Main Worker Worker Worker

19 Execution flow for overlapped frames Simple system taskset (parallel) Complex system taskset (parallel) Complex system taskset (1 task) Simple system taskset (DX11 CmdLists) Execute CmdLists Main Worker Worker Worker

20 Implications of overlapped frames Buffers need to be duplicated or copied for the frame Size can be limited with partial frame overlap Latency will increase by up to 1 frame CPU submits previous frame to GPU while computing current frame Use dependencies to control where overlap occurs Maximal benefit when combined with CPU loadbalancing If frame is GPU bound, move work to CPU

21 Beware! Serialization ahead How to avoid it Do not wait in a task o Sleep, WaitForSingleObject, etc. Don t take locks How to mitigate: Use taskset dependencies and context id Post events to main thread and allow it to schedule tasksets Use lock-free constructs

22 Serialization ot Always Obvious Implicit serialization: Memory allocation (even CRT s alloc/new) Library calls that use locking Mitigation: Pre-allocate memory, custom allocator, etc. Instrument engine code (e.g. GPA Platform Analyzer) Validate task running time is as expected using Platform Analyzer

23 Debugging your tasks Various tools available to help debug tasking Use Platform Analyzer in GPA to visualize task execution Instrument tasks to view where/when they execute Instrument locking code for Platform Analyzer to see locks/waits in tasks Xperf can help see the bigger picture See last year s Gamefest talk and Bruce Dawson s talk How Valve Makes Games Better with Xperf Make the entire frame a DG to prevent dependency confusion

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25 Great I'm so fast I'm GPU bound! GPU Context Main Frame Worker0 Worker1 Worker2 When GPUView shows the GPU is behind the CPU Option1: Increase fidelity of CPU based talks, its free! Option 2: Move some GPU work back to the CPU Lots of options but post processing plays to CPU strengths

26 CPU post-processing sample Morphological antialiasing (MLAA) plus HDR processing Uses both CPU tasking and GPU to CPU pipelining Helper Pipeline class in MLAA sample to simplify scheduling of data transfer

27 The MLAA algorithm MSAA better than FSAA, but still brute-force HW MSAA4x on PS3 not used, because of perf. cost MSAA4x can be expensive on PC as well MLAA: new CPU-based antialiasing algorithm Getting tons of traction, more games integrating, efforts to run on GPUs (drivers, SIGGRAPH talk, )

28 The MLAA algorithm Two tasksets implement the algorithm Find discontinuities between pixels in image buffer Identify predefined edge patterns and blend weights. Blend colors in the neighborhood of these patterns Extra steps needed on PC/DX Copy FB back and forth to CPU-accessible memory

29 MLAA Taskset 1 Find pixels discontinuities Do an horizontal pass, and a vertical pass Horizontal pass check for discontinuities between rows If found, pixel is marked as an edge pixel Vertical pass is the same with two substitutions: row -> column and horizontal -> vertical Step 2 and 3 also work with a horizontal, then vertical pass Instruction-level parallelism: SIMD code is used to process multiple pixels at once Task-based parallelism: Each task processes a block of 8 rows/columns

30 MLAA Taskset 2 Identify predefined edge patterns walk discontinuity flags Compute discontinuity lines Most edges result in L-shaped patterns Other types decompose to L patterns

31 MLAA Taskset 2 L-shapes have a primary segment (0.5+ pixels) and a secondary segment. Connect the middle point of the secondary segment to the extremity of the primary segment Forms a trapezoid with the pixel Area of the trapezoid is the blend weight for that pixel V0V1 : secondary segment, V1V2, primary segment; in green discontinuity lines, in red new connection line a = 1/3 for pixel c5, 1/24 for pixel d5; both blended with bottom neighbor as primary segment is horizontal

32 MLAA Taskset 2 Blend colors Blending weights calculated for L-shape Calculations are a bit more complicated for color images eed minimize color differences at the stitching positions of different L-shapes. Once we are done with the blending passes, the color buffer is copied back to GPU memory

33 Pipelining GPU data to CPU D3D provides pipelining from CPU to GPU Application must pipeline GPU to CPU Read-back RT from Frame n Render Frame n+1 to RT MLAA Frame n, update and Present Read-back RT from Frame n+1 Render Frame n+2 to RT

34 GPU CPU A Frame moving through the pipeline Worker Threads Main Thread

35 MLAA Sample

36 120 MSAAx4 and MLAA on 1280x ms / frame Scene complexity 1 to 100 MSAAx4 MLAA

37 MSAAx4 and MLAA on 1280x ms / frame Scene complexity 1 to 100 MSAAx4 MLAA

38 Conclusion/call to action Task your systems to scale across the PC ecosystem Use dependencies Data synchronization Overlap frames Remove OS synchronization Use Platform Analyzer to visualize performance Check out the tasking samples for yourself!

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40 With the chance to sell your game on STEAM* 2011, Intel Corporation. All rights reserved. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. 2011, Valve Corporation. All rights reserved. Steam and the Steam logo are trademarks or registered trademarks of Valve Corporation in the United States and/or other countries. *Other names and brands may be claimed as the property of others.

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42 Legal Disclaimers IFORMATIO I THIS DOCUMET IS PROVIDED I COECTIO WITH ITEL PRODUCTS. EXCEPT AS PROVIDED I ITEL'S TERMS AD CODITIOS OF SALE FOR SUCH PRODUCTS, ITEL ASSUMES O LIABILITY WHATSOEVER, AD ITEL DISCLAIMS AY EXPRESS OR IMPLIED WARRATY RELATIG TO SALE AD/OR USE OF ITEL PRODUCTS, ICLUDIG LIABILITY OR WARRATIES RELATIG TO FITESS FOR A PARTICULAR PURPOSE, MERCHATABILITY, OR IFRIGEMET OF AY PATET, COPYRIGHT, OR OTHER ITELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel may make changes to specifications, product descriptions, and plans at any time, without notice. The Intel processor and/or chipset products referenced in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. All dates provided are subject to change without notice. All dates specified are target dates, are provided for planning purposes only and are subject to change. Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. * Other names and brands may be claimed as the property of others. Copyright 2011, Intel Corporation. All rights reserved.

43 Optimization otice Optimization otice Intel compilers, associated libraries and associated development tools may include or utilize options that optimize for instruction sets that are available in both Intel and non- Intel microprocessors (for example SIMD instruction sets), but do not optimize equally for non-intel microprocessors. In addition, certain compiler options for Intel compilers, including some that are not specific to Intel micro-architecture, are reserved for Intel microprocessors. For a detailed description of Intel compiler options, including the instruction sets and specific microprocessors they implicate, please refer to the Intel Compiler User and Reference Guides under Compiler Options." Many library routines that are part of Intel compiler products are more highly optimized for Intel microprocessors than for other microprocessors. While the compilers and libraries in Intel compiler products offer optimizations for both Intel and Intel-compatible microprocessors, depending on the options you select, your code and other factors, you likely will get extra performance on Intel microprocessors. Intel compilers, associated libraries and associated development tools may or may not optimize to the same degree for non-intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include Intel Streaming SIMD Extensions 2 (Intel SSE2), Intel Streaming SIMD Extensions 3 (Intel SSE3), and Supplemental Streaming SIMD Extensions 3 (Intel SSSE3) instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. While Intel believes our compilers and libraries are excellent choices to assist in obtaining the best performance on Intel and non-intel microprocessors, Intel recommends that you evaluate other compilers and libraries to determine which best meet your requirements. We hope to win your business by striving to offer the best performance of any compiler or library; please let us know if you find we do not. otice revision #

44 Appendix I Thread Building Blocks: Graphics Performance Analyzers: Visual Computing Home Page Graphics Samples Home Page Keep up to date with samples releasing throughout the year Graphics Samples Page: Sandy Bridge Samples Page:

45 Appendix II MLAA Algorithm paper details Developed and published in 2009 by Alexander Reshetov from Intel Labs