Features. Description. PA32KAS ARM Cortex -M0 MCU Datasheet PA32KAS. The PA32KAS is a HARDSlL TM

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1 ARM Cortex -M0 MCU Datasheet Features ARM Cortex -M0 DesignStart processor On-Chip Memory o 16kB Data o 16kB Program o On-Chip error correction and detection (EDAC) & scrubbing Up to 8MB of off-chip Memory via Sync Burst Memory (SBM) interface o Supports SST memories with EDAC 32 Dedicated General Purpose I/O (GPIO) pins o Configurable direction, pull up/down o Configurable as edge or level sensitive interrupt sources 32 General purpose counter/timers o Configurable interrupt sources o Can be trigger from 2 sources (GPIO or other counter/timers) 2 UARTS o Internal FIFO o Transmit or receive interrupt source 2 Serial Peripheral Interface (SPI) ports o Internal FIFO o Transmit or receive interrupt source o Multiple chip select outputs System-level Triple Mode Redundancy (TMR) on all internal registers o Triple Mode Redundancy (TMR) 3.3V I/O Supply; 1.5V Core Supply Available in Die Form or 188 pin Ceramic Quad Flat Package Description The is a HARDSlL TM ARM Cortex -M0 based Processor System with a related set of peripherals. Initial program code memory is loaded from an external Serial Peripheral Interface (SPI) based memory on power up. The device is Latch up immune at 125C. The HARDSIL TM Hardened by Process combined with additional Hardened by Design provides the optimal solution for harsh environments. Rev 1.0 page 1

2 S 1 Functional Description The ARM Cortex-M0 Processor chip is designed for high reliability applications. It has been designed for extreme environment applications. It is capable of operating at extremely high and low temperatures (-55 C to >200 C) and within extreme radiation environments. 1.1 Power-Up Sequence The detects the Power-Up condition and begins operations by loading the internal code memory from an external Serial Peripheral Interface (SPI) based memory. After loading the code memory, the processor follows a normal ARM Cortex -M0 start sequence. The Power-Up condition is triggered by either the internal Power-On-Reset detect or from an external Power-On-Reset condition. The internal Power-On-Reset detect is enabled when the EXTMODE pin is low. The external Power-On-Reset condition is triggered by the EXTPORn signal being low (independent of the EXTMODE pin setting). When the Power-Up condition is triggered, the ARM Cortex -M0 processor is held in reset, while the internal code memory is loaded. The code memory is loaded from an external SPI based memory. The memory is read starting at address 0, in blocks of 128 bytes. The value on the ROM_SIZE pin determines how many total bytes are read from the external memory (either 4KB or 16KB). The ROM_DELAY pins are used to configure the time delay (by number of clock cycles) from Power-Up detection, until the load sequence begins. This time delay needs to be sufficient for the power supplies to have reached final working voltages, and for the external SPI memory to be ready for commands. The signal POROUTn will go high after the configured time delay has ended, and the memory load begins. The ROM_CHECK pin can be used to configure the memory load process in validation mode. In validation mode each 128 byte packet is read twice from the SPI memory. On the first read the data is written to the internal memory. On the second read the data is read from the internal memory and compared to the second SPI read; if these don t match, the dual read of the 128 bytes is repeated. In addition to loading the code memory, the Power-Up condition will cause the data memory to be initialized to all zero values. This allows correct error-detect and correct (EDAC) syndromes to be generated for all memory data. Rev 1.0 page 2

3 S In addition to Power-Up resets, the EXTRESETn pin can be used to reset the devices. Based on previous software configuration (in the RST_CNTL_ROM and RST_CNTRL_RAM registers), this reset can skip the memory initialization sequence and just reset the processor and peripherals. 1.2 Power-Up Behavior of pins This section describes the Power-Up and Reset behavior of the GPIO*, SPI* and UART* pins on the device. - Following a reset, the SPI ports are configured as Masters. - At Power-up or external Power-On-Reset, the internal SYNC_PORESET signal is asserted asynchronously (without clock required). For all other reset events the internal SYNC_PORESET signal is asserted synchronously. - The SYNC_PORESET signal directly asserts the internal HRESET signal. This signal synchronously resets the processor and peripherals. - The IO interface unit places all the GPIO*, SPI*, and UART* pins in tri-state mode while HRESET is active. - The HRESET is de-asserted after loading the program code from external memory when the processor starts its boot sequence. - Processor boot code can then configure the pins as needed by the peripheral control registers. Rev 1.0 page 3

4 2 Block Diagram SPI ROM Interface SPI ROM Interface ARM CORTEX-M0 16kB Data SRAM with EDAC 16kB Code SRAM with EDAC Sync Burst Memory Interface SBM Interface AHB-LITE BUS AHB to APB Bridge SMB Config GPIO GPIO Interface Interrupt Config System Config A P B UARTs SPI UART Interface SPI Interface IO Pin Config B U S Counter/Time rs Power On-Reset System Control Interrupts Clocks Test Control Config Test 3 Pin Descriptions Rev 1.0 page 4

5 Pin Type Description Type Internal Pullup/dow n CLK EXTRESETn EXTPORn EXTMODE POROUTn GPIO[31:0] System Pins System Clock. All Address, Data and Control are timed relative to the rising edge of the Clock. External System Reset, active low. Resets the processor and all peripherals. This is asserted asynchronously but de-asserted internally synchronously. External Power-On Reset, active low. Asynchronous Power-On reset. Resets the processor, all peripherals and triggers power-up memory load sequence. This is asserted asynchronously but de-asserted internally synchronously. External Power-On Reset only mode selection. When low the internal Power-On reset logic is enabled along with the EXTPORn signal. When high,the internal Power-On reset is disabled and only the EXTPORn signal is used to signal a Power-On reset. Output of the internal Power-On-Reset Signal. Indicates the reset status of the part. This is signal goes low asynchronously with either EXTPORn or the internal POR. It goes high after the time delay specified by ROM_DELAY. About 3 cycles after this signal goes high, the internal boot sequence will begin. General Purpose I/O pins Software configurable General Purpose I/O pins. Software configurable for direction, interrupts sources, and counter/timer triggers. UART pins CLOCK Sync In Sync In Static In Out Sync I/O None None None None None Software configurabl e UART_RX[1:0] Receive inputs for UARTS ports. ASync In Software configurabl e UART_TX[1:0] Transmit outputs for UARTS ports. ASync Out Serial Peripheral Interfaces (SPI) Software configurabl e Rev 1.0 page 5

6 SPI_SCK[1:0] SPI_SSEL_0[1:0] SPI_SSEL_1[1:0] SPI_SSEL_2[1:0] SPI_SSEL_3[1:0] SPI_ MOSI [1:0] SPI_ MISO [1:0] Clock pins for Serial Peripheral Interfaces (SPI). When SPI interface is in master mode, this is the Clock Out pin. When the SPI interface is in slave mode, this is the Clock In Pin. Select pins for Serial Peripheral Interfaces (SPI). When SPI interface is in master mode, these are the Select Out pin. When the SPI interface is in slave mode, these are the Select In Pin. Master Out Slave In (MOSI) pins for Serial Peripheral Interfaces (SPI). When SPI interface is in master mode, this is the Data Out pin. When the SPI interface is in slave mode, this is the Data In Pin. Master In Slave Out (MOSI) pins for Serial Peripheral Interfaces (SPI). When SPI interface is in master mode, this is the Data In pin. When the SPI interface is in slave mode, this is the Data Out Pin. SPI ROM pins Sync I/O Sync I/O Sync I/O Sync I/O Software configurabl e Software configurabl e Software configurabl e Software configurabl e ROM_SCK SPI Clock to Boot ROM. Sync Out None ROM_CSn SPI Chip Select to Boot ROM (Active Low). Sync Out None ROM_SO SPI Data Out to Boot ROM. Sync Out None ROM_SI SPI Data In from Boot ROM. Sync In None ROM_SPEED Configures the ROM_SCK clock rate (divided Static In None from the CLK pin). 00 Divide by 4 CLK=50Mhz) 01 Divide by 6 CLK=50Mhz) 10 Divide by 12 (4.2 CLK=50Mhz) 11 Divide by 50 (1 CLK=50Mhz) ROM_DELAY[2:0] Configures the delay from Power-On reset until Static In None the boot sequence is started on ROM SPI interface. The delay time is based on the counting of the system clock (CLK) cycles CLK=50Mhz) cycles CLK=50Mhz) cycles CLK=50Mhz) 011 5,000 cycles CLK=50Mhz) ,000 cycles CLK=50Mhz) ,000 cycles CLK=50Mhz) 110 5,000,000 cycles CLK=50Mhz) ROM_SIZE Configures the amount of ROM address space to fill from the external ROM. 0 Loads 4K Bytes 1 Loads 16K Bytes Static In None Rev 1.0 page 6

7 ROM_CHECK Configures the ROM check mode. In check mode each 128 byte block of data is read twice and verified that the same data is received both times. 0 Normal load sequence 1 Check mode load sequence Sync Burst Memory (SBM) pins Static In None SBM_RESETn The output of the internal Power-On reset. Can Sync Out None be used to reset the external memory. This signal is a few cycles behind POROUTn and can be triggered by software as well. SBM_ ADSPn Sync burst memory ADSPn (Address Strobe Sync Out None Processor), active low. SBM_CEn Sync burst memory Cen (Chip Enable), active Sync Out None low. SBM_WEn Sync burst memory Wen (Write Enable), active Sync Out None low. SBM_BWEn [3:0] Sync burst memory BWEn (Byte Write Enable), Sync Out None active low. When SBM_WEn is active (is 0), these signify which bytes to write. Bit 3 => SBM_DATA [31:24] Bit 2 => SBM_DATA [23:16] Bit 1 => SBM_DATA [15:8] Bit 0 => SBM_DATA [7:0] SBM_ADDR [21:0] Sync burst memory ADDR (Address). These Sync Out None signify a 32-bit word address. SBM_DATA[31:0] Sync burst memory DATA. Sync I/O None SBM_OEn Syncburst memory OEn (Output Enable), active low. Used to enable the Data out of the SBM memory during a read operation. Sync Out None SBM_P[3:0] SBM_INITn SBM_SYNC_BURST_CFG Sync Burst Memory (SBM) pins for SST enhanced mode memories Sync burst memory PARITY Data (when parity is enabled). For use with SST memories with PARITY feature. Sync burst memory INITn, active low (Indicates Initialization sequence in process). For use with SST memories that support initialization sequences. A low value indicates the memory is in initialization mode and is not yet ready. Sync burst memory SYNC_BURST_CFG (Enables sync burst compatibility mode). A high value indicates that interface is in normal sync burst compatible mode. Sync I/O Sync In Sync Out None None None Rev 1.0 page 7

8 SBM_EDAC_CFG SBM_PAR_EN_CFG SBM_EVEN_PAR_CFG SBM_SBEn SBM_MBEn SBM_PEn SBM_ACKn Sync burst memory EDAC_CFG (Enables EDAC Mode) Sync burst Memory EDAC_EN_CFG (Enable Parity Mode) Sync burst Memory EVN_PAR_CFG (Configures Even/Odd Parity). Signify even (1) or odd (0) parity checking is used when parity is enabled (SBM_PAR_EN_CFG=1). Sync burst memory SBEn, active low (Single Bit Error status) Sync burst memory SMEn, active low (Multi-Bit Error status) Sync burst memory PEn, active low (Parity Error status) Sync burst memory ACKn, active low (Error Acknowledge) JTAG pins Sync Out Sync Out Sync Out Sync In Sync In Sync In Sync Out None None None None None None None TCK Test Clock. During normal (non-test mode) CLOCK None operation of the part this pin should be tied low. TMS Test Mode Select. Sync In Pullup TRSTn Test Reset, active low. During normal (non-test Sync In Pullup mode) operation of the part this pin should be tied low. TDI Test Data In. Sync In Pullup TDO Test Data Out. Sync Out None TEST pins IDDQ Used for IDDQ Testing. Should be tied low In None SCAN_EN Used for Scan Testing. Should be tied low In None SCAN_MODE Used for Scan Testing. Should be tied low In None PARAMEN Used Parametric Testing. Should be tied low In None PARAMO Used Parametric Testing. Should be ignored Out None MEM_RM Memory Test, should be tied low In None MEM_RWM Memory Test, should be tied high. For use above In None 125C and below 50Mhz, this should be tied low. MEM_WM Memory Test, should be tied low In None MEM_OLM Memory Test, should be tied low In None Power/Ground/Analog pins VDD (pin/pad) 1.5V 1.5V Core power Power VSS (pin/pad) VSSIO Ground Ground (pad) DVDD (pin) VDDIO (pad) 3.3V 3.3V IO power Power Rev 1.0 page 8

9 4 Package Options Ceramic Quad Flat Package Pin Outline Note: Pin 1 is in lower left hand corner of package incrementing counterclockwise. Rev 1.0 page 9

10 5 Die Options 5.1 Table of Die Pad Coordinates from Center of Die in Microns Die Size (Without Scribe and Partial Street) X = 9061 um; Y = 4861 um Pad # Die Signal Name X (um) Y (um) Pad # Die Signal Name X (um) Y (um) 1 VDDIO_PAD_ VDDIO_PAD_ SBM_ADDR[15] ROM_SIZE VSS_PAD_ VSS_PAD_ SBM_ADDR[16] ROM_CHECK VSSIO_PAD_ VSSIO_PAD_ SBM_ADDR[17] UART_RX[0] VDDIO_PAD_ VDDIO_PAD_ SBM_ADDR[18] UART_TX[0] VDD_PAD_ VDD_PAD_ SBM_ADDR[19] UART_RX[1] VSSIO_PAD_ VSSIO_PAD_ SBM_ADDR[20] UART_TX[1] VDDIO_PAD_ VDDIO_PAD_ SBM_ADDR[21] SPI_SCK[0] VSS_PAD_ VSS_PAD_ SBM_D[0] SPI_SSEL_0[0] VSSIO_PAD_ VSSIO_PAD_ SBM_D[1] SPI_SSEL_1[0] VDDIO_PAD_ VDDIO_PAD_ SBM_D[2] SPI_SSEL_2[0] VDD_PAD_ VDD_PAD_ SBM_D[3] SPI_SSEL_3[0] VSSIO_PAD_ VSSIO_PAD_ SBM_D[4] SPI_MOSI[0] VDDIO_PAD_ VDDIO_PAD_ SBM_D[5] SPI_MISO[0] VSS_PAD_ VSS_PAD_ SBM_D[6] SPI_SCK[1] VSSIO_PAD_ VSSIO_PAD_ SBM_D[7] SPI_SSEL_0[1] VDDIO_PAD_ VDDIO_PAD_ SBM_D[8] SPI_SSEL_1[1] VDD_PAD_ VDD_PAD_ Rev 1.0 page 10

11 34 SBM_D[9] SPI_SSEL_2[1] VSSIO_PAD_ VSSIO_PAD_ SBM_D[10] SPI_SSEL_3[1] VDDIO_PAD_ VDDIO_PAD_ SBM_D[11] SPI_MOSI[1] VSS_PAD_ VSS_PAD_ SBM_D[12] SPI_MISO[1] VSSIO_PAD_ VSSIO_PAD_ SBM_D[13] GPIO[0] VDDIO_PAD_ VDDIO_PAD_ SBM_D[14] GPIO[1] VDD_PAD_ VDD_PAD_ SBM_D[15] GPIO[2] VSSIO_PAD_ VSSIO_PAD_ CLK GPIO[3] VDDIO_PAD_ VDDIO_PAD_ SBM_D[16] GPIO[4] VSS_PAD_ VSS_PAD_ SBM_D[17] GPIO[5] VSSIO_PAD_ VSSIO_PAD_ SBM_D[18] GPIO[6] VDDIO_PAD_ VDDIO_PAD_ SBM_D[19] GPIO[7] VDD_PAD_ VDD_PAD_ SBM_D[20] GPIO[8] VSSIO_PAD_ VSSIO_PAD_ SBM_D[21] GPIO[9] VDDIO_PAD_ VDDIO_PAD_ SBM_D[22] GPIO[10] VSS_PAD_ VSS_PAD_ SBM_D[23] GPIO[11] VSSIO_PAD_ VSSIO_PAD_ SBM_D[24] GPIO[12] VDDIO_PAD_ VDDIO_PAD_ SBM_D[25] GPIO[13] VDD_PAD_ VDD_PAD_ SBM_D[26] GPIO[14] VSSIO_PAD_ VSSIO_PAD_ SBM_D[27] GPIO[15] VDDIO_PAD_ VDDIO_PAD_ SBM_D[28] GPIO[16] VSS_PAD_ VSS_PAD_ SBM_D[29] GPIO[17] VSSIO_PAD_ VSSIO_PAD_ Rev 1.0 page 11

12 78 SBM_D[30] GPIO[18] VDDIO_PAD_ VDDIO_PAD_ SBM_D[31] GPIO[19] VDD_PAD_ VDD_PAD_ SBM_P[0] GPIO[20] VSSIO_PAD_ VSSIO_PAD_ SBM_P[1] GPIO[21] VDDIO_PAD_ VDDIO_PAD_ SBM_P[2] GPIO[22] VSS_PAD_ VSS_PAD_ SBM_P[3] GPIO[23] VSSIO_PAD_ VSSIO_PAD_ SBM_OEn GPIO[24] VDDIO_PAD_ VDDIO_PAD_ SBM_SBEn GPIO[25] VDD_PAD_ VDD_PAD_ SBM_MBEn GPIO[26] VSSIO_PAD_ VSSIO_PAD_ SBM_PEn GPIO[27] VDDIO_PAD_ VDDIO_PAD_ SBM_INITn GPIO[28] VSS_PAD_ VSS_PAD_ SBM_ACKn GPIO[29] VSSIO_PAD_ VSSIO_PAD_ SBM_SYNC_BURST_CFG GPIO[30] VDDIO_PAD_ VDDIO_PAD_ SBM_EDAC_CFG GPIO[31] VDD_PAD_ VDD_PAD_ SBM_PAR_EN_CFG PARAMEN VSSIO_PAD_ VSSIO_PAD_ SBM_EVEN_PAR_CFG PARAMO VDDIO_PAD_ VDDIO_PAD_ MEM_RM IDDQ VSS_PAD_ VSS_PAD_ MEM_RWM SBM_RESETn VSSIO_PAD_ VSSIO_PAD_ MEM_WM SBM_ADSPn VDDIO_PAD_ VDDIO_PAD_ MEM_OLM SBM_CEn VDD_PAD_ VDD_PAD_ TCK SBM_WEn VSSIO_PAD_ VSSIO_PAD_ TMS SBM_BWEn[0] Rev 1.0 page 12

13 S 121 VDDIO_PAD_ VDDIO_PAD_ TRSTn SBM_BWEn[1] VSS_PAD_ VSS_PAD_ TDI SBM_BWEn[2] VSSIO_PAD_ VSSIO_PAD_ TDO SBM_BWEn[3] VDDIO_PAD_ VDDIO_PAD_ SCAN_EN SBM_ADDR[0] VDD_PAD_ VDD_PAD_ SCAN_MODE SBM_ADDR[1] VSSIO_PAD_ VSSIO_PAD_ EXTPORn SBM_ADDR[2] VDDIO_PAD_ VDDIO_PAD_ EXTMODE SBM_ADDR[3] VSS_PAD_ VSS_PAD_ EXTRESETn SBM_ADDR[4] VSSIO_PAD_ VSSIO_PAD_ POROUTn SBM_ADDR[5] VDDIO_PAD_ VDDIO_PAD_ ROM_SCK SBM_ADDR[6] VDD_PAD_ VDD_PAD_ ROM_CSn SBM_ADDR[7] VSSIO_PAD_ VSSIO_PAD_ ROM_SO SBM_ADDR[8] VDDIO_PAD_ VDDIO_PAD_ ROM_SI SBM_ADDR[9] VSS_PAD_ VSS_PAD_ ROM_SPEED[0] SBM_ADDR[10] VSSIO_PAD_ VSSIO_PAD_ ROM_SPEED[1] SBM_ADDR[11] VDDIO_PAD_ VDDIO_PAD_ ROM_DELAY[0] SBM_ADDR[12] VDD_PAD_ VDD_PAD_ ROM_DELAY[1] SBM_ADDR[13] VSSIO_PAD_ VSSIO_PAD_ ROM_DELAY[2] SBM_ADDR[14] Note: Die pad 1 is in lower left hand corner of die on the outer pad ring incrementing counterclockwise. Rev 1.0 page 13

14 5.2 Pad Layout with Marking in Upper Left Corner of Die Note: Upper Left Corner Metal Fill Missing + Layer Markings Rev 1.0 page 14

15 S 5.3 Reference Picture of Upper Left Corner of Die Note: Metal fill is missing in UPPER left corner of die (lighter area) with small layer text in metal. The other three sides have metal fill completely to the corner. Pad 1 is located in lower left corner of die. Rev 1.0 page 15

16 6 Ratings Tables (-D0000F0EAA & -CQ188F0EAA) 6.1 Absolute Maximum Ratings Symbol Rating Hi Rel Unit V dd1 DC supply -0.3 to 1.8 V voltage(core) V dd2 DC supply voltage -0.3 to 3.8 V (I/O) V I/O Voltage on any pin -0.3 to 3.8 V T CASE Operating -55 to 125 C Temperature T BIAS Temperature Under -55 to 125 C Bias T STG Storage Temperature -55 to 125 C 6.2 Recommended Supply Operating Condition Grade Temperature VSS VDD VDDIO Mil 125C -55 to 125C 0V 1.5V +/- 10% 3.3V +/-10% 6.3 Recommended Supply Conditions Symbol Parameter Min Typ Max Unit VDD Core Supply V VDDIO I/O Supply Voltage V VSS Ground V V ramp1 VDD voltage ramp time us V ramp2 VDDIO voltage ramp time us V PROFF1 VDD level at which the Power-On-Reset is released V V PROFF2 V PRON1 V PRON2 Notes: VDDIO level at which the Power-On-Reset is released V VDD level at which the Power-On-Reset is V activated 3 VDDIO level at which the Power-On-Reset is V activated 3 Rev 1.0 page 16

17 S 1. Ramp time is the time from VDD/VDDIO at 0V until it reaches the operating range. The Maximum value will depend on t DBT (Boot Delay) and the Clock frequency (if clock is running during power the power up sequence). 2. V PROFF is the voltage at which the internal Power-on-Reset is released when power is rising. The EFuse and boot delay logic both begin operating at this point and will operate correctly at this reduced voltage. The programmed boot delay needs to be specified so that t DBT is sufficient for the VDD and VDDIO to have reached the operating range in the specified time, for the rest of the device to operate correctly. 3. V PRON is the voltage at which the internal Power-on-Reset is activated when power is falling or during a VDD glitch. 4. t DBT can be reconfigured through Efuse data using the JTAG port. Rev 1.0 page 17

18 6.4 Signal Pads Operating Conditions This applies to all signal pads except. Symbol Parameter Test Conditions Min. Max. Unit V IL Input Low Voltage V V IH Input High Voltage 2.0 VDDIO V +0.3 Il Input leakage current (each IO VDDIO= Max ua pin) Vin= 0V to VDDIO I OL Low level sink current V OL=0.4V, VDD= Min 8.0 ma I OH High level source current V OH=2.4V, VDD= Min 8.0 ma V OL Output Low Voltage Iol= +8mA, VDD= Min 0.4 V V OH Output High Voltage Ioh= -8mA, VDD= Min 2.4 V Rev 1.0 page 18

19 6.5 DC Current Consumption Symbol Condition Device Typ 1 WCPOW 2 Supply Unit I Idd Max Core Current at VDD ma 50Mhz I ISB Quiescent Current 3 80 VDD ua 120 VDD ua Notes: 1. Typical conditions are 25C, VDD=1.5, VDDIO=3.3, typical/typical process 2. WCPOW condition is 125C, VDD=1.65V, VDDIO=3.63V, typical/typical process 3. External clock stopped, all chip level inputs in a constant state, pull-ups/pull-downs not active (or not in conflict with the driven or applied levels), and no DC load on any outputs. 6.6 Internal Weak Pull-up/Pull-down Typ Units Value Pull-up 33 Kohms Pull-down 33 Kohms Notes: 1. Pins with dedicated Pull-ups: TMS, TRSTn, TDI 2. Pins with software configurable Pulls: GPIO[31:0] pin CQFP Pin Capacitance Symbol Parameter Conditions Max Unit C IN Input Capacitance Vin = 3 V 8.8 pf C I/O I/O Capacitance Vout = 3V 17 pf Rev 1.0 page 19

20 7 AC Electrical Characteristics 7.1 AC Timing Conditions VDD 1.5V +/- 10% VDDIO 3.3V +/- 10% Input Swing Levels 0 to 3.3V Input Rise/Fall Times 1-4 ns 1 Input Timing Reference Levels 1.65V Output Timing Reference 1.65V Levels AC Test Load 20pf Notes: 1. Rise/Fall times are measured from 20% to 80% of VDDIO Output delay derating for loads The following table shows the effect of various output loads on the output data valid timing: Load t DV (Min 1 ) t DV (Typ 1 ) t DV (Max 1 ) Units 5pf A-0.7 B-0.6 C-1.0 ns 20pf A 2 B 2 C 2 ns 35pf A+0.8 B+0.6 C+0.8 ns Notes: 1. Delay Value over normal operating conditions: a. Best case military (-55C, VDD+10%, fast/fast process) b. Typical (25C, VDD, typical/typical process) c. Worst case military (125C, VDD-10%, slow/slow process) 2. A, B, and C represent the reference delay values for a given IO signals (at 20pf Load) 7.2 General Signals Timing Parameter Description Min 2 Typical 3 Max 4 Unit Clock t CYC Clock cycle time (min) ns t CH Clock high ns t CL Clock low ns Setup Times 1 t CRESETS EXTRESETn setup before CLK rise ns Rev 1.0 page 20

21 S Hold Times 1 t CRESETH EXTRESETn hold after CLK rise ns Notes: 1. All timing parameters are the max delay unless noted. Where the parameter applies to multiple signals some of them may have a less stringent requirement. 2. Min timing conditions are -55C, 1.65V, fast/fast process 3. Typical timing conditions are 25C, 1.5V, typical/typical process 4. Max timing conditions are 125C, 1.35V, slow/slow process 7.3 Sync Burst Memory Interface Timing Symbol Parameter Min 2 Typical 3 Max 4 Unit Output Times 1 t CR SBM_RESETn valid after CLK rise ns t CADSP SBM_ADSPn valid after CLK rise ns t CCE SBM_CEn valid after CLK rise ns t CWE SBM_WEn valid after CLK rise ns t CBWE SBM_BWEn valid after CLK rise ns t CADDR SBM_ADDR valid after CLK rise ns t CDATA SBM_DATA valid after CLK rise ns t CPAR SBM_P valid after CLK rise ns t CCFG SBM Config outputs valid after CLK rise ns t CACK SBM_ACKn valid after CLK rise ns Rev 1.0 page 21

22 S Setup Times 1 t CINITS SBM_INITn setup before CLK rise ns t CDS SBM_DATA setup before CLK rise ns t CPS SBM_P setup before CLK rise ns t CSBES SBM_SBEn setup before CLK rise ns t CMBES SBM_MBEs setup before CLK rise ns Hold Times 1 t CDH SBM_DATA hold after CLK rise ns t CPH SBM_P hold after CLK rise ns t CSBEH SBM_SBEn hold after CLK rise ns t CMBEH SBM_MBEs hold after CLK rise ns Notes: 1. All timing parameters are the max delay unless noted. Where the parameter applies to multiple signals some of them may have a less stringent requirement. 2. Min timing conditions are -55C, 1.65V, fast/fast process 3. Typical timing conditions are 25C, 1.5V, typical/typical process 4. Max timing conditions are 125C, 1.35V, slow/slow process Rev 1.0 page 22

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24 S 7.4 GPIO Timing Parameter Description Min 2 Typical 3 Max 4 Unit Output Times 1 t CGPIO GPIO valid after CLK rise ns Setup Times 1,5 t CGPIOS ns Hold Times 1,5 t CGPIOH GPIO hold after CLK rise ns Notes: 1. All timing parameters are the max delay unless noted. Where the parameter applies to multiple signals some of them may have a less stringent requirement. 2. Min timing conditions are -55C, 1.65V, fast/fast process 3. Typical timing conditions are 25C, 1.5V, typical/typical process 4. Max timing conditions are 125C, 1.35V, slow/slow process 5. Setup and Hold times apply when GPIO pin synchronization is disabled. Rev 1.0 page 24

25 S 7.5 SPI ROM Timing Parameter Description Min 2 Typical 3 Max 4 Unit Output Times 1,5 t CSC ROM_CSn valid after CLK rise ns t CSCK ROM_SCK valid after CLK rise ns t CSO ROM_SO valid after CLK rise ns Setup Times 1,6 t CSIS ns Hold Times 1,6 t CSIH GPIO hold after CLK rise ns Notes: 1. All timing parameters are the max delay unless noted. Where the parameter applies to multiple signals some of them may have a less stringent requirement. 2. Min timing conditions are -55C, 1.65V, fast/fast process 3. Typical timing conditions are 25C, 1.5V, typical/typical process 4. Max timing conditions are 125C, 1.35V, slow/slow process 5. The ROM_SO signal is enabled on the cycles that ROM_SCn is low, and ROM_SO changes on the cycles that ROM_SCK falls. 6. The ROM_SI signal is captured on the rising edge of CLK on the cycles that ROM_SCK will be rising at the output. Rev 1.0 page 25

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27 S 7.6 SPI Interface Configured as SPI Master Timing Parameter Description Min 2 Typical 3 Max 4 Unit Output Times 1,5 t CSEL SPI_SEL_x valid after CLK rise ns t CSCK SPI_SCK valid after CLK rise ns t CMOSI SPI_MOSI valid after CLK rise ns Setup Times 1,6 t CMISOS SPI_MISO setup before CLK rise ns Hold Times 1,6 t CMISOH SPI_MISO hold after CLK rise ns Notes: 1. All timing parameters are the max delay unless noted. Where the parameter applies to multiple signals some of them may have a less stringent requirement. 2. Min timing conditions are -55C, 1.65V, fast/fast process 3. Typical timing conditions are 25C, 1.5V, typical/typical process 4. Max timing conditions are 125C, 1.35V, slow/slow process 5. The SPI_MOSI signal is enabled on the cycles that SPI_SSEL_x is low, and SPI_MOSI changes on the cycles that SPI_SCK falls. 6. The SPI_MISO signal is captured on the rising edge of CLK on the cycles that SPI_SCK will be rising at the output. Rev 1.0 page 27

28 Rev 1.0 page 28

29 7.7 SPI Interface Configured as SPI Slave Parameter Description Min Max Clock 1 t SCKCYC SPI_SCK Cycle time 8 cycles of CLK Output Times 2 t SCKMISO SPI_MISO valid after SPI_SCK fall 2 cycles of CLK 3 cycles of CLK + 15ns Setup Times t SDKMOSIH SPI_MOSI setup before SPI_SCK rise 0 cycle of CLK 0 cycle of CLK Hold Times t SDKMOSIH SPI_MOSI hold after SPI_SCK rise 1 cycle of CLK 3 cycles of CLK Notes: 1. The Cycle time of SPI_SCK must be at least 8x the CLK period. 2. Output/Setup/Hold times are a function of the number of CLK cycles. Rev 1.0 page 29

30 8 Radiation Hardened Performance Parameter Description Min Typ Max Unit TID Total Ionizing Dose 300K - - rad (Si) SER Soft Error Rate (EDAC disabled) 1.3e errors / bit / day* SER Soft Error Rate (EDAC enabled) 1e errors / bit / day* LET Linear Energy Transfer (latch-up immunity) MeV-cm2 / mg *Geosynchronous orbit solar min. with 100 mils of Al shielding With EDAC enabled, the Scrub Engine should also be enabled and running at an appropriate frequency to prevent accumulation of errors in the memory in order to achieve consistently low SER over time. Rev 1.0 page 30

31 9 Package Drawing Pin Ceramic Quad Flat Package Rev 1.0 page 31

32 10 Ordering Information Part Number Environment Package -CQ188F0EAA Radiation Ceramic -D0000F0EAA Radiation Die -CQ18803EAA High Temp Ceramic (>=200C) Aluminum Wedge -CQ18802EAA High Temp Ceramic (<175C) Gold Ball -D000003EAA High Temp Die >=200C) Rev 1.0 page 32

33 11 Revision History Date Version Page Description Locations 10/19/ Initial Revision 12/17/ Updated block diagram and added power table 10/8/ Complete update. 11/7/ Style update and pin description updates 2/3/ Added missing Pin POROUTn 4/24/ Style updates 5/28/ OpCond updates 6/4/ Update clock cycle times 8/13/ Added Package Drawing 9/16/ , 5 Added description of GPIO, SPI, and UART pins at power-up and reset. Updated description of pin EXTMODE 3/31/ pg Added Die Option Section 5 pg 10-15, Changed Order Info 5/6/ Clarify EXTMODE pins description. Updated descriptions for TCK and TRSTn. Added missing pin descriptions for MEM_xx pins. 9/16/ Style updates for Vorago template 10/5/ Style updates to Rating Tables, and AC Electrical Characteristics sections 10/21/ Updated part numbers: A -> PA11S/PA12S Updated Ordering Information 12/16/ Updated part number to 4/4/2016 Rev Add radiation specifications Remove data on PA32KBSA 4/12/2016 Rev1.1 2, 16, 20 Corrected inconsistencies in temperature specification VORAGO Technologies standard terms and conditions of sale: VORAGO Technologies 1501 S MoPac Expressway, Suite #350 Austin, TX info@voragotech.com Phone: (512) Rev 1.0 page 33